mirror of https://github.com/hak5/openwrt.git
172 lines
3.6 KiB
Diff
172 lines
3.6 KiB
Diff
From 5644da4f635a30fc03b4f12d81b2197d716d9cef Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 22 Jan 2013 20:19:33 +0100
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Subject: [PATCH 09/14] MIPS: ralink: adds rt305x devicetree
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This adds the devicetree file that describes the rt305x evaluation kit.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/4898/
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---
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arch/mips/ralink/dts/rt3050.dtsi | 96 ++++++++++++++++++++++++++++++++++
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arch/mips/ralink/dts/rt3052_eval.dts | 52 ++++++++++++++++++
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2 files changed, 148 insertions(+)
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create mode 100644 arch/mips/ralink/dts/rt3050.dtsi
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create mode 100644 arch/mips/ralink/dts/rt3052_eval.dts
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--- /dev/null
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+++ b/arch/mips/ralink/dts/rt3050.dtsi
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@@ -0,0 +1,96 @@
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "ralink,rt3050-soc", "ralink,rt3052-soc";
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+
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+ cpus {
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+ cpu@0 {
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+ compatible = "mips,mips24KEc";
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+ };
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+ };
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+
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+ chosen {
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+ bootargs = "console=ttyS0,57600 init=/init";
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+ };
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+
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+ palmbus@10000000 {
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+ compatible = "palmbus";
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+ reg = <0x10000000 0x200000>;
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+ ranges = <0x0 0x10000000 0x1FFFFF>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ sysc@0 {
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+ compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc";
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+ reg = <0x0 0x100>;
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+ };
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+
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+ timer@100 {
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+ compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
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+ reg = <0x100 0x100>;
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+ };
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+
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+ intc: intc@200 {
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+ compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
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+ reg = <0x200 0x100>;
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+
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+ };
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+
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+ memc@300 {
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+ compatible = "ralink,rt3052-memc", "ralink,rt3050-memc";
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+ reg = <0x300 0x100>;
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+ };
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+
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+ gpio0: gpio@600 {
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+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
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+ reg = <0x600 0x34>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,ngpio = <24>;
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+ ralink,regs = [ 00 04 08 0c
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+ 20 24 28 2c
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+ 30 34 ];
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+ };
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+
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+ gpio1: gpio@638 {
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+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
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+ reg = <0x638 0x24>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,ngpio = <16>;
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+ ralink,regs = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+ };
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+
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+ gpio2: gpio@660 {
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+ compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
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+ reg = <0x660 0x24>;
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+
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+
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+ ralink,ngpio = <12>;
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+ ralink,regs = [ 00 04 08 0c
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+ 10 14 18 1c
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+ 20 24 ];
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+ };
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+
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+ uartlite@c00 {
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+ compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
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+ reg = <0xc00 0x100>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <12>;
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+
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+ reg-shift = <2>;
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+ };
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+ };
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+};
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--- /dev/null
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+++ b/arch/mips/ralink/dts/rt3052_eval.dts
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@@ -0,0 +1,52 @@
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+/dts-v1/;
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+
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+/include/ "rt3050.dtsi"
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+
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "ralink,rt3052-eval-board", "ralink,rt3052-soc";
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+ model = "Ralink RT3052 evaluation board";
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+
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+ memory@0 {
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+ reg = <0x0 0x2000000>;
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+ };
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+
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+ palmbus@10000000 {
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+ sysc@0 {
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+ ralink,pinmux = "uartlite", "spi";
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+ ralink,uartmux = "gpio";
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+ ralink,wdtmux = <0>;
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+ };
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+ };
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+
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+ cfi@1f000000 {
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+ compatible = "cfi-flash";
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+ reg = <0x1f000000 0x800000>;
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+
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+ bank-width = <2>;
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+ device-width = <2>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "uboot";
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+ reg = <0x0 0x30000>;
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+ read-only;
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+ };
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+ partition@30000 {
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+ label = "uboot-env";
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+ reg = <0x30000 0x10000>;
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+ read-only;
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+ };
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+ partition@40000 {
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+ label = "calibration";
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+ reg = <0x40000 0x10000>;
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+ read-only;
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+ };
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+ partition@50000 {
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+ label = "linux";
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+ reg = <0x50000 0x7b0000>;
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+ };
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+ };
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+};
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