mirror of https://github.com/hak5/openwrt.git
352 lines
9.2 KiB
Diff
352 lines
9.2 KiB
Diff
Content-Type: text/plain; charset="utf-8"
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MIME-Version: 1.0
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Content-Transfer-Encoding: 7bit
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Subject: [v3,05/13] clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
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From: Stephen Boyd <sboyd@codeaurora.org>
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X-Patchwork-Id: 6063261
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Message-Id: <1426920332-9340-6-git-send-email-sboyd@codeaurora.org>
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To: Mike Turquette <mturquette@linaro.org>, Stephen Boyd <sboyd@codeaurora.org>
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Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
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linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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Viresh Kumar <viresh.kumar@linaro.org>
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Date: Fri, 20 Mar 2015 23:45:24 -0700
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HFPLLs are the main frequency source for Krait CPU clocks. Add
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support for changing the rate of these PLLs.
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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I'd really like to get rid of __clk_hfpll_init_once() if possible...
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drivers/clk/qcom/Makefile | 1 +
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drivers/clk/qcom/clk-hfpll.c | 253 +++++++++++++++++++++++++++++++++++++++++++
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drivers/clk/qcom/clk-hfpll.h | 54 +++++++++
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3 files changed, 308 insertions(+)
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create mode 100644 drivers/clk/qcom/clk-hfpll.c
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create mode 100644 drivers/clk/qcom/clk-hfpll.h
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--- a/drivers/clk/qcom/Makefile
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+++ b/drivers/clk/qcom/Makefile
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@@ -8,6 +8,7 @@ clk-qcom-y += clk-rcg2.o
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clk-qcom-y += clk-branch.o
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clk-qcom-y += clk-regmap-divider.o
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clk-qcom-y += clk-regmap-mux.o
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+clk-qcom-y += clk-hfpll.o
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clk-qcom-y += reset.o
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clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
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--- /dev/null
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+++ b/drivers/clk/qcom/clk-hfpll.c
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@@ -0,0 +1,253 @@
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+/*
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+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+#include <linux/kernel.h>
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+#include <linux/export.h>
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+#include <linux/regmap.h>
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+#include <linux/delay.h>
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+#include <linux/err.h>
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+#include <linux/clk-provider.h>
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+#include <linux/spinlock.h>
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+
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+#include "clk-regmap.h"
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+#include "clk-hfpll.h"
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+
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+#define PLL_OUTCTRL BIT(0)
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+#define PLL_BYPASSNL BIT(1)
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+#define PLL_RESET_N BIT(2)
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+
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+/* Initialize a HFPLL at a given rate and enable it. */
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+static void __clk_hfpll_init_once(struct clk_hw *hw)
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+{
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+ struct clk_hfpll *h = to_clk_hfpll(hw);
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+ struct hfpll_data const *hd = h->d;
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+ struct regmap *regmap = h->clkr.regmap;
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+
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+ if (likely(h->init_done))
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+ return;
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+
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+ /* Configure PLL parameters for integer mode. */
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+ if (hd->config_val)
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+ regmap_write(regmap, hd->config_reg, hd->config_val);
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+ regmap_write(regmap, hd->m_reg, 0);
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+ regmap_write(regmap, hd->n_reg, 1);
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+
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+ if (hd->user_reg) {
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+ u32 regval = hd->user_val;
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+ unsigned long rate;
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+
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+ rate = clk_hw_get_rate(hw->clk);
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+
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+ /* Pick the right VCO. */
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+ if (hd->user_vco_mask && rate > hd->low_vco_max_rate)
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+ regval |= hd->user_vco_mask;
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+ regmap_write(regmap, hd->user_reg, regval);
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+ }
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+
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+ if (hd->droop_reg)
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+ regmap_write(regmap, hd->droop_reg, hd->droop_val);
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+
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+ h->init_done = true;
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+}
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+
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+static void __clk_hfpll_enable(struct clk_hw *hw)
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+{
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+ struct clk_hfpll *h = to_clk_hfpll(hw);
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+ struct hfpll_data const *hd = h->d;
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+ struct regmap *regmap = h->clkr.regmap;
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+ u32 val;
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+
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+ __clk_hfpll_init_once(hw);
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+
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+ /* Disable PLL bypass mode. */
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+ regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL);
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+
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+ /*
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+ * H/W requires a 5us delay between disabling the bypass and
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+ * de-asserting the reset. Delay 10us just to be safe.
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+ */
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+ udelay(10);
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+
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+ /* De-assert active-low PLL reset. */
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+ regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
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+
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+ /* Wait for PLL to lock. */
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+ if (hd->status_reg) {
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+ do {
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+ regmap_read(regmap, hd->status_reg, &val);
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+ } while (!(val & BIT(hd->lock_bit)));
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+ } else {
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+ udelay(60);
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+ }
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+
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+ /* Enable PLL output. */
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+ regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);
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+}
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+
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+/* Enable an already-configured HFPLL. */
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+static int clk_hfpll_enable(struct clk_hw *hw)
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+{
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+ unsigned long flags;
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+ struct clk_hfpll *h = to_clk_hfpll(hw);
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+ struct hfpll_data const *hd = h->d;
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+ struct regmap *regmap = h->clkr.regmap;
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+ u32 mode;
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+
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+ spin_lock_irqsave(&h->lock, flags);
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+ regmap_read(regmap, hd->mode_reg, &mode);
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+ if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)))
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+ __clk_hfpll_enable(hw);
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+ spin_unlock_irqrestore(&h->lock, flags);
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+
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+ return 0;
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+}
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+
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+static void __clk_hfpll_disable(struct clk_hfpll *h)
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+{
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+ struct hfpll_data const *hd = h->d;
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+ struct regmap *regmap = h->clkr.regmap;
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+
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+ /*
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+ * Disable the PLL output, disable test mode, enable the bypass mode,
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+ * and assert the reset.
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+ */
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+ regmap_update_bits(regmap, hd->mode_reg,
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+ PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0);
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+}
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+
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+static void clk_hfpll_disable(struct clk_hw *hw)
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+{
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+ struct clk_hfpll *h = to_clk_hfpll(hw);
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&h->lock, flags);
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+ __clk_hfpll_disable(h);
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+ spin_unlock_irqrestore(&h->lock, flags);
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+}
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+
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+static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long *parent_rate)
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+{
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+ struct clk_hfpll *h = to_clk_hfpll(hw);
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+ struct hfpll_data const *hd = h->d;
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+ unsigned long rrate;
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+
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+ rate = clamp(rate, hd->min_rate, hd->max_rate);
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+
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+ rrate = DIV_ROUND_UP(rate, *parent_rate) * *parent_rate;
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+ if (rrate > hd->max_rate)
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+ rrate -= *parent_rate;
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+
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+ return rrate;
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+}
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+
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+/*
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+ * For optimization reasons, assumes no downstream clocks are actively using
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+ * it.
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+ */
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+static int clk_hfpll_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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+{
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+ struct clk_hfpll *h = to_clk_hfpll(hw);
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+ struct hfpll_data const *hd = h->d;
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+ struct regmap *regmap = h->clkr.regmap;
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+ unsigned long flags;
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+ u32 l_val, val;
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+ bool enabled;
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+
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+ l_val = rate / parent_rate;
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+
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+ spin_lock_irqsave(&h->lock, flags);
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+
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+ enabled = __clk_is_enabled(hw->clk);
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+ if (enabled)
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+ __clk_hfpll_disable(h);
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+
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+ /* Pick the right VCO. */
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+ if (hd->user_reg && hd->user_vco_mask) {
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+ regmap_read(regmap, hd->user_reg, &val);
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+ if (rate <= hd->low_vco_max_rate)
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+ val &= ~hd->user_vco_mask;
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+ else
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+ val |= hd->user_vco_mask;
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+ regmap_write(regmap, hd->user_reg, val);
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+ }
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+
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+ regmap_write(regmap, hd->l_reg, l_val);
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+
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+ if (enabled)
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+ __clk_hfpll_enable(hw);
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+
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+ spin_unlock_irqrestore(&h->lock, flags);
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+
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+ return 0;
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+}
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+
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+static unsigned long clk_hfpll_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ struct clk_hfpll *h = to_clk_hfpll(hw);
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+ struct hfpll_data const *hd = h->d;
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+ struct regmap *regmap = h->clkr.regmap;
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+ u32 l_val;
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+
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+ regmap_read(regmap, hd->l_reg, &l_val);
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+
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+ return l_val * parent_rate;
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+}
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+
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+static void clk_hfpll_init(struct clk_hw *hw)
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+{
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+ struct clk_hfpll *h = to_clk_hfpll(hw);
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+ struct hfpll_data const *hd = h->d;
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+ struct regmap *regmap = h->clkr.regmap;
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+ u32 mode, status;
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+
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+ regmap_read(regmap, hd->mode_reg, &mode);
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+ if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) {
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+ __clk_hfpll_init_once(hw);
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+ return;
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+ }
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+
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+ if (hd->status_reg) {
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+ regmap_read(regmap, hd->status_reg, &status);
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+ if (!(status & BIT(hd->lock_bit))) {
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+ WARN(1, "HFPLL %s is ON, but not locked!\n",
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+ __clk_get_name(hw->clk));
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+ clk_hfpll_disable(hw);
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+ __clk_hfpll_init_once(hw);
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+ }
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+ }
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+}
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+
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+static int hfpll_is_enabled(struct clk_hw *hw)
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+{
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+ struct clk_hfpll *h = to_clk_hfpll(hw);
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+ struct hfpll_data const *hd = h->d;
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+ struct regmap *regmap = h->clkr.regmap;
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+ u32 mode;
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+
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+ regmap_read(regmap, hd->mode_reg, &mode);
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+ mode &= 0x7;
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+ return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL);
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+}
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+
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+const struct clk_ops clk_ops_hfpll = {
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+ .enable = clk_hfpll_enable,
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+ .disable = clk_hfpll_disable,
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+ .is_enabled = hfpll_is_enabled,
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+ .round_rate = clk_hfpll_round_rate,
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+ .set_rate = clk_hfpll_set_rate,
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+ .recalc_rate = clk_hfpll_recalc_rate,
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+ .init = clk_hfpll_init,
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+};
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+EXPORT_SYMBOL_GPL(clk_ops_hfpll);
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--- /dev/null
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+++ b/drivers/clk/qcom/clk-hfpll.h
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@@ -0,0 +1,54 @@
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+/*
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+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+#ifndef __QCOM_CLK_HFPLL_H__
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+#define __QCOM_CLK_HFPLL_H__
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+
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+#include <linux/clk-provider.h>
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+#include <linux/spinlock.h>
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+#include "clk-regmap.h"
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+
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+struct hfpll_data {
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+ u32 mode_reg;
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+ u32 l_reg;
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+ u32 m_reg;
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+ u32 n_reg;
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+ u32 user_reg;
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+ u32 droop_reg;
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+ u32 config_reg;
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+ u32 status_reg;
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+ u8 lock_bit;
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+
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+ u32 droop_val;
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+ u32 config_val;
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+ u32 user_val;
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+ u32 user_vco_mask;
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+ unsigned long low_vco_max_rate;
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+
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+ unsigned long min_rate;
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+ unsigned long max_rate;
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+};
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+
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+struct clk_hfpll {
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+ struct hfpll_data const *d;
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+ int init_done;
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+
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+ struct clk_regmap clkr;
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+ spinlock_t lock;
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+};
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+
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+#define to_clk_hfpll(_hw) \
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+ container_of(to_clk_regmap(_hw), struct clk_hfpll, clkr)
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+
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+extern const struct clk_ops clk_ops_hfpll;
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+
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+#endif
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