mirror of https://github.com/hak5/openwrt.git
227 lines
6.3 KiB
Diff
227 lines
6.3 KiB
Diff
From 3cdd9f5c4953465abb87ec757159cc0576ae6b0a Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Sat, 5 Dec 2015 21:16:43 +0800
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Subject: [PATCH] clk: sunxi: Add VE (Video Engine) module clock driver for
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sun[457]i
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The video engine has its own special module clock, consisting of a clock
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gate, configurable dividers, and a reset control.
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On later (sun[68]i) families, the reset control is moved out of this
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piece of hardware and grouped with reset controls of other peripherals.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Tested-by: Jens Kuske <jenskuske@gmail.com>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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Documentation/devicetree/bindings/clock/sunxi.txt | 4 +
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drivers/clk/sunxi/Makefile | 1 +
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drivers/clk/sunxi/clk-a10-ve.c | 171 ++++++++++++++++++++++
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3 files changed, 176 insertions(+)
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create mode 100644 drivers/clk/sunxi/clk-a10-ve.c
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--- a/Documentation/devicetree/bindings/clock/sunxi.txt
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+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
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@@ -71,6 +71,7 @@ Required properties:
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"allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
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"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
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"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
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+ "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
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Required properties for all clocks:
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- reg : shall be the control register address for the clock.
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@@ -90,6 +91,9 @@ Required properties for all clocks:
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And "allwinner,*-usb-clk" clocks also require:
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- reset-cells : shall be set to 1
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+The "allwinner,sun4i-a10-ve-clk" clock also requires:
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+- reset-cells : shall be set to 0
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+
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The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
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- #reset-cells : shall be set to 1
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- resets : shall be the reset control phandle for the mmc block.
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--- a/drivers/clk/sunxi/Makefile
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+++ b/drivers/clk/sunxi/Makefile
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@@ -7,6 +7,7 @@ obj-y += clk-a10-codec.o
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obj-y += clk-a10-hosc.o
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obj-y += clk-a10-mod1.o
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obj-y += clk-a10-pll2.o
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+obj-y += clk-a10-ve.o
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obj-y += clk-a20-gmac.o
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obj-y += clk-mod0.o
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obj-y += clk-simple-gates.o
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--- /dev/null
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+++ b/drivers/clk/sunxi/clk-a10-ve.c
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@@ -0,0 +1,171 @@
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+/*
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+ * Copyright 2015 Chen-Yu Tsai
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+ *
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+ * Chen-Yu Tsai <wens@csie.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/clk-provider.h>
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+#include <linux/of.h>
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+#include <linux/of_address.h>
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+#include <linux/reset-controller.h>
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+#include <linux/slab.h>
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+#include <linux/spinlock.h>
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+
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+static DEFINE_SPINLOCK(ve_lock);
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+
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+#define SUN4I_VE_ENABLE 31
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+#define SUN4I_VE_DIVIDER_SHIFT 16
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+#define SUN4I_VE_DIVIDER_WIDTH 3
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+#define SUN4I_VE_RESET 0
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+
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+/**
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+ * sunxi_ve_reset... - reset bit in ve clk registers handling
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+ */
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+
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+struct ve_reset_data {
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+ void __iomem *reg;
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+ spinlock_t *lock;
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+ struct reset_controller_dev rcdev;
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+};
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+
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+static int sunxi_ve_reset_assert(struct reset_controller_dev *rcdev,
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+ unsigned long id)
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+{
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+ struct ve_reset_data *data = container_of(rcdev,
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+ struct ve_reset_data,
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+ rcdev);
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+ unsigned long flags;
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+ u32 reg;
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+
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+ spin_lock_irqsave(data->lock, flags);
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+
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+ reg = readl(data->reg);
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+ writel(reg & ~BIT(SUN4I_VE_RESET), data->reg);
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+
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+ spin_unlock_irqrestore(data->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int sunxi_ve_reset_deassert(struct reset_controller_dev *rcdev,
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+ unsigned long id)
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+{
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+ struct ve_reset_data *data = container_of(rcdev,
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+ struct ve_reset_data,
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+ rcdev);
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+ unsigned long flags;
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+ u32 reg;
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+
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+ spin_lock_irqsave(data->lock, flags);
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+
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+ reg = readl(data->reg);
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+ writel(reg | BIT(SUN4I_VE_RESET), data->reg);
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+
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+ spin_unlock_irqrestore(data->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int sunxi_ve_of_xlate(struct reset_controller_dev *rcdev,
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+ const struct of_phandle_args *reset_spec)
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+{
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+ if (WARN_ON(reset_spec->args_count != 0))
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+ return -EINVAL;
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+
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+ return 0;
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+}
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+
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+static struct reset_control_ops sunxi_ve_reset_ops = {
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+ .assert = sunxi_ve_reset_assert,
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+ .deassert = sunxi_ve_reset_deassert,
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+};
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+
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+static void __init sun4i_ve_clk_setup(struct device_node *node)
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+{
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+ struct clk *clk;
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+ struct clk_divider *div;
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+ struct clk_gate *gate;
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+ struct ve_reset_data *reset_data;
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+ const char *parent;
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+ const char *clk_name = node->name;
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+ void __iomem *reg;
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+ int err;
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+
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+ reg = of_io_request_and_map(node, 0, of_node_full_name(node));
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+ if (IS_ERR(reg))
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+ return;
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+
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+ div = kzalloc(sizeof(*div), GFP_KERNEL);
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+ if (!div)
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+ goto err_unmap;
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+
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+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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+ if (!gate)
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+ goto err_free_div;
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+
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+ of_property_read_string(node, "clock-output-names", &clk_name);
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+ parent = of_clk_get_parent_name(node, 0);
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+
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+ gate->reg = reg;
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+ gate->bit_idx = SUN4I_VE_ENABLE;
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+ gate->lock = &ve_lock;
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+
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+ div->reg = reg;
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+ div->shift = SUN4I_VE_DIVIDER_SHIFT;
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+ div->width = SUN4I_VE_DIVIDER_WIDTH;
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+ div->lock = &ve_lock;
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+
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+ clk = clk_register_composite(NULL, clk_name, &parent, 1,
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+ NULL, NULL,
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+ &div->hw, &clk_divider_ops,
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+ &gate->hw, &clk_gate_ops,
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+ CLK_SET_RATE_PARENT);
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+ if (IS_ERR(clk))
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+ goto err_free_gate;
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+
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+ err = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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+ if (err)
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+ goto err_unregister_clk;
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+
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+ reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
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+ if (!reset_data)
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+ goto err_del_provider;
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+
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+ reset_data->reg = reg;
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+ reset_data->lock = &ve_lock;
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+ reset_data->rcdev.nr_resets = 1;
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+ reset_data->rcdev.ops = &sunxi_ve_reset_ops;
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+ reset_data->rcdev.of_node = node;
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+ reset_data->rcdev.of_xlate = sunxi_ve_of_xlate;
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+ reset_data->rcdev.of_reset_n_cells = 0;
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+ err = reset_controller_register(&reset_data->rcdev);
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+ if (err)
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+ goto err_free_reset;
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+
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+ return;
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+
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+err_free_reset:
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+ kfree(reset_data);
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+err_del_provider:
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+ of_clk_del_provider(node);
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+err_unregister_clk:
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+ clk_unregister(clk);
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+err_free_gate:
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+ kfree(gate);
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+err_free_div:
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+ kfree(div);
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+err_unmap:
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+ iounmap(reg);
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+}
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+CLK_OF_DECLARE(sun4i_ve, "allwinner,sun4i-a10-ve-clk",
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+ sun4i_ve_clk_setup);
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