mirror of https://github.com/hak5/openwrt.git
421 lines
11 KiB
Diff
421 lines
11 KiB
Diff
From 6912e27d97ba5671e8c2434bed0ebd23fde5e13d Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Wed, 18 Jun 2014 14:29:29 -0700
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Subject: [PATCH 171/182] clk: qcom: Add Krait clock controller driver
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The Krait CPU clocks are made up of a primary mux and secondary
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mux for each CPU and the L2, controlled via cp15 accessors. For
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Kraits within KPSSv1 each secondary mux accepts a different aux
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source, but on KPSSv2 each secondary mux accepts the same aux
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source.
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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drivers/clk/qcom/Kconfig | 8 +
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drivers/clk/qcom/Makefile | 1 +
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drivers/clk/qcom/krait-cc.c | 364 +++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 373 insertions(+)
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create mode 100644 drivers/clk/qcom/krait-cc.c
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diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
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index e9e5360..7418108 100644
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--- a/drivers/clk/qcom/Kconfig
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+++ b/drivers/clk/qcom/Kconfig
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@@ -70,6 +70,14 @@ config KPSS_XCC
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if you want to support CPU frequency scaling on devices such
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as MSM8960, APQ8064, etc.
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+config KRAITCC
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+ tristate "Krait Clock Controller"
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+ depends on COMMON_CLK_QCOM && ARM
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+ select KRAIT_CLOCKS
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+ help
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+ Support for the Krait CPU clocks on Qualcomm devices.
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+ Say Y if you want to support CPU frequency scaling.
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+
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config KRAIT_CLOCKS
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bool
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select KRAIT_L2_ACCESSORS
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diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
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index 29b2a45..1b88abe 100644
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--- a/drivers/clk/qcom/Makefile
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+++ b/drivers/clk/qcom/Makefile
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@@ -19,3 +19,4 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
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obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
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obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
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obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
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+obj-$(CONFIG_KRAITCC) += krait-cc.o
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diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
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new file mode 100644
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index 0000000..90985ea
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--- /dev/null
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+++ b/drivers/clk/qcom/krait-cc.c
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@@ -0,0 +1,364 @@
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+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 and
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+ * only version 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/of.h>
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+#include <linux/of_device.h>
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+#include <linux/clk.h>
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+#include <linux/clk-provider.h>
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+#include <linux/slab.h>
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+
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+#include <asm/smp_plat.h>
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+
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+#include "clk-krait.h"
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+
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+DEFINE_FIXED_DIV_CLK(acpu_aux, 2, "gpll0_vote");
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+
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+static u8 sec_mux_map[] = {
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+ 2,
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+ 0,
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+};
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+
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+static u8 pri_mux_map[] = {
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+ 1,
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+ 2,
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+ 0,
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+};
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+
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+static int
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+krait_add_div(struct device *dev, int id, const char *s, unsigned offset)
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+{
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+ struct div_clk *div;
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+ struct clk_init_data init = {
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+ .num_parents = 1,
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+ .ops = &clk_ops_div,
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+ .flags = CLK_SET_RATE_PARENT,
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+ };
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+ const char *p_names[1];
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+ struct clk *clk;
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+
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+ div = devm_kzalloc(dev, sizeof(*dev), GFP_KERNEL);
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+ if (!div)
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+ return -ENOMEM;
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+
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+ div->data.div = 2;
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+ div->data.min_div = 2;
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+ div->data.max_div = 2;
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+ div->ops = &clk_div_ops_kpss_div2;
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+ div->mask = 0x3;
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+ div->shift = 6;
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+ div->priv = (void *)(id >= 0);
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+ div->offset = offset;
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+ div->hw.init = &init;
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+
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+ init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
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+ if (!init.name)
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+ return -ENOMEM;
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+
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+ init.parent_names = p_names;
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+ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
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+ if (!p_names[0]) {
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+ kfree(init.name);
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+ return -ENOMEM;
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+ }
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+
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+ clk = devm_clk_register(dev, &div->hw);
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+ kfree(p_names[0]);
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+ kfree(init.name);
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+
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+ return PTR_ERR_OR_ZERO(clk);
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+}
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+
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+static int
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+krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned offset,
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+ bool unique_aux)
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+{
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+ struct mux_clk *mux;
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+ static const char *sec_mux_list[] = {
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+ "acpu_aux",
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+ "qsb",
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+ };
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+ struct clk_init_data init = {
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+ .parent_names = sec_mux_list,
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+ .num_parents = ARRAY_SIZE(sec_mux_list),
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+ .ops = &clk_ops_gen_mux,
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+ .flags = CLK_SET_RATE_PARENT,
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+ };
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+ struct clk *clk;
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+
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+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
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+ if (!mux)
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+ return -ENOMEM;
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+
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+ mux->offset = offset;
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+ mux->priv = (void *)(id >= 0);
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+ mux->has_safe_parent = true;
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+ mux->safe_sel = 2;
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+ mux->ops = &clk_mux_ops_kpss;
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+ mux->mask = 0x3;
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+ mux->shift = 2;
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+ mux->parent_map = sec_mux_map;
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+ mux->hw.init = &init;
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+
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+ init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
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+ if (!init.name)
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+ return -ENOMEM;
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+
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+ if (unique_aux) {
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+ sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
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+ if (!sec_mux_list[0]) {
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+ clk = ERR_PTR(-ENOMEM);
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+ goto err_aux;
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+ }
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+ }
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+
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+ clk = devm_clk_register(dev, &mux->hw);
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+
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+ if (unique_aux)
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+ kfree(sec_mux_list[0]);
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+err_aux:
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+ kfree(init.name);
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+ return PTR_ERR_OR_ZERO(clk);
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+}
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+
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+static struct clk *
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+krait_add_pri_mux(struct device *dev, int id, const char * s, unsigned offset)
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+{
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+ struct mux_clk *mux;
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+ const char *p_names[3];
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+ struct clk_init_data init = {
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+ .parent_names = p_names,
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+ .num_parents = ARRAY_SIZE(p_names),
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+ .ops = &clk_ops_gen_mux,
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+ .flags = CLK_SET_RATE_PARENT,
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+ };
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+ struct clk *clk;
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+
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+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
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+ if (!mux)
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+ return ERR_PTR(-ENOMEM);
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+
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+ mux->has_safe_parent = true;
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+ mux->safe_sel = 0;
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+ mux->ops = &clk_mux_ops_kpss;
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+ mux->mask = 0x3;
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+ mux->shift = 0;
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+ mux->offset = offset;
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+ mux->priv = (void *)(id >= 0);
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+ mux->parent_map = pri_mux_map;
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+ mux->hw.init = &init;
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+
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+ init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
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+ if (!init.name)
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+ return ERR_PTR(-ENOMEM);
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+
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+ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
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+ if (!p_names[0]) {
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+ clk = ERR_PTR(-ENOMEM);
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+ goto err_p0;
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+ }
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+
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+ p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
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+ if (!p_names[1]) {
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+ clk = ERR_PTR(-ENOMEM);
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+ goto err_p1;
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+ }
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+
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+ p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
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+ if (!p_names[2]) {
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+ clk = ERR_PTR(-ENOMEM);
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+ goto err_p2;
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+ }
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+
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+ clk = devm_clk_register(dev, &mux->hw);
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+
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+ kfree(p_names[2]);
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+err_p2:
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+ kfree(p_names[1]);
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+err_p1:
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+ kfree(p_names[0]);
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+err_p0:
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+ kfree(init.name);
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+ return clk;
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+}
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+
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+/* id < 0 for L2, otherwise id == physical CPU number */
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+static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
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+{
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+ int ret;
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+ unsigned offset;
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+ void *p = NULL;
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+ const char *s;
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+ struct clk *clk;
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+
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+ if (id >= 0) {
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+ offset = 0x4501 + (0x1000 * id);
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+ s = p = kasprintf(GFP_KERNEL, "%d", id);
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+ if (!s)
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+ return ERR_PTR(-ENOMEM);
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+ } else {
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+ offset = 0x500;
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+ s = "_l2";
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+ }
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+
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+ ret = krait_add_div(dev, id, s, offset);
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+ if (ret) {
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+ clk = ERR_PTR(ret);
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+ goto err;
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+ }
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+
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+ ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
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+ if (ret) {
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+ clk = ERR_PTR(ret);
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+ goto err;
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+ }
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+
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+ clk = krait_add_pri_mux(dev, id, s, offset);
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+err:
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+ kfree(p);
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+ return clk;
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+}
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+
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+static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
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+{
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+ unsigned int idx = clkspec->args[0];
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+ struct clk **clks = data;
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+
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+ if (idx >= 5) {
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+ pr_err("%s: invalid clock index %d\n", __func__, idx);
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+ return ERR_PTR(-EINVAL);
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+ }
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+
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+ return clks[idx] ? : ERR_PTR(-ENODEV);
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+}
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+
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+static const struct of_device_id krait_cc_match_table[] = {
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+ { .compatible = "qcom,krait-cc-v1", (void *)1UL },
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+ { .compatible = "qcom,krait-cc-v2" },
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+ {}
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+};
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+MODULE_DEVICE_TABLE(of, krait_cc_match_table);
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+
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+static int krait_cc_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ const struct of_device_id *id;
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+ unsigned long cur_rate, aux_rate;
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+ int i, cpu;
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+ struct clk *clk;
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+ struct clk **clks;
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+ struct clk *l2_pri_mux_clk;
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+
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+ id = of_match_device(krait_cc_match_table, &pdev->dev);
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+ if (!id)
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+ return -ENODEV;
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+
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+ /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
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+ clk = clk_register_fixed_rate(dev, "qsb", NULL, CLK_IS_ROOT, 1);
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+ if (IS_ERR(clk))
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+ return PTR_ERR(clk);
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+
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+ if (!id->data) {
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+ clk = devm_clk_register(dev, &acpu_aux.hw);
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+ if (IS_ERR(clk))
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+ return PTR_ERR(clk);
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+ }
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+
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+ /* Krait configurations have at most 4 CPUs and one L2 */
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+ clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
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+ if (!clks)
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+ return -ENOMEM;
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+
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+ for_each_possible_cpu(i) {
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+ cpu = cpu_logical_map(i);
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+ clk = krait_add_clks(dev, cpu, id->data);
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+ if (IS_ERR(clk))
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+ return PTR_ERR(clk);
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+ clks[cpu] = clk;
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+ }
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+
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+ l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
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+ if (IS_ERR(l2_pri_mux_clk))
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+ return PTR_ERR(l2_pri_mux_clk);
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+ clks[4] = l2_pri_mux_clk;
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+
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+ /*
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+ * We don't want the CPU or L2 clocks to be turned off at late init
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+ * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
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+ * refcount of these clocks. Any cpufreq/hotplug manager can assume
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+ * that the clocks have already been prepared and enabled by the time
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+ * they take over.
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+ */
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+ for_each_online_cpu(i) {
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+ cpu = cpu_logical_map(i);
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+ clk_prepare_enable(l2_pri_mux_clk);
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+ WARN(clk_prepare_enable(clks[cpu]),
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+ "Unable to turn on CPU%d clock", cpu);
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+ }
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+
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+ /*
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+ * Force reinit of HFPLLs and muxes to overwrite any potential
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+ * incorrect configuration of HFPLLs and muxes by the bootloader.
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+ * While at it, also make sure the cores are running at known rates
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+ * and print the current rate.
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+ *
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+ * The clocks are set to aux clock rate first to make sure the
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+ * secondary mux is not sourcing off of QSB. The rate is then set to
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+ * two different rates to force a HFPLL reinit under all
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+ * circumstances.
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+ */
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+ cur_rate = clk_get_rate(l2_pri_mux_clk);
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+ aux_rate = 384000000;
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+ if (cur_rate == 1) {
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+ pr_info("L2 @ QSB rate. Forcing new rate.\n");
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+ cur_rate = aux_rate;
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+ }
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+ clk_set_rate(l2_pri_mux_clk, aux_rate);
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+ clk_set_rate(l2_pri_mux_clk, 2);
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+ clk_set_rate(l2_pri_mux_clk, cur_rate);
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+ pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
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+ for_each_possible_cpu(i) {
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+ cpu = cpu_logical_map(i);
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+ clk = clks[cpu];
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+ cur_rate = clk_get_rate(clk);
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+ if (cur_rate == 1) {
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+ pr_info("CPU%d @ QSB rate. Forcing new rate.\n", i);
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+ cur_rate = aux_rate;
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+ }
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+ clk_set_rate(clk, aux_rate);
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+ clk_set_rate(clk, 2);
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+ clk_set_rate(clk, cur_rate);
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+ pr_info("CPU%d @ %lu KHz\n", i, clk_get_rate(clk) / 1000);
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+ }
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+
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+ of_clk_add_provider(dev->of_node, krait_of_get, clks);
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+
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+ return 0;
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+}
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+
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+static struct platform_driver krait_cc_driver = {
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+ .probe = krait_cc_probe,
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+ .driver = {
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+ .name = "clock-krait",
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+ .of_match_table = krait_cc_match_table,
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+ .owner = THIS_MODULE,
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+ },
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+};
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+module_platform_driver(krait_cc_driver);
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+
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+MODULE_DESCRIPTION("Krait CPU Clock Driver");
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+MODULE_LICENSE("GPL v2");
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--
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1.7.10.4
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