mirror of https://github.com/hak5/openwrt.git
579 lines
15 KiB
Diff
579 lines
15 KiB
Diff
--- a/include/linux/spi/spi.h
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+++ b/include/linux/spi/spi.h
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@@ -523,6 +523,8 @@ struct spi_transfer {
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u16 delay_usecs;
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u32 speed_hz;
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+ unsigned last_in_message_list;
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+
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struct list_head transfer_list;
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};
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--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -198,6 +198,14 @@ config SPI_GPIO_OLD
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If unsure, say N.
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+config SPI_CNS21XX
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+ tristate "Cavium Netowrks CNS21xx SPI master (EXPERIMENTAL)"
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+ depends on ARCH_CNS21XX
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+ select SPI_BITBANG
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+ help
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+ This driver supports the buil-in SPI controller of the Cavium Networks
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+ CNS21xx SoCs.
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+
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config SPI_IMX
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tristate "Freescale i.MX SPI controllers"
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depends on ARCH_MXC
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--- a/drivers/spi/Makefile
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+++ b/drivers/spi/Makefile
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@@ -21,6 +21,7 @@ obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfi
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obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o
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obj-$(CONFIG_SPI_BUTTERFLY) += spi-butterfly.o
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obj-$(CONFIG_SPI_CLPS711X) += spi-clps711x.o
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+obj-$(CONFIG_SPI_CNS21XX) += spi-cns21xx.o
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obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
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obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
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obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
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--- a/drivers/spi/spi-bitbang.c
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+++ b/drivers/spi/spi-bitbang.c
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@@ -328,6 +328,13 @@ static void bitbang_work(struct work_str
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*/
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if (!m->is_dma_mapped)
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t->rx_dma = t->tx_dma = 0;
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+
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+ if (t->transfer_list.next == &m->transfers) {
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+ t->last_in_message_list = 1;
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+ } else {
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+ t->last_in_message_list = 0;
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+ }
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+
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status = bitbang->txrx_bufs(spi, t);
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}
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if (status > 0)
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--- /dev/null
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+++ b/drivers/spi/spi-cns21xx.c
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@@ -0,0 +1,521 @@
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+/*
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+ * Copyright (c) 2008 Cavium Networks
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+ * Copyright (c) 2010-2012 Gabor Juhos <juhosg@openwrt.org>
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+ *
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+ * This file is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License, Version 2, as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <linux/spinlock.h>
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+#include <linux/workqueue.h>
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+#include <linux/interrupt.h>
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+#include <linux/delay.h>
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+#include <linux/errno.h>
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+#include <linux/platform_device.h>
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+#include <linux/io.h>
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+#include <linux/spi/spi.h>
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+#include <linux/spi/spi_bitbang.h>
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+
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+#include <mach/hardware.h>
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+#include <mach/cns21xx.h>
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+
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+#define DRIVER_NAME "cns21xx-spi"
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+
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+#ifdef CONFIG_CNS21XX_SPI_DEBUG
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+#define DBG(fmt, args...) pr_info("[CNS21XX_SPI_DEBUG]" fmt, ## args)
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+#else
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+#define DBG(fmt, args...) do {} while (0)
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+#endif /* CNS21XX_SPI_DEBUG */
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+
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+#define SPI_REG_CFG 0x40
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+#define SPI_REG_STAT 0x44
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+#define SPI_REG_BIT_RATE 0x48
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+#define SPI_REG_TX_CTRL 0x4c
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+#define SPI_REG_TX_DATA 0x50
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+#define SPI_REG_RX_CTRL 0x54
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+#define SPI_REG_RX_DATA 0x58
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+#define SPI_REG_FIFO_TX_CFG 0x5c
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+#define SPI_REG_FIFO_TX_CTRL 0x60
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+#define SPI_REG_FIFO_RX_CFG 0x64
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+#define SPI_REG_INTR_STAT 0x68
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+#define SPI_REG_INTR_ENA 0x6c
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+
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+#define CFG_SPI_EN BIT(31)
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+#define CFG_SPI_CLKPOL BIT(14)
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+#define CFG_SPI_CLKPHA BIT(13)
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+#define CFG_SPI_MASTER_EN BIT(11)
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+#define CFG_SPI_CHAR_LEN_M 0x3
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+#define CFG_SPI_CHAR_LEN_8BITS 0
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+#define CFG_SPI_CHAR_LEN_16BITS 1
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+#define CFG_SPI_CHAR_LEN_24BITS 2
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+#define CFG_SPI_CHAR_LEN_32BITS 3
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+
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+#define STAT_SPI_BUSY_STA BIT(1)
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+
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+#define BIT_RATE_DIV_1 0
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+#define BIT_RATE_DIV_2 1
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+#define BIT_RATE_DIV_4 2
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+#define BIT_RATE_DIV_8 3
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+#define BIT_RATE_DIV_16 4
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+#define BIT_RATE_DIV_32 5
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+#define BIT_RATE_DIV_64 6
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+#define BIT_RATE_DIV_128 7
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+
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+#define TX_CTRL_SPI_TXDAT_EOF BIT(2)
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+#define TX_CTRL_SPI_TXCH_NUM_M 0x3
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+#define TX_CTRL_CLEAR_MASK (TX_CTRL_SPI_TXDAT_EOF | \
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+ TX_CTRL_SPI_TXCH_NUM_M)
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+
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+#define RX_CTRL_SPI_RXDAT_EOF BIT(2)
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+#define RX_CTRL_SPI_RXCH_NUM_M 0x3
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+
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+#define INTR_STAT_SPI_TXBF_UNRN_FG BIT(7)
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+#define INTR_STAT_SPI_RXBF_OVRN_FG BIT(6)
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+#define INTR_STAT_SPI_TXFF_UNRN_FG BIT(5)
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+#define INTR_STAT_SPI_RXFF_OVRN_FG BIT(4)
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+#define INTR_STAT_SPI_TXBUF_FG BIT(3)
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+#define INTR_STAT_SPI_RXBUF_FG BIT(2)
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+#define INTR_STAT_SPI_TXFF_FG BIT(1)
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+#define INTR_STAT_SPI_RXFF_FG BIT(0)
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+
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+#define INTR_STAT_CLEAR_MASK (INTR_STAT_SPI_TXBF_UNRN_FG | \
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+ INTR_STAT_SPI_RXBF_OVRN_FG | \
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+ INTR_STAT_SPI_TXFF_UNRN_FG | \
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+ INTR_STAT_SPI_RXFF_OVRN_FG)
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+
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+#define FIFO_TX_CFG_SPI_TXFF_THRED_M 0x3
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+#define FIFO_TX_CFG_SPI_TXFF_THRED_S 4
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+#define FIFO_TX_CFG_SPI_TXFF_THRED_2 0
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+#define FIFO_TX_CFG_SPI_TXFF_THRED_4 1
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+#define FIFO_TX_CFG_SPI_TXFF_THRED_6 0
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+#define FIFO_TX_CFG_SPI_TXFF_STATUS_M 0xf
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+
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+#define FIFO_RX_CFG_SPI_RXFF_THRED_M 0x3
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+#define FIFO_RX_CFG_SPI_RXFF_THRED_S 4
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+#define FIFO_RX_CFG_SPI_RXFF_THRED_2 0
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+#define FIFO_RX_CFG_SPI_RXFF_THRED_4 1
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+#define FIFO_RX_CFG_SPI_RXFF_THRED_6 0
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+#define FIFO_RX_CFG_SPI_RXFF_STATUS_M 0xf
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+
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+#define CNS21XX_SPI_NUM_BIT_RATES 8
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+
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+struct cns21xx_spi {
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+ struct spi_bitbang bitbang;
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+
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+ struct spi_master *master;
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+ struct device *dev;
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+ void __iomem *base;
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+ struct resource *region;
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+
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+ unsigned freq_max;
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+ unsigned freq_min;
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+
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+};
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+
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+static inline struct cns21xx_spi *to_hw(struct spi_device *spi)
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+{
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+ return spi_master_get_devdata(spi->master);
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+}
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+
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+static inline u32 cns21xx_spi_rr(struct cns21xx_spi *hw, unsigned int reg)
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+{
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+ return __raw_readl(hw->base + reg);
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+}
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+
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+static inline void cns21xx_spi_wr(struct cns21xx_spi *hw, u32 val,
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+ unsigned int reg)
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+{
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+ __raw_writel(val, hw->base + reg);
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+}
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+
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+#define CNS21XX_SPI_RETRY_COUNT 100
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+static inline int cns21xx_spi_wait(struct cns21xx_spi *hw, unsigned int reg,
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+ u32 mask, u32 val)
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+{
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+ int retry_cnt = 0;
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+
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+ do {
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+ if ((cns21xx_spi_rr(hw, reg) & mask) == val)
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+ break;
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+
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+ if (++retry_cnt > CNS21XX_SPI_RETRY_COUNT) {
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+ dev_err(hw->dev, "timeout waiting on register %02x\n",
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+ reg);
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+ return -EIO;
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+ }
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+ } while (1);
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+
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+ return 0;
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+}
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+
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+static int cns21xx_spi_txrx_word(struct cns21xx_spi *hw, u8 tx_channel,
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+ u8 tx_eof_flag, u32 tx_data, u32 *rx_data)
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+{
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+ unsigned int tx_ctrl;
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+ u8 rx_channel;
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+ u8 rx_eof_flag;
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+ int err = 0;
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+
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+ err = cns21xx_spi_wait(hw, SPI_REG_STAT, STAT_SPI_BUSY_STA, 0);
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+ if (err)
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+ return err;
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+
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+ err = cns21xx_spi_wait(hw, SPI_REG_INTR_STAT, INTR_STAT_SPI_TXBUF_FG,
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+ INTR_STAT_SPI_TXBUF_FG);
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+ if (err)
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+ return err;
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+
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+ tx_ctrl = cns21xx_spi_rr(hw, SPI_REG_TX_CTRL);
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+ tx_ctrl &= ~(TX_CTRL_CLEAR_MASK);
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+ tx_ctrl |= (tx_channel & TX_CTRL_SPI_TXCH_NUM_M);
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+ tx_ctrl |= (tx_eof_flag) ? TX_CTRL_SPI_TXDAT_EOF : 0;
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+ cns21xx_spi_wr(hw, tx_ctrl, SPI_REG_TX_CTRL);
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+
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+ cns21xx_spi_wr(hw, tx_data, SPI_REG_TX_DATA);
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+
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+ err = cns21xx_spi_wait(hw, SPI_REG_INTR_STAT, INTR_STAT_SPI_RXBUF_FG,
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+ INTR_STAT_SPI_RXBUF_FG);
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+ if (err)
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+ return err;
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+
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+ rx_channel = cns21xx_spi_rr(hw, SPI_REG_RX_CTRL) &
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+ RX_CTRL_SPI_RXCH_NUM_M;
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+
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+ rx_eof_flag = (cns21xx_spi_rr(hw, SPI_REG_RX_CTRL) &
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+ RX_CTRL_SPI_RXDAT_EOF) ? 1 : 0;
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+
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+ *rx_data = cns21xx_spi_rr(hw, SPI_REG_RX_DATA);
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+
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+ if ((tx_channel != rx_channel) || (tx_eof_flag != rx_eof_flag))
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+ return -EPROTO;
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+
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+ return 0;
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+}
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+
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+static void cns21xx_spi_chipselect(struct spi_device *spi, int value)
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+{
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+ struct cns21xx_spi *hw = to_hw(spi);
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+ unsigned int spi_config;
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+ unsigned int tx_ctrl;
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+
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+ switch (value) {
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+ case BITBANG_CS_INACTIVE:
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+ break;
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+
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+ case BITBANG_CS_ACTIVE:
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+ spi_config = cns21xx_spi_rr(hw, SPI_REG_CFG);
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+
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+ if (spi->mode & SPI_CPHA)
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+ spi_config |= CFG_SPI_CLKPHA;
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+ else
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+ spi_config &= ~CFG_SPI_CLKPHA;
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+
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+ if (spi->mode & SPI_CPOL)
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+ spi_config |= CFG_SPI_CLKPOL;
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+ else
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+ spi_config &= ~CFG_SPI_CLKPOL;
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+
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+ cns21xx_spi_wr(hw, spi_config, SPI_REG_CFG);
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+
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+ tx_ctrl = cns21xx_spi_rr(hw, SPI_REG_TX_CTRL);
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+ tx_ctrl &= ~(TX_CTRL_CLEAR_MASK);
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+ tx_ctrl |= (spi->chip_select & TX_CTRL_SPI_TXCH_NUM_M);
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+ cns21xx_spi_wr(hw, tx_ctrl, SPI_REG_TX_CTRL);
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+
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+ break;
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+ }
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+}
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+
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+static int cns21xx_spi_setup(struct spi_device *spi)
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+{
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+ struct cns21xx_spi *hw = to_hw(spi);
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+
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+ if (spi->bits_per_word != 8) {
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+ dev_err(&spi->dev, "%s: invalid bits_per_word=%u\n",
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+ __func__, spi->bits_per_word);
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+ return -EINVAL;
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+ }
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+
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+ if (spi->max_speed_hz == 0)
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+ spi->max_speed_hz = hw->freq_max;
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+
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+ if (spi->max_speed_hz > hw->freq_max ||
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+ spi->max_speed_hz < hw->freq_min) {
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+ dev_err(&spi->dev, "%s: max_speed_hz=%u out of range\n",
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+ __func__, spi->max_speed_hz);
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+static int cns21xx_spi_setup_transfer(struct spi_device *spi,
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+ struct spi_transfer *t)
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+{
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+ struct cns21xx_spi *hw = to_hw(spi);
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+ u8 bits_per_word;
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+ u32 hz;
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+ int i;
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+
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+ bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
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+ hz = t ? t->speed_hz : spi->max_speed_hz;
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+
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+ if (!bits_per_word)
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+ bits_per_word = spi->bits_per_word;
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+
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+ if (!hz)
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+ hz = spi->max_speed_hz;
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+
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+ if (bits_per_word != 8) {
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+ dev_err(&spi->dev, "%s: invalid bits_per_word=%u\n",
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+ __func__, bits_per_word);
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+ return -EINVAL;
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+ }
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+
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+ if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
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+ dev_err(&spi->dev, "%s: max_speed_hz=%u out of range\n",
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+ __func__, hz);
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+ return -EINVAL;
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+ }
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+
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+ for (i = 0; i < CNS21XX_SPI_NUM_BIT_RATES; i++)
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+ if (spi->max_speed_hz > (cns21xx_get_apb_freq() >> i))
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+ break;
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+
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+ DBG("max_speed:%uHz, curr_speed:%luHz, rate_index=%d\n",
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+ spi->max_speed_hz, cns21xx_get_apb_freq() / (1 << i), i);
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+
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+ cns21xx_spi_wr(hw, i, SPI_REG_BIT_RATE);
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+
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+ return 0;
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+}
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+
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+static int cns21xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
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+{
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+ struct cns21xx_spi *hw = to_hw(spi);
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+ const unsigned char *tx_buf;
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+ unsigned char *rx_buf;
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+ u32 rx_data;
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+ int tx_eof;
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+ int err = 0;
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+ int i;
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+
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+ tx_buf = t->tx_buf;
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+ rx_buf = t->rx_buf;
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+ tx_eof = t->last_in_message_list;
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+
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+ DBG("txrx: tx %p, rx %p, len %d\n", tx_buf, rx_buf, t->len);
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+
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+ if (tx_buf) {
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+ for (i = 0; i < t->len; i++)
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+ DBG("tx_buf[%02d]: 0x%02x\n", i, tx_buf[i]);
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+
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+ for (i = 0; i < (t->len - 1); i++) {
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+ err = cns21xx_spi_txrx_word(hw, spi->chip_select, 0,
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+ tx_buf[i], &rx_data);
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+ if (err)
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+ goto done;
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+
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+ if (rx_buf) {
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+ rx_buf[i] = rx_data;
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+ DBG("rx_buf[%02d]:0x%02x\n", i, rx_buf[i]);
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+ }
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+ }
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+
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+ err = cns21xx_spi_txrx_word(hw, spi->chip_select, tx_eof,
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+ tx_buf[i], &rx_data);
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+ if (err)
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+ goto done;
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+
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+ if ((tx_eof) && rx_buf) {
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+ rx_buf[i] = rx_data;
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+ DBG("rx_buf[%02d]:0x%02x\n", i, rx_buf[i]);
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+ }
|
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+ } else if (rx_buf) {
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+ for (i = 0; i < (t->len - 1); i++) {
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+ err = cns21xx_spi_txrx_word(hw, spi->chip_select, 0,
|
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+ 0xff, &rx_data);
|
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+ if (err)
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+ goto done;
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+
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+ rx_buf[i] = rx_data;
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+ DBG("rx_buf[%02d]:0x%02x\n", i, rx_buf[i]);
|
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+ }
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+
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+ err = cns21xx_spi_txrx_word(hw, spi->chip_select, tx_eof,
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+ 0xff, &rx_data);
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+ if (err)
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+ goto done;
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+
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+ rx_buf[i] = rx_data;
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+ DBG("rx_buf[%02d]:0x%02x\n", i, rx_buf[i]);
|
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+ }
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+
|
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+ done:
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+ return (err) ? err : t->len;
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+}
|
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+
|
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+static void __init cns21xx_spi_hw_init(struct cns21xx_spi *hw)
|
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+{
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+ u32 t;
|
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+ u32 pclk;
|
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+
|
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+ /* Setup configuration register */
|
|
+ cns21xx_spi_wr(hw, CFG_SPI_MASTER_EN, SPI_REG_CFG);
|
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+
|
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+ /* Set default clock to PCLK/2 */
|
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+ cns21xx_spi_wr(hw, BIT_RATE_DIV_2, SPI_REG_BIT_RATE);
|
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+
|
|
+ /* Configure SPI's Tx channel */
|
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+ cns21xx_spi_wr(hw, 0, SPI_REG_TX_CTRL);
|
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+
|
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+ /* Configure Tx FIFO Threshold */
|
|
+ t = cns21xx_spi_rr(hw, SPI_REG_FIFO_TX_CFG);
|
|
+ t &= ~(FIFO_TX_CFG_SPI_TXFF_THRED_M << FIFO_TX_CFG_SPI_TXFF_THRED_S);
|
|
+ t |= (FIFO_TX_CFG_SPI_TXFF_THRED_2 << FIFO_TX_CFG_SPI_TXFF_THRED_S);
|
|
+ cns21xx_spi_wr(hw, t, SPI_REG_FIFO_TX_CFG);
|
|
+
|
|
+ /* Configure Rx FIFO Threshold */
|
|
+ t = cns21xx_spi_rr(hw, SPI_REG_FIFO_RX_CFG);
|
|
+ t &= ~(FIFO_RX_CFG_SPI_RXFF_THRED_M << FIFO_RX_CFG_SPI_RXFF_THRED_S);
|
|
+ t |= (FIFO_RX_CFG_SPI_RXFF_THRED_2 << FIFO_RX_CFG_SPI_RXFF_THRED_S);
|
|
+ cns21xx_spi_wr(hw, t, SPI_REG_FIFO_RX_CFG);
|
|
+
|
|
+ /* Disable interrupts, and clear interrupt status */
|
|
+ cns21xx_spi_wr(hw, 0, SPI_REG_INTR_ENA);
|
|
+ cns21xx_spi_wr(hw, INTR_STAT_CLEAR_MASK, SPI_REG_INTR_STAT);
|
|
+
|
|
+ (void) cns21xx_spi_rr(hw, SPI_REG_RX_DATA);
|
|
+
|
|
+ /* Enable SPI */
|
|
+ t = cns21xx_spi_rr(hw, SPI_REG_CFG);
|
|
+ t |= CFG_SPI_EN;
|
|
+ cns21xx_spi_wr(hw, t, SPI_REG_CFG);
|
|
+
|
|
+ pclk = cns21xx_get_apb_freq();
|
|
+ hw->freq_max = pclk;
|
|
+ hw->freq_min = pclk / (1 << BIT_RATE_DIV_128);
|
|
+}
|
|
+
|
|
+static int __init cns21xx_spi_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct cns21xx_spi *hw;
|
|
+ struct spi_master *master;
|
|
+ struct resource *res;
|
|
+ int err = 0;
|
|
+
|
|
+ master = spi_alloc_master(&pdev->dev, sizeof(struct cns21xx_spi));
|
|
+ if (!master) {
|
|
+ dev_err(&pdev->dev, "No memory for spi_master\n");
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+
|
|
+ hw = spi_master_get_devdata(master);
|
|
+
|
|
+ platform_set_drvdata(pdev, hw);
|
|
+ hw->master = spi_master_get(master);
|
|
+ hw->dev = &pdev->dev;
|
|
+
|
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
+ if (!res) {
|
|
+ dev_dbg(&pdev->dev, "no MEM resource found\n");
|
|
+ err = -ENOENT;
|
|
+ goto err_put_master;
|
|
+ }
|
|
+
|
|
+ hw->region = request_mem_region(res->start, resource_size(res),
|
|
+ dev_name(&pdev->dev));
|
|
+ if (!hw->region) {
|
|
+ dev_err(&pdev->dev, "unable to reserve iomem region\n");
|
|
+ err = -ENXIO;
|
|
+ goto err_put_master;
|
|
+ }
|
|
+
|
|
+ hw->base = ioremap(res->start, resource_size(res));
|
|
+ if (!hw->base) {
|
|
+ dev_err(&pdev->dev, "ioremap failed\n");
|
|
+ err = -ENOENT;
|
|
+ goto err_release_region;
|
|
+ }
|
|
+
|
|
+ cns21xx_spi_hw_init(hw);
|
|
+
|
|
+ master->bus_num = pdev->id;
|
|
+ if (master->bus_num == -1)
|
|
+ master->bus_num = 0;
|
|
+
|
|
+ master->num_chipselect = 4;
|
|
+ master->setup = cns21xx_spi_setup;
|
|
+
|
|
+ hw->bitbang.master = hw->master;
|
|
+ hw->bitbang.chipselect = cns21xx_spi_chipselect;
|
|
+ hw->bitbang.txrx_bufs = cns21xx_spi_txrx;
|
|
+ hw->bitbang.setup_transfer = cns21xx_spi_setup_transfer;
|
|
+
|
|
+ err = spi_bitbang_start(&hw->bitbang);
|
|
+ if (err) {
|
|
+ dev_err(hw->dev, "unable to register SPI master\n");
|
|
+ goto err_unmap;
|
|
+ }
|
|
+
|
|
+ dev_info(hw->dev, "iomem at %08x\n", res->start);
|
|
+
|
|
+ return 0;
|
|
+
|
|
+ err_unmap:
|
|
+ iounmap(hw->base);
|
|
+
|
|
+ err_release_region:
|
|
+ release_resource(hw->region);
|
|
+ kfree(hw->region);
|
|
+
|
|
+ err_put_master:
|
|
+ spi_master_put(hw->bitbang.master);
|
|
+ platform_set_drvdata(pdev, NULL);
|
|
+
|
|
+ return err;
|
|
+}
|
|
+
|
|
+static int cns21xx_spi_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct cns21xx_spi *hw = platform_get_drvdata(pdev);
|
|
+
|
|
+ spi_bitbang_stop(&hw->bitbang);
|
|
+ iounmap(hw->base);
|
|
+ release_resource(hw->region);
|
|
+ kfree(hw->region);
|
|
+ spi_master_put(hw->bitbang.master);
|
|
+ platform_set_drvdata(pdev, NULL);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct platform_driver cns21xx_spi_driver = {
|
|
+ .remove = cns21xx_spi_remove,
|
|
+ .driver = {
|
|
+ .name = DRIVER_NAME,
|
|
+ .owner = THIS_MODULE,
|
|
+ },
|
|
+};
|
|
+
|
|
+static int __init cns21xx_spi_init(void)
|
|
+{
|
|
+ return platform_driver_probe(&cns21xx_spi_driver, cns21xx_spi_probe);
|
|
+}
|
|
+
|
|
+static void __exit cns21xx_spi_exit(void)
|
|
+{
|
|
+ platform_driver_unregister(&cns21xx_spi_driver);
|
|
+}
|
|
+
|
|
+module_init(cns21xx_spi_init);
|
|
+module_exit(cns21xx_spi_exit);
|
|
+
|
|
+MODULE_DESCRIPTION("Cavium Networks CNS21xx SPI Controller driver");
|
|
+MODULE_AUTHOR("STAR Semi Corp.");
|
|
+MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
|
|
+MODULE_LICENSE("GPL v2");
|
|
+MODULE_ALIAS("platform:" DRIVER_NAME);
|