Tomasz Maciej Nowak 2d61f8821c mvebu: cortexa9: correct cpu subtype ... Armada 370 processors have only 16 double-precision registers. The change introduced by 8dcc108760 ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") switched accidentally the toolchain for mvebu cortexa9 subtarget to cpu type with 32 double-precision registers. This stems from gcc defaults which assume "vfpv3-d32" if only "vfpv3" as mfpu is specified. That change resulted in unusable image, in which kernel will kill userspace as soon as it causing "Illegal instruction". Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272 Fixes: 8dcc108760 ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>		2020-03-28 22:58:36 +01:00
..
base-files	mvebu: use generic diag.sh	2020-03-15 01:45:44 +01:00
cortexa9	mvebu: cortexa9: correct cpu subtype	2020-03-28 22:58:36 +01:00
cortexa53	mvebu: Remove kernel 4.14 support	2020-03-12 09:28:27 +01:00
cortexa72	mvebu: Remove kernel 4.14 support	2020-03-12 09:28:27 +01:00
files-4.19/arch	mvebu: add initial support for uDPU board	2019-06-28 21:49:33 +02:00
image	treewide: gather DEVICE_VARS into one place	2020-03-21 19:55:12 +01:00
patches-4.19	mvebu: use generic diag.sh	2020-03-15 01:45:44 +01:00
Makefile	treewide: remove maintainer variable from targets	2020-03-16 22:21:45 +01:00
config-4.19	treewide: kernel config: remove runtime options	2019-11-24 14:19:43 +01:00