mirror of https://github.com/hak5/openwrt.git
259 lines
4.7 KiB
Diff
259 lines
4.7 KiB
Diff
--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -250,6 +250,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
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kirkwood-linkstation-lswsxl.dtb \
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kirkwood-linkstation-lswvl.dtb \
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kirkwood-linkstation-lswxl.dtb \
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+ kirkwood-linksys-audi.dtb \
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kirkwood-linksys-viper.dtb \
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kirkwood-lschlv2.dtb \
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kirkwood-lsxhl.dtb \
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--- /dev/null
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+++ b/arch/arm/boot/dts/kirkwood-linksys-audi.dts
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@@ -0,0 +1,245 @@
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+/*
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+ * kirkwood-linksys-audi.dts - Device Tree file for Linksys EA3500
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+ *
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+ * (c) 2013 Jonas Gorski <jogo@openwrt.org>
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+ * (c) 2013 Deutsche Telekom Innovation Laboratories
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+ * (c) 2014 Luka Perkov <luka@openwrt.org>
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+ * (c) 2014 Dan Walters <dan@walters.io>
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+/dts-v1/;
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+
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+#include "kirkwood.dtsi"
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+#include "kirkwood-6282.dtsi"
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+
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+/ {
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+ model = "Linksys Audi (EA3500)";
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+ compatible = "linksys,audi", "marvell,kirkwood-88f6282", "marvell,kirkwood";
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+
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+ memory {
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+ device_type = "memory";
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+ reg = <0x00000000 0x4000000>;
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+ };
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+
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+ aliases {
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+ serial0 = &uart0;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ gpio_keys {
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+ compatible = "gpio-keys";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >;
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+ pinctrl-names = "default";
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+
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+ wps {
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+ label = "WPS Button";
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+ linux,code = <KEY_WPS_BUTTON>;
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+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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+ };
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+
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+ reset {
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+ label = "Reset Button";
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+ linux,code = <KEY_RESTART>;
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+ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
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+ };
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+ };
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+
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+ gpio-leds {
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+ compatible = "gpio-leds";
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+ pinctrl-0 = < &pmx_led_green_power >;
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+ pinctrl-names = "default";
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+
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+ green-power {
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+ label = "audi:green:power";
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+ gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
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+ };
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+ };
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+
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+ mvsw61xx {
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+ compatible = "marvell,88e6171";
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+ status = "okay";
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+ reg = <0x10>;
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+
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+ mii-bus = <&mdio>;
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+ cpu-port-0 = <5>;
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+ cpu-port-1 = <6>;
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+ is-indirect;
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+ };
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+
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+ dsa {
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+ compatible = "marvell,dsa";
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+ #address-cells = <2>;
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+ #size-cells = <0>;
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+
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+ dsa,ethernet = <ð0port>;
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+ dsa,mii-bus = <&mdio>;
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+
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+ switch@16,0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <16 0>; /* MDIO address 16, switch 0 in tree */
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+
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+ port@0 {
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+ reg = <0>;
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+ label = "ethernet1";
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+ };
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+
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+ port@1 {
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+ reg = <1>;
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+ label = "ethernet2";
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+ };
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+
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+ port@2 {
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+ reg = <2>;
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+ label = "ethernet3";
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+ };
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+
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+ port@3 {
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+ reg = <3>;
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+ label = "ethernet4";
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+ };
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+
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+ port@4 {
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+ reg = <4>;
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+ label = "internet";
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+ };
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+
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+ port@5 {
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+ reg = <5>;
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+ label = "cpu";
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+ };
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+ };
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+ };
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+};
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+
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+&pinctrl {
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+ pmx_led_green_power: pmx-led-green-power {
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+ marvell,pins = "mpp7";
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+ marvell,function = "gpo";
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+ };
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+ pmx_btn_wps: pmx-btn-wps {
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+ marvell,pins = "mpp47";
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+ marvell,function = "gpio";
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+ };
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+ pmx_btn_reset: pmx-btn-reset {
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+ marvell,pins = "mpp48";
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+ marvell,function = "gpio";
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+ };
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+};
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+
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+&nand {
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+ status = "okay";
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+ pinctrl-0 = <&pmx_nand>;
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+ pinctrl-names = "default";
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+
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+ partitions {
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+ compatible = "fixed-partitions";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ partition@0 {
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+ label = "u-boot";
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+ reg = <0x0 0x80000>;
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+ read-only;
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+ };
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+
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+ partition@80000 {
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+ label = "u_env";
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+ reg = <0x80000 0x4000>;
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+ };
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+
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+ partition@84000 {
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+ label = "s_env";
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+ reg = <0x84000 0x4000>;
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+ };
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+
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+ partition@200000 {
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+ label = "kernel1";
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+ reg = <0x200000 0x290000>;
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+ };
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+
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+ partition@490000 {
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+ label = "rootfs1";
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+ reg = <0x490000 0x1170000>;
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+ };
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+
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+ partition@1600000 {
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+ label = "kernel2";
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+ reg = <0x1600000 0x290000>;
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+ };
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+
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+ partition@1890000 {
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+ label = "rootfs2";
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+ reg = <0x1890000 0x1170000>;
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+ };
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+
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+ partition@2a00000 {
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+ label = "syscfg";
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+ reg = <0x2a00000 0x1600000>;
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+ };
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+
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+ partition@88000 {
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+ label = "unused";
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+ reg = <0x88000 0x178000>;
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+ };
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+
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+ };
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+};
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+
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+&pciec {
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+ status = "okay";
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+};
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+
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+&pcie0 {
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+ status = "okay";
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+};
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+
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+&pcie1 {
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+ status = "okay";
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+};
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+
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+&mdio {
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+ status = "okay";
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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+
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+/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set
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+ * fixed speed and duplex.
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+ */
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+ð0 {
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+ status = "okay";
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+ ethernet0-port@0 {
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+ speed = <1000>;
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+ duplex = <1>;
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+ };
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+};
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+
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+/* eth1 is connected to the switch at port 6. However DSA only supports a
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+ * single CPU port. Upstream uses DSA so they disable this port to avoid confusion.
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+ */
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+ð1 {
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+ status = "okay";
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+ ethernet1-port@0 {
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+ speed = <1000>;
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+ duplex = <1>;
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+ };
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+};
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+
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+/* There is no battery on the board, so the RTC does not keep
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+ * time when there is no power, making it useless.
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+ */
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+&rtc {
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+ status = "disabled";
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+};
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