mirror of https://github.com/hak5/openwrt.git
476 lines
15 KiB
Diff
476 lines
15 KiB
Diff
From f9cd25fae900b1251e14ec894849846e0a2a7cb3 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Sat, 2 Jul 2016 12:17:10 -0700
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Subject: [PATCH] drm/vc4: Add support for branching in shader validation.
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We're already checking that branch instructions are between the start
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of the shader and the proper PROG_END sequence. The other thing we
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need to make branching safe is to verify that the shader doesn't read
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past the end of the uniforms stream.
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To do that, we require that at any basic block reading uniforms have
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the following instructions:
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load_imm temp, <next offset within uniform stream>
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add unif_addr, temp, unif
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The instructions are generated by userspace, and the kernel verifies
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that the load_imm is of the expected offset, and that the add adds it
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to a uniform. We track which uniform in the stream that is, and at
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draw call time fix up the uniform stream to have the address of the
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start of the shader's uniforms at that location.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 6d45c81d229d71da54d374143e7d6abad4c0cf31)
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---
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drivers/gpu/drm/vc4/vc4_drv.h | 3 +
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drivers/gpu/drm/vc4/vc4_qpu_defines.h | 3 +
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drivers/gpu/drm/vc4/vc4_validate.c | 13 +-
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drivers/gpu/drm/vc4/vc4_validate_shaders.c | 281 +++++++++++++++++++++++++++--
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4 files changed, 283 insertions(+), 17 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -363,6 +363,9 @@ struct vc4_validated_shader_info {
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uint32_t uniforms_src_size;
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uint32_t num_texture_samples;
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struct vc4_texture_sample_info *texture_samples;
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+
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+ uint32_t num_uniform_addr_offsets;
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+ uint32_t *uniform_addr_offsets;
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};
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/**
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--- a/drivers/gpu/drm/vc4/vc4_qpu_defines.h
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+++ b/drivers/gpu/drm/vc4/vc4_qpu_defines.h
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@@ -270,6 +270,9 @@ enum qpu_unpack_r4 {
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#define QPU_OP_ADD_SHIFT 24
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#define QPU_OP_ADD_MASK QPU_MASK(28, 24)
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+#define QPU_LOAD_IMM_SHIFT 0
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+#define QPU_LOAD_IMM_MASK QPU_MASK(31, 0)
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+
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#define QPU_BRANCH_TARGET_SHIFT 0
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#define QPU_BRANCH_TARGET_MASK QPU_MASK(31, 0)
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--- a/drivers/gpu/drm/vc4/vc4_validate.c
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+++ b/drivers/gpu/drm/vc4/vc4_validate.c
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@@ -802,7 +802,7 @@ validate_gl_shader_rec(struct drm_device
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uint32_t src_offset = *(uint32_t *)(pkt_u + o);
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uint32_t *texture_handles_u;
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void *uniform_data_u;
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- uint32_t tex;
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+ uint32_t tex, uni;
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*(uint32_t *)(pkt_v + o) = bo[i]->paddr + src_offset;
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@@ -840,6 +840,17 @@ validate_gl_shader_rec(struct drm_device
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}
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}
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+ /* Fill in the uniform slots that need this shader's
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+ * start-of-uniforms address (used for resetting the uniform
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+ * stream in the presence of control flow).
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+ */
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+ for (uni = 0;
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+ uni < validated_shader->num_uniform_addr_offsets;
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+ uni++) {
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+ uint32_t o = validated_shader->uniform_addr_offsets[uni];
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+ ((uint32_t *)exec->uniforms_v)[o] = exec->uniforms_p;
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+ }
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+
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*(uint32_t *)(pkt_v + o + 4) = exec->uniforms_p;
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exec->uniforms_u += validated_shader->uniforms_src_size;
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--- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c
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+++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c
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@@ -39,6 +39,8 @@
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#include "vc4_drv.h"
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#include "vc4_qpu_defines.h"
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+#define LIVE_REG_COUNT (32 + 32 + 4)
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+
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struct vc4_shader_validation_state {
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/* Current IP being validated. */
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uint32_t ip;
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@@ -57,8 +59,9 @@ struct vc4_shader_validation_state {
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*
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* This is used for the validation of direct address memory reads.
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*/
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- uint32_t live_min_clamp_offsets[32 + 32 + 4];
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- bool live_max_clamp_regs[32 + 32 + 4];
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+ uint32_t live_min_clamp_offsets[LIVE_REG_COUNT];
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+ bool live_max_clamp_regs[LIVE_REG_COUNT];
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+ uint32_t live_immediates[LIVE_REG_COUNT];
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/* Bitfield of which IPs are used as branch targets.
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*
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@@ -66,6 +69,20 @@ struct vc4_shader_validation_state {
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* points and clearing the texturing/clamping state.
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*/
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unsigned long *branch_targets;
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+
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+ /* Set when entering a basic block, and cleared when the uniform
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+ * address update is found. This is used to make sure that we don't
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+ * read uniforms when the address is undefined.
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+ */
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+ bool needs_uniform_address_update;
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+
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+ /* Set when we find a backwards branch. If the branch is backwards,
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+ * the taraget is probably doing an address reset to read uniforms,
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+ * and so we need to be sure that a uniforms address is present in the
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+ * stream, even if the shader didn't need to read uniforms in later
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+ * basic blocks.
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+ */
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+ bool needs_uniform_address_for_loop;
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};
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static uint32_t
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@@ -227,8 +244,14 @@ check_tmu_write(struct vc4_validated_sha
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/* Since direct uses a RADDR uniform reference, it will get counted in
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* check_instruction_reads()
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*/
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- if (!is_direct)
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+ if (!is_direct) {
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+ if (validation_state->needs_uniform_address_update) {
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+ DRM_ERROR("Texturing with undefined uniform address\n");
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+ return false;
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+ }
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+
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validated_shader->uniforms_size += 4;
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+ }
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if (submit) {
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if (!record_texture_sample(validated_shader,
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@@ -242,6 +265,98 @@ check_tmu_write(struct vc4_validated_sha
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return true;
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}
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+static bool require_uniform_address_uniform(struct vc4_validated_shader_info *validated_shader)
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+{
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+ uint32_t o = validated_shader->num_uniform_addr_offsets;
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+ uint32_t num_uniforms = validated_shader->uniforms_size / 4;
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+
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+ validated_shader->uniform_addr_offsets =
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+ krealloc(validated_shader->uniform_addr_offsets,
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+ (o + 1) *
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+ sizeof(*validated_shader->uniform_addr_offsets),
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+ GFP_KERNEL);
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+ if (!validated_shader->uniform_addr_offsets)
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+ return false;
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+
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+ validated_shader->uniform_addr_offsets[o] = num_uniforms;
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+ validated_shader->num_uniform_addr_offsets++;
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+
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+ return true;
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+}
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+
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+static bool
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+validate_uniform_address_write(struct vc4_validated_shader_info *validated_shader,
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+ struct vc4_shader_validation_state *validation_state,
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+ bool is_mul)
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+{
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+ uint64_t inst = validation_state->shader[validation_state->ip];
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+ u32 add_b = QPU_GET_FIELD(inst, QPU_ADD_B);
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+ u32 raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
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+ u32 raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
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+ u32 add_lri = raddr_add_a_to_live_reg_index(inst);
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+ /* We want our reset to be pointing at whatever uniform follows the
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+ * uniforms base address.
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+ */
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+ u32 expected_offset = validated_shader->uniforms_size + 4;
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+
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+ /* We only support absolute uniform address changes, and we
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+ * require that they be in the current basic block before any
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+ * of its uniform reads.
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+ *
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+ * One could potentially emit more efficient QPU code, by
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+ * noticing that (say) an if statement does uniform control
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+ * flow for all threads and that the if reads the same number
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+ * of uniforms on each side. However, this scheme is easy to
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+ * validate so it's all we allow for now.
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+ */
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+
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+ if (QPU_GET_FIELD(inst, QPU_SIG) != QPU_SIG_NONE) {
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+ DRM_ERROR("uniforms address change must be "
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+ "normal math\n");
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+ return false;
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+ }
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+
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+ if (is_mul || QPU_GET_FIELD(inst, QPU_OP_ADD) != QPU_A_ADD) {
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+ DRM_ERROR("Uniform address reset must be an ADD.\n");
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+ return false;
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+ }
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+
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+ if (QPU_GET_FIELD(inst, QPU_COND_ADD) != QPU_COND_ALWAYS) {
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+ DRM_ERROR("Uniform address reset must be unconditional.\n");
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+ return false;
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+ }
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+
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+ if (QPU_GET_FIELD(inst, QPU_PACK) != QPU_PACK_A_NOP &&
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+ !(inst & QPU_PM)) {
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+ DRM_ERROR("No packing allowed on uniforms reset\n");
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+ return false;
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+ }
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+
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+ if (add_lri == -1) {
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+ DRM_ERROR("First argument of uniform address write must be "
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+ "an immediate value.\n");
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+ return false;
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+ }
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+
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+ if (validation_state->live_immediates[add_lri] != expected_offset) {
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+ DRM_ERROR("Resetting uniforms with offset %db instead of %db\n",
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+ validation_state->live_immediates[add_lri],
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+ expected_offset);
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+ return false;
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+ }
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+
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+ if (!(add_b == QPU_MUX_A && raddr_a == QPU_R_UNIF) &&
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+ !(add_b == QPU_MUX_B && raddr_b == QPU_R_UNIF)) {
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+ DRM_ERROR("Second argument of uniform address write must be "
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+ "a uniform.\n");
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+ return false;
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+ }
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+
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+ validation_state->needs_uniform_address_update = false;
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+ validation_state->needs_uniform_address_for_loop = false;
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+ return require_uniform_address_uniform(validated_shader);
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+}
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+
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static bool
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check_reg_write(struct vc4_validated_shader_info *validated_shader,
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struct vc4_shader_validation_state *validation_state,
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@@ -251,14 +366,37 @@ check_reg_write(struct vc4_validated_sha
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uint32_t waddr = (is_mul ?
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QPU_GET_FIELD(inst, QPU_WADDR_MUL) :
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QPU_GET_FIELD(inst, QPU_WADDR_ADD));
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+ uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
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+ bool ws = inst & QPU_WS;
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+ bool is_b = is_mul ^ ws;
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+ u32 lri = waddr_to_live_reg_index(waddr, is_b);
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+
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+ if (lri != -1) {
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+ uint32_t cond_add = QPU_GET_FIELD(inst, QPU_COND_ADD);
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+ uint32_t cond_mul = QPU_GET_FIELD(inst, QPU_COND_MUL);
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+
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+ if (sig == QPU_SIG_LOAD_IMM &&
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+ QPU_GET_FIELD(inst, QPU_PACK) == QPU_PACK_A_NOP &&
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+ ((is_mul && cond_mul == QPU_COND_ALWAYS) ||
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+ (!is_mul && cond_add == QPU_COND_ALWAYS))) {
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+ validation_state->live_immediates[lri] =
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+ QPU_GET_FIELD(inst, QPU_LOAD_IMM);
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+ } else {
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+ validation_state->live_immediates[lri] = ~0;
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+ }
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+ }
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switch (waddr) {
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case QPU_W_UNIFORMS_ADDRESS:
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- /* XXX: We'll probably need to support this for reladdr, but
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- * it's definitely a security-related one.
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- */
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- DRM_ERROR("uniforms address load unsupported\n");
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- return false;
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+ if (is_b) {
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+ DRM_ERROR("relative uniforms address change "
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+ "unsupported\n");
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+ return false;
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+ }
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+
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+ return validate_uniform_address_write(validated_shader,
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+ validation_state,
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+ is_mul);
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case QPU_W_TLB_COLOR_MS:
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case QPU_W_TLB_COLOR_ALL:
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@@ -406,9 +544,35 @@ check_instruction_writes(struct vc4_vali
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}
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static bool
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-check_instruction_reads(uint64_t inst,
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- struct vc4_validated_shader_info *validated_shader)
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+check_branch(uint64_t inst,
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+ struct vc4_validated_shader_info *validated_shader,
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+ struct vc4_shader_validation_state *validation_state,
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+ int ip)
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{
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+ int32_t branch_imm = QPU_GET_FIELD(inst, QPU_BRANCH_TARGET);
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+ uint32_t waddr_add = QPU_GET_FIELD(inst, QPU_WADDR_ADD);
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+ uint32_t waddr_mul = QPU_GET_FIELD(inst, QPU_WADDR_MUL);
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+
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+ if ((int)branch_imm < 0)
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+ validation_state->needs_uniform_address_for_loop = true;
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+
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+ /* We don't want to have to worry about validation of this, and
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+ * there's no need for it.
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+ */
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+ if (waddr_add != QPU_W_NOP || waddr_mul != QPU_W_NOP) {
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+ DRM_ERROR("branch instruction at %d wrote a register.\n",
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+ validation_state->ip);
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+ return false;
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+ }
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+
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+ return true;
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+}
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+
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+static bool
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+check_instruction_reads(struct vc4_validated_shader_info *validated_shader,
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+ struct vc4_shader_validation_state *validation_state)
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+{
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+ uint64_t inst = validation_state->shader[validation_state->ip];
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uint32_t raddr_a = QPU_GET_FIELD(inst, QPU_RADDR_A);
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uint32_t raddr_b = QPU_GET_FIELD(inst, QPU_RADDR_B);
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uint32_t sig = QPU_GET_FIELD(inst, QPU_SIG);
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@@ -420,6 +584,12 @@ check_instruction_reads(uint64_t inst,
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* already be OOM.
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*/
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validated_shader->uniforms_size += 4;
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+
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+ if (validation_state->needs_uniform_address_update) {
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+ DRM_ERROR("Uniform read with undefined uniform "
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+ "address\n");
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+ return false;
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+ }
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}
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return true;
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@@ -516,6 +686,65 @@ vc4_validate_branches(struct vc4_shader_
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return true;
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}
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+/* Resets any known state for the shader, used when we may be branched to from
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+ * multiple locations in the program (or at shader start).
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+ */
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+static void
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+reset_validation_state(struct vc4_shader_validation_state *validation_state)
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+{
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+ int i;
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+
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+ for (i = 0; i < 8; i++)
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+ validation_state->tmu_setup[i / 4].p_offset[i % 4] = ~0;
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+
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+ for (i = 0; i < LIVE_REG_COUNT; i++) {
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+ validation_state->live_min_clamp_offsets[i] = ~0;
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+ validation_state->live_max_clamp_regs[i] = false;
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+ validation_state->live_immediates[i] = ~0;
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+ }
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+}
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+
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+static bool
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+texturing_in_progress(struct vc4_shader_validation_state *validation_state)
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+{
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+ return (validation_state->tmu_write_count[0] != 0 ||
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+ validation_state->tmu_write_count[1] != 0);
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+}
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+
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+static bool
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+vc4_handle_branch_target(struct vc4_shader_validation_state *validation_state)
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+{
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+ uint32_t ip = validation_state->ip;
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+
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+ if (!test_bit(ip, validation_state->branch_targets))
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+ return true;
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+
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+ if (texturing_in_progress(validation_state)) {
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+ DRM_ERROR("Branch target landed during TMU setup\n");
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+ return false;
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+ }
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+
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+ /* Reset our live values tracking, since this instruction may have
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+ * multiple predecessors.
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+ *
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+ * One could potentially do analysis to determine that, for
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+ * example, all predecessors have a live max clamp in the same
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+ * register, but we don't bother with that.
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+ */
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+ reset_validation_state(validation_state);
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+
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+ /* Since we've entered a basic block from potentially multiple
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+ * predecessors, we need the uniforms address to be updated before any
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+ * unforms are read. We require that after any branch point, the next
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+ * uniform to be loaded is a uniform address offset. That uniform's
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+ * offset will be marked by the uniform address register write
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+ * validation, or a one-off the end-of-program check.
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+ */
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+ validation_state->needs_uniform_address_update = true;
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+
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+ return true;
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+}
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+
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struct vc4_validated_shader_info *
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vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
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{
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@@ -524,16 +753,12 @@ vc4_validate_shader(struct drm_gem_cma_o
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uint32_t ip;
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struct vc4_validated_shader_info *validated_shader = NULL;
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struct vc4_shader_validation_state validation_state;
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- int i;
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memset(&validation_state, 0, sizeof(validation_state));
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validation_state.shader = shader_obj->vaddr;
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validation_state.max_ip = shader_obj->base.size / sizeof(uint64_t);
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- for (i = 0; i < 8; i++)
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- validation_state.tmu_setup[i / 4].p_offset[i % 4] = ~0;
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- for (i = 0; i < ARRAY_SIZE(validation_state.live_min_clamp_offsets); i++)
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- validation_state.live_min_clamp_offsets[i] = ~0;
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+ reset_validation_state(&validation_state);
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validation_state.branch_targets =
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kcalloc(BITS_TO_LONGS(validation_state.max_ip),
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@@ -554,6 +779,9 @@ vc4_validate_shader(struct drm_gem_cma_o
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validation_state.ip = ip;
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+ if (!vc4_handle_branch_target(&validation_state))
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+ goto fail;
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+
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switch (sig) {
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case QPU_SIG_NONE:
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case QPU_SIG_WAIT_FOR_SCOREBOARD:
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@@ -569,7 +797,8 @@ vc4_validate_shader(struct drm_gem_cma_o
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goto fail;
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}
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- if (!check_instruction_reads(inst, validated_shader))
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+ if (!check_instruction_reads(validated_shader,
|
|
+ &validation_state))
|
|
goto fail;
|
|
|
|
if (sig == QPU_SIG_PROG_END) {
|
|
@@ -587,6 +816,11 @@ vc4_validate_shader(struct drm_gem_cma_o
|
|
}
|
|
break;
|
|
|
|
+ case QPU_SIG_BRANCH:
|
|
+ if (!check_branch(inst, validated_shader,
|
|
+ &validation_state, ip))
|
|
+ goto fail;
|
|
+ break;
|
|
default:
|
|
DRM_ERROR("Unsupported QPU signal %d at "
|
|
"instruction %d\n", sig, ip);
|
|
@@ -607,6 +841,21 @@ vc4_validate_shader(struct drm_gem_cma_o
|
|
goto fail;
|
|
}
|
|
|
|
+ /* If we did a backwards branch and we haven't emitted a uniforms
|
|
+ * reset since then, we still need the uniforms stream to have the
|
|
+ * uniforms address available so that the backwards branch can do its
|
|
+ * uniforms reset.
|
|
+ *
|
|
+ * We could potentially prove that the backwards branch doesn't
|
|
+ * contain any uses of uniforms until program exit, but that doesn't
|
|
+ * seem to be worth the trouble.
|
|
+ */
|
|
+ if (validation_state.needs_uniform_address_for_loop) {
|
|
+ if (!require_uniform_address_uniform(validated_shader))
|
|
+ goto fail;
|
|
+ validated_shader->uniforms_size += 4;
|
|
+ }
|
|
+
|
|
/* Again, no chance of integer overflow here because the worst case
|
|
* scenario is 8 bytes of uniforms plus handles per 8-byte
|
|
* instruction.
|