mirror of https://github.com/hak5/openwrt.git
359 lines
13 KiB
Diff
359 lines
13 KiB
Diff
From d1a9a03cbe1110756a63d4a3747e22eb8417f75e Mon Sep 17 00:00:00 2001
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From: Mario Kleiner <mario.kleiner.de@gmail.com>
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Date: Thu, 23 Jun 2016 08:17:50 +0200
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Subject: [PATCH] drm/vc4: Implement precise vblank timestamping.
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Precise vblank timestamping is implemented via the
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usual scanout position based method. On VC4 the
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pixelvalves PV do not have a scanout position
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register. Only the hardware video scaler HVS has a
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similar register which describes which scanline for
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the output is currently composited and stored in the
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HVS fifo for later consumption by the PV.
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This causes a problem in that the HVS runs at a much
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faster clock (system clock / audio gate) than the PV
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which runs at video mode dot clock, so the unless the
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fifo between HVS and PV is full, the HVS will progress
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faster in its observable read line position than video
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scan rate, so the HVS position reading can't be directly
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translated into a scanout position for timestamp correction.
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Additionally when the PV is in vblank, it doesn't consume
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from the fifo, so the fifo gets full very quickly and then
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the HVS stops compositing until the PV enters active scanout
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and starts consuming scanlines from the fifo again, making
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new space for the HVS to composite.
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Therefore a simple translation of HVS read position into
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elapsed time since (or to) start of active scanout does
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not work, but for the most interesting cases we can still
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get useful and sufficiently accurate results:
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1. The PV enters active scanout of a new frame with the
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fifo of the HVS completely full, and the HVS can refill
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any fifo line which gets consumed and thereby freed up by
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the PV during active scanout very quickly. Therefore the
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PV and HVS work effectively in lock-step during active
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scanout with the fifo never having more than 1 scanline
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freed up by the PV before it gets refilled. The PV's
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real scanout position is therefore trailing the HVS
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compositing position as scanoutpos = hvspos - fifosize
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and we can get the true scanoutpos as HVS readpos minus
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fifo size, so precise timestamping works while in active
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scanout, except for the last few scanlines of the frame,
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when the HVS reaches end of frame, stops compositing and
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the PV catches up and drains the fifo. This special case
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would only introduce minor errors though.
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2. If we are in vblank, then we can only guess something
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reasonable. If called from vblank irq, we assume the irq is
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usually dispatched with minimum delay, so we can take a
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timestamp taken at entry into the vblank irq handler as a
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baseline and then add a full vblank duration until the
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guessed start of active scanout. As irq dispatch is usually
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pretty low latency this works with relatively low jitter and
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good results.
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If we aren't called from vblank then we could be anywhere
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within the vblank interval, so we return a neutral result,
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simply the current system timestamp, and hope for the best.
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Measurement shows the generated timestamps to be rather precise,
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and at least never off more than 1 vblank duration worst-case.
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Limitations: Doesn't work well yet for interlaced video modes,
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therefore disabled in interlaced mode for now.
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v2: Use the DISPBASE registers to determine the FIFO size (changes
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by anholt)
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Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Reviewed-and-tested-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2)
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(cherry picked from commit 1bf59f1dcbe25272f6b5d870054647e58a8a9c55)
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 162 +++++++++++++++++++++++++++++++++++++++++
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drivers/gpu/drm/vc4/vc4_drv.c | 2 +
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drivers/gpu/drm/vc4/vc4_drv.h | 7 ++
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drivers/gpu/drm/vc4/vc4_regs.h | 22 +++++-
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4 files changed, 192 insertions(+), 1 deletion(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -47,12 +47,17 @@ struct vc4_crtc {
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const struct vc4_crtc_data *data;
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void __iomem *regs;
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+ /* Timestamp at start of vblank irq - unaffected by lock delays. */
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+ ktime_t t_vblank;
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+
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/* Which HVS channel we're using for our CRTC. */
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int channel;
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u8 lut_r[256];
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u8 lut_g[256];
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u8 lut_b[256];
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+ /* Size in pixels of the COB memory allocated to this CRTC. */
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+ u32 cob_size;
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struct drm_pending_vblank_event *event;
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};
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@@ -134,6 +139,144 @@ int vc4_crtc_debugfs_regs(struct seq_fil
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}
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#endif
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+int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
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+ unsigned int flags, int *vpos, int *hpos,
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+ ktime_t *stime, ktime_t *etime,
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+ const struct drm_display_mode *mode)
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+{
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+ struct vc4_dev *vc4 = to_vc4_dev(dev);
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+ struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
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+ u32 val;
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+ int fifo_lines;
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+ int vblank_lines;
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+ int ret = 0;
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+
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+ /*
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+ * XXX Doesn't work well in interlaced mode yet, partially due
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+ * to problems in vc4 kms or drm core interlaced mode handling,
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+ * so disable for now in interlaced mode.
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+ */
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+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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+ return ret;
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+
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+ /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
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+
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+ /* Get optional system timestamp before query. */
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+ if (stime)
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+ *stime = ktime_get();
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+
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+ /*
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+ * Read vertical scanline which is currently composed for our
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+ * pixelvalve by the HVS, and also the scaler status.
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+ */
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+ val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
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+
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+ /* Get optional system timestamp after query. */
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+ if (etime)
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+ *etime = ktime_get();
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+
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+ /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
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+
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+ /* Vertical position of hvs composed scanline. */
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+ *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
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+
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+ /* No hpos info available. */
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+ if (hpos)
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+ *hpos = 0;
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+
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+ /* This is the offset we need for translating hvs -> pv scanout pos. */
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+ fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
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+
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+ if (fifo_lines > 0)
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+ ret |= DRM_SCANOUTPOS_VALID;
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+
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+ /* HVS more than fifo_lines into frame for compositing? */
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+ if (*vpos > fifo_lines) {
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+ /*
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+ * We are in active scanout and can get some meaningful results
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+ * from HVS. The actual PV scanout can not trail behind more
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+ * than fifo_lines as that is the fifo's capacity. Assume that
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+ * in active scanout the HVS and PV work in lockstep wrt. HVS
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+ * refilling the fifo and PV consuming from the fifo, ie.
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+ * whenever the PV consumes and frees up a scanline in the
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+ * fifo, the HVS will immediately refill it, therefore
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+ * incrementing vpos. Therefore we choose HVS read position -
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+ * fifo size in scanlines as a estimate of the real scanout
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+ * position of the PV.
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+ */
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+ *vpos -= fifo_lines + 1;
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+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
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+ *vpos /= 2;
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+
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+ ret |= DRM_SCANOUTPOS_ACCURATE;
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+ return ret;
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+ }
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+
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+ /*
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+ * Less: This happens when we are in vblank and the HVS, after getting
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+ * the VSTART restart signal from the PV, just started refilling its
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+ * fifo with new lines from the top-most lines of the new framebuffers.
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+ * The PV does not scan out in vblank, so does not remove lines from
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+ * the fifo, so the fifo will be full quickly and the HVS has to pause.
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+ * We can't get meaningful readings wrt. scanline position of the PV
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+ * and need to make things up in a approximative but consistent way.
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+ */
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+ ret |= DRM_SCANOUTPOS_IN_VBLANK;
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+ vblank_lines = mode->crtc_vtotal - mode->crtc_vdisplay;
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+
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+ if (flags & DRM_CALLED_FROM_VBLIRQ) {
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+ /*
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+ * Assume the irq handler got called close to first
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+ * line of vblank, so PV has about a full vblank
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+ * scanlines to go, and as a base timestamp use the
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+ * one taken at entry into vblank irq handler, so it
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+ * is not affected by random delays due to lock
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+ * contention on event_lock or vblank_time lock in
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+ * the core.
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+ */
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+ *vpos = -vblank_lines;
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+
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+ if (stime)
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+ *stime = vc4_crtc->t_vblank;
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+ if (etime)
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+ *etime = vc4_crtc->t_vblank;
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+
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+ /*
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+ * If the HVS fifo is not yet full then we know for certain
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+ * we are at the very beginning of vblank, as the hvs just
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+ * started refilling, and the stime and etime timestamps
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+ * truly correspond to start of vblank.
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+ */
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+ if ((val & SCALER_DISPSTATX_FULL) != SCALER_DISPSTATX_FULL)
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+ ret |= DRM_SCANOUTPOS_ACCURATE;
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+ } else {
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+ /*
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+ * No clue where we are inside vblank. Return a vpos of zero,
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+ * which will cause calling code to just return the etime
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+ * timestamp uncorrected. At least this is no worse than the
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+ * standard fallback.
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+ */
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+ *vpos = 0;
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+ }
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+
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+ return ret;
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+}
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+
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+int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
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+ int *max_error, struct timeval *vblank_time,
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+ unsigned flags)
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+{
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+ struct vc4_dev *vc4 = to_vc4_dev(dev);
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+ struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id];
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+ struct drm_crtc *crtc = &vc4_crtc->base;
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+ struct drm_crtc_state *state = crtc->state;
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+
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+ /* Helper routine in DRM core does all the work: */
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+ return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc_id, max_error,
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+ vblank_time, flags,
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+ &state->adjusted_mode);
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+}
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+
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static void vc4_crtc_destroy(struct drm_crtc *crtc)
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{
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drm_crtc_cleanup(crtc);
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@@ -535,6 +678,7 @@ static irqreturn_t vc4_crtc_irq_handler(
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irqreturn_t ret = IRQ_NONE;
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if (stat & PV_INT_VFP_START) {
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+ vc4_crtc->t_vblank = ktime_get();
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CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
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drm_crtc_handle_vblank(&vc4_crtc->base);
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vc4_crtc_handle_page_flip(vc4_crtc);
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@@ -759,6 +903,22 @@ static void vc4_set_crtc_possible_masks(
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}
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}
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+static void
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+vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
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+{
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+ struct drm_device *drm = vc4_crtc->base.dev;
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+ struct vc4_dev *vc4 = to_vc4_dev(drm);
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+ u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
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+ /* Top/base are supposed to be 4-pixel aligned, but the
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+ * Raspberry Pi firmware fills the low bits (which are
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+ * presumably ignored).
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+ */
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+ u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
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+ u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
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+
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+ vc4_crtc->cob_size = top - base + 4;
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+}
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+
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static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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@@ -835,6 +995,8 @@ static int vc4_crtc_bind(struct device *
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crtc->cursor = cursor_plane;
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}
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+ vc4_crtc_get_cob_allocation(vc4_crtc);
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+
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CRTC_WRITE(PV_INTEN, 0);
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CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
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ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
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--- a/drivers/gpu/drm/vc4/vc4_drv.c
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+++ b/drivers/gpu/drm/vc4/vc4_drv.c
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@@ -116,6 +116,8 @@ static struct drm_driver vc4_drm_driver
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.enable_vblank = vc4_enable_vblank,
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.disable_vblank = vc4_disable_vblank,
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.get_vblank_counter = drm_vblank_no_hw_counter,
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+ .get_scanout_position = vc4_crtc_get_scanoutpos,
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+ .get_vblank_timestamp = vc4_crtc_get_vblank_timestamp,
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#if defined(CONFIG_DEBUG_FS)
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.debugfs_init = vc4_debugfs_init,
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--- a/drivers/gpu/drm/vc4/vc4_drv.h
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+++ b/drivers/gpu/drm/vc4/vc4_drv.h
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@@ -419,6 +419,13 @@ int vc4_enable_vblank(struct drm_device
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void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id);
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void vc4_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file);
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int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg);
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+int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
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+ unsigned int flags, int *vpos, int *hpos,
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+ ktime_t *stime, ktime_t *etime,
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+ const struct drm_display_mode *mode);
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+int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id,
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+ int *max_error, struct timeval *vblank_time,
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+ unsigned flags);
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/* vc4_debugfs.c */
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int vc4_debugfs_init(struct drm_minor *minor);
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -368,7 +368,6 @@
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# define SCALER_DISPBKGND_FILL BIT(24)
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#define SCALER_DISPSTAT0 0x00000048
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-#define SCALER_DISPBASE0 0x0000004c
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# define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
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# define SCALER_DISPSTATX_MODE_SHIFT 30
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# define SCALER_DISPSTATX_MODE_DISABLED 0
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@@ -377,6 +376,24 @@
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# define SCALER_DISPSTATX_MODE_EOF 3
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# define SCALER_DISPSTATX_FULL BIT(29)
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# define SCALER_DISPSTATX_EMPTY BIT(28)
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+# define SCALER_DISPSTATX_FRAME_COUNT_MASK VC4_MASK(17, 12)
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+# define SCALER_DISPSTATX_FRAME_COUNT_SHIFT 12
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+# define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0)
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+# define SCALER_DISPSTATX_LINE_SHIFT 0
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+
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+#define SCALER_DISPBASE0 0x0000004c
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+/* Last pixel in the COB (display FIFO memory) allocated to this HVS
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+ * channel. Must be 4-pixel aligned (and thus 4 pixels less than the
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+ * next COB base).
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+ */
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+# define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16)
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+# define SCALER_DISPBASEX_TOP_SHIFT 16
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+/* First pixel in the COB (display FIFO memory) allocated to this HVS
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+ * channel. Must be 4-pixel aligned.
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+ */
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+# define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0)
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+# define SCALER_DISPBASEX_BASE_SHIFT 0
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+
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#define SCALER_DISPCTRL1 0x00000050
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#define SCALER_DISPBKGND1 0x00000054
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#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \
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@@ -387,6 +404,9 @@
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(x) * (SCALER_DISPSTAT1 - \
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SCALER_DISPSTAT0))
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#define SCALER_DISPBASE1 0x0000005c
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+#define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \
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+ (x) * (SCALER_DISPBASE1 - \
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+ SCALER_DISPBASE0))
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#define SCALER_DISPCTRL2 0x00000060
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#define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \
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(x) * (SCALER_DISPCTRL1 - \
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