mirror of https://github.com/hak5/openwrt.git
189 lines
5.7 KiB
Diff
189 lines
5.7 KiB
Diff
From c9de2447d4b9cf641276d74902405a0b5e1c2a8d Mon Sep 17 00:00:00 2001
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From: Remi Pommarel <repk@triplefau.lt>
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Date: Sun, 6 Dec 2015 17:22:47 +0100
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Subject: [PATCH] clk: bcm2835: Support for clock parent selection
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Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple
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parent clocks. These clocks divide the rate of a parent which can be selected by
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setting the proper bits in the clock control register.
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Previously all these parents where handled by a mux clock. But a mux clock
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cannot be used because updating clock control register to select parent needs a
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password to be xor'd with the parent index.
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This patch get rid of mux clock and make these clocks handle their own parent,
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allowing them to select the one to use.
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Signed-off-by: Remi Pommarel <repk@triplefau.lt>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Michael Turquette <mturquette@baylibre.com>
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(cherry picked from commit 6d18b8adbe679b5947aa822b676efff230acc5f6)
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---
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drivers/clk/bcm/clk-bcm2835.c | 122 ++++++++++++++++++++++++++----------------
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1 file changed, 77 insertions(+), 45 deletions(-)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -1216,16 +1216,6 @@ static long bcm2835_clock_rate_from_divi
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return temp;
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}
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-static long bcm2835_clock_round_rate(struct clk_hw *hw,
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- unsigned long rate,
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- unsigned long *parent_rate)
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-{
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- struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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- u32 div = bcm2835_clock_choose_div(hw, rate, *parent_rate, false);
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-
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- return bcm2835_clock_rate_from_divisor(clock, *parent_rate, div);
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-}
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-
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static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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@@ -1297,13 +1287,75 @@ static int bcm2835_clock_set_rate(struct
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return 0;
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}
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+static int bcm2835_clock_determine_rate(struct clk_hw *hw,
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+ struct clk_rate_request *req)
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+{
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+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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+ struct clk_hw *parent, *best_parent = NULL;
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+ unsigned long rate, best_rate = 0;
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+ unsigned long prate, best_prate = 0;
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+ size_t i;
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+ u32 div;
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+
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+ /*
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+ * Select parent clock that results in the closest but lower rate
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+ */
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+ for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
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+ parent = clk_hw_get_parent_by_index(hw, i);
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+ if (!parent)
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+ continue;
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+ prate = clk_hw_get_rate(parent);
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+ div = bcm2835_clock_choose_div(hw, req->rate, prate, true);
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+ rate = bcm2835_clock_rate_from_divisor(clock, prate, div);
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+ if (rate > best_rate && rate <= req->rate) {
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+ best_parent = parent;
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+ best_prate = prate;
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+ best_rate = rate;
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+ }
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+ }
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+
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+ if (!best_parent)
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+ return -EINVAL;
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+
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+ req->best_parent_hw = best_parent;
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+ req->best_parent_rate = best_prate;
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+
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+ req->rate = best_rate;
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+
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+ return 0;
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+}
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+
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+static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
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+{
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+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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+ struct bcm2835_cprman *cprman = clock->cprman;
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+ const struct bcm2835_clock_data *data = clock->data;
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+ u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
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+
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+ cprman_write(cprman, data->ctl_reg, src);
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+ return 0;
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+}
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+
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+static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
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+{
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+ struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
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+ struct bcm2835_cprman *cprman = clock->cprman;
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+ const struct bcm2835_clock_data *data = clock->data;
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+ u32 src = cprman_read(cprman, data->ctl_reg);
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+
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+ return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
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+}
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+
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+
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static const struct clk_ops bcm2835_clock_clk_ops = {
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.is_prepared = bcm2835_clock_is_on,
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.prepare = bcm2835_clock_on,
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.unprepare = bcm2835_clock_off,
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.recalc_rate = bcm2835_clock_get_rate,
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.set_rate = bcm2835_clock_set_rate,
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- .round_rate = bcm2835_clock_round_rate,
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+ .determine_rate = bcm2835_clock_determine_rate,
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+ .set_parent = bcm2835_clock_set_parent,
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+ .get_parent = bcm2835_clock_get_parent,
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};
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static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
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@@ -1319,7 +1371,9 @@ static const struct clk_ops bcm2835_vpu_
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.is_prepared = bcm2835_vpu_clock_is_on,
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.recalc_rate = bcm2835_clock_get_rate,
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.set_rate = bcm2835_clock_set_rate,
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- .round_rate = bcm2835_clock_round_rate,
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+ .determine_rate = bcm2835_clock_determine_rate,
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+ .set_parent = bcm2835_clock_set_parent,
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+ .get_parent = bcm2835_clock_get_parent,
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};
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static struct clk *bcm2835_register_pll(struct bcm2835_cprman *cprman,
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@@ -1413,45 +1467,23 @@ static struct clk *bcm2835_register_cloc
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{
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struct bcm2835_clock *clock;
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struct clk_init_data init;
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- const char *parent;
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+ const char *parents[1 << CM_SRC_BITS];
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+ size_t i;
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/*
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- * Most of the clock generators have a mux field, so we
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- * instantiate a generic mux as our parent to handle it.
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+ * Replace our "xosc" references with the oscillator's
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+ * actual name.
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*/
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- if (data->num_mux_parents) {
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- const char *parents[1 << CM_SRC_BITS];
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- int i;
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-
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- parent = devm_kasprintf(cprman->dev, GFP_KERNEL,
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- "mux_%s", data->name);
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- if (!parent)
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- return NULL;
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-
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- /*
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- * Replace our "xosc" references with the oscillator's
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- * actual name.
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- */
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- for (i = 0; i < data->num_mux_parents; i++) {
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- if (strcmp(data->parents[i], "xosc") == 0)
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- parents[i] = cprman->osc_name;
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- else
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- parents[i] = data->parents[i];
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- }
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-
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- clk_register_mux(cprman->dev, parent,
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- parents, data->num_mux_parents,
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- CLK_SET_RATE_PARENT,
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- cprman->regs + data->ctl_reg,
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- CM_SRC_SHIFT, CM_SRC_BITS,
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- 0, &cprman->regs_lock);
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- } else {
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- parent = data->parents[0];
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+ for (i = 0; i < data->num_mux_parents; i++) {
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+ if (strcmp(data->parents[i], "xosc") == 0)
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+ parents[i] = cprman->osc_name;
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+ else
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+ parents[i] = data->parents[i];
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}
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memset(&init, 0, sizeof(init));
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- init.parent_names = &parent;
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- init.num_parents = 1;
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+ init.parent_names = parents;
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+ init.num_parents = data->num_mux_parents;
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init.name = data->name;
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init.flags = CLK_IGNORE_UNUSED;
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