mirror of https://github.com/hak5/openwrt.git
519 lines
17 KiB
Diff
519 lines
17 KiB
Diff
From 3fcab2551c8649da57ad5fc5166f85edd870f641 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Fri, 17 Jul 2015 13:15:50 -0700
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Subject: [PATCH] drm/vc4: Add support for MSAA rendering.
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For MSAA, you set a bit in the binner that halves the size of tiles in
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each direction, so you can pack 4 samples per pixel in the tile
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buffer. During rendering, you can load and store raw tile buffer
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contents (to save the per-sample MSAA contents), or you can load/store
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resolved tile buffer contents (loads spam the pixel value to all 4
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samples, and stores either average the 4 color samples, or store the
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first sample for Z/S).
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/gpu/drm/vc4/vc4_packet.h | 23 ++-
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drivers/gpu/drm/vc4/vc4_render_cl.c | 274 ++++++++++++++++++++++++++++++------
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drivers/gpu/drm/vc4/vc4_validate.c | 5 +-
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include/uapi/drm/vc4_drm.h | 11 +-
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4 files changed, 258 insertions(+), 55 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_packet.h
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+++ b/drivers/gpu/drm/vc4/vc4_packet.h
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@@ -123,6 +123,11 @@ enum vc4_packet {
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#define VC4_PACKET_TILE_COORDINATES_SIZE 3
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#define VC4_PACKET_GEM_HANDLES_SIZE 9
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+/* Number of multisamples supported. */
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+#define VC4_MAX_SAMPLES 4
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+/* Size of a full resolution color or Z tile buffer load/store. */
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+#define VC4_TILE_BUFFER_SIZE (64 * 64 * 4)
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+
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/** @{
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* Bits used by packets like VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
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* VC4_PACKET_TILE_RENDERING_MODE_CONFIG.
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@@ -137,10 +142,20 @@ enum vc4_packet {
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* low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and
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* VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER.
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*/
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-#define VC4_LOADSTORE_FULL_RES_EOF (1 << 3)
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-#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL (1 << 2)
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-#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS (1 << 1)
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-#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR (1 << 0)
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+#define VC4_LOADSTORE_FULL_RES_EOF BIT(3)
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+#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2)
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+#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1)
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+#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0)
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+
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+/** @{
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+ *
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+ * low bits of VC4_PACKET_STORE_FULL_RES_TILE_BUFFER and
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+ * VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER.
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+ */
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+#define VC4_LOADSTORE_FULL_RES_EOF BIT(3)
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+#define VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL BIT(2)
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+#define VC4_LOADSTORE_FULL_RES_DISABLE_ZS BIT(1)
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+#define VC4_LOADSTORE_FULL_RES_DISABLE_COLOR BIT(0)
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/** @{
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*
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--- a/drivers/gpu/drm/vc4/vc4_render_cl.c
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+++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
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@@ -37,9 +37,11 @@
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struct vc4_rcl_setup {
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struct drm_gem_cma_object *color_read;
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- struct drm_gem_cma_object *color_ms_write;
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+ struct drm_gem_cma_object *color_write;
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struct drm_gem_cma_object *zs_read;
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struct drm_gem_cma_object *zs_write;
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+ struct drm_gem_cma_object *msaa_color_write;
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+ struct drm_gem_cma_object *msaa_zs_write;
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struct drm_gem_cma_object *rcl;
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u32 next_offset;
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@@ -82,6 +84,22 @@ static void vc4_store_before_load(struct
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}
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/*
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+ * Calculates the physical address of the start of a tile in a RCL surface.
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+ *
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+ * Unlike the other load/store packets,
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+ * VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER don't look at the tile
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+ * coordinates packet, and instead just store to the address given.
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+ */
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+static uint32_t vc4_full_res_offset(struct vc4_exec_info *exec,
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+ struct drm_gem_cma_object *bo,
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+ struct drm_vc4_submit_rcl_surface *surf,
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+ uint8_t x, uint8_t y)
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+{
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+ return bo->paddr + surf->offset + VC4_TILE_BUFFER_SIZE *
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+ (DIV_ROUND_UP(exec->args->width, 32) * y + x);
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+}
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+
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+/*
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* Emits a PACKET_TILE_COORDINATES if one isn't already pending.
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*
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* The tile coordinates packet triggers a pending load if there is one, are
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@@ -108,22 +126,41 @@ static void emit_tile(struct vc4_exec_in
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* may be outstanding at a time.
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*/
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if (setup->color_read) {
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- rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
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- rcl_u16(setup, args->color_read.bits);
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- rcl_u32(setup,
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- setup->color_read->paddr + args->color_read.offset);
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+ if (args->color_read.flags &
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+ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
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+ rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);
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+ rcl_u32(setup,
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+ vc4_full_res_offset(exec, setup->color_read,
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+ &args->color_read, x, y) |
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+ VC4_LOADSTORE_FULL_RES_DISABLE_ZS);
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+ } else {
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+ rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
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+ rcl_u16(setup, args->color_read.bits);
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+ rcl_u32(setup, setup->color_read->paddr +
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+ args->color_read.offset);
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+ }
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}
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if (setup->zs_read) {
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- if (setup->color_read) {
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- /* Exec previous load. */
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- vc4_tile_coordinates(setup, x, y);
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- vc4_store_before_load(setup);
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+ if (args->zs_read.flags &
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+ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
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+ rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER);
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+ rcl_u32(setup,
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+ vc4_full_res_offset(exec, setup->zs_read,
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+ &args->zs_read, x, y) |
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+ VC4_LOADSTORE_FULL_RES_DISABLE_COLOR);
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+ } else {
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+ if (setup->color_read) {
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+ /* Exec previous load. */
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+ vc4_tile_coordinates(setup, x, y);
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+ vc4_store_before_load(setup);
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+ }
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+
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+ rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
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+ rcl_u16(setup, args->zs_read.bits);
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+ rcl_u32(setup, setup->zs_read->paddr +
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+ args->zs_read.offset);
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}
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-
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- rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
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- rcl_u16(setup, args->zs_read.bits);
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- rcl_u32(setup, setup->zs_read->paddr + args->zs_read.offset);
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}
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/* Clipping depends on tile coordinates having been
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@@ -144,20 +181,60 @@ static void emit_tile(struct vc4_exec_in
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(y * exec->bin_tiles_x + x) * 32));
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}
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+ if (setup->msaa_color_write) {
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+ bool last_tile_write = (!setup->msaa_zs_write &&
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+ !setup->zs_write &&
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+ !setup->color_write);
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+ uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_ZS;
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+
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+ if (!last_tile_write)
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+ bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL;
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+ else if (last)
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+ bits |= VC4_LOADSTORE_FULL_RES_EOF;
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+ rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);
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+ rcl_u32(setup,
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+ vc4_full_res_offset(exec, setup->msaa_color_write,
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+ &args->msaa_color_write, x, y) |
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+ bits);
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+ }
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+
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+ if (setup->msaa_zs_write) {
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+ bool last_tile_write = (!setup->zs_write &&
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+ !setup->color_write);
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+ uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_COLOR;
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+
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+ if (setup->msaa_color_write)
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+ vc4_tile_coordinates(setup, x, y);
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+ if (!last_tile_write)
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+ bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL;
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+ else if (last)
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+ bits |= VC4_LOADSTORE_FULL_RES_EOF;
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+ rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER);
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+ rcl_u32(setup,
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+ vc4_full_res_offset(exec, setup->msaa_zs_write,
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+ &args->msaa_zs_write, x, y) |
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+ bits);
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+ }
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+
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if (setup->zs_write) {
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+ bool last_tile_write = !setup->color_write;
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+
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+ if (setup->msaa_color_write || setup->msaa_zs_write)
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+ vc4_tile_coordinates(setup, x, y);
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+
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rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
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rcl_u16(setup, args->zs_write.bits |
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- (setup->color_ms_write ?
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- VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR : 0));
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+ (last_tile_write ?
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+ 0 : VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR));
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rcl_u32(setup,
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(setup->zs_write->paddr + args->zs_write.offset) |
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- ((last && !setup->color_ms_write) ?
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+ ((last && last_tile_write) ?
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VC4_LOADSTORE_TILE_BUFFER_EOF : 0));
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}
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- if (setup->color_ms_write) {
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- if (setup->zs_write) {
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- /* Reset after previous store */
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+ if (setup->color_write) {
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+ if (setup->msaa_color_write || setup->msaa_zs_write ||
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+ setup->zs_write) {
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vc4_tile_coordinates(setup, x, y);
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}
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@@ -192,14 +269,26 @@ static int vc4_create_rcl_bo(struct drm_
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}
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if (setup->color_read) {
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- loop_body_size += (VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE);
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+ if (args->color_read.flags &
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+ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
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+ loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE;
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+ } else {
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+ loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE;
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+ }
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}
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if (setup->zs_read) {
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- if (setup->color_read) {
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- loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE;
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- loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
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+ if (args->zs_read.flags &
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+ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
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+ loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE;
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+ } else {
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+ if (setup->color_read &&
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+ !(args->color_read.flags &
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+ VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES)) {
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+ loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE;
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+ loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
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+ }
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+ loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE;
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}
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- loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE;
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}
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if (has_bin) {
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@@ -207,13 +296,23 @@ static int vc4_create_rcl_bo(struct drm_
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loop_body_size += VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE;
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}
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+ if (setup->msaa_color_write)
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+ loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE;
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+ if (setup->msaa_zs_write)
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+ loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE;
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+
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if (setup->zs_write)
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loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE;
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- if (setup->color_ms_write) {
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- if (setup->zs_write)
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- loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE;
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+ if (setup->color_write)
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loop_body_size += VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE;
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- }
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+
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+ /* We need a VC4_PACKET_TILE_COORDINATES in between each store. */
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+ loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE *
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+ ((setup->msaa_color_write != NULL) +
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+ (setup->msaa_zs_write != NULL) +
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+ (setup->color_write != NULL) +
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+ (setup->zs_write != NULL) - 1);
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+
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size += xtiles * ytiles * loop_body_size;
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setup->rcl = &vc4_bo_create(dev, size, true)->base;
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@@ -224,13 +323,12 @@ static int vc4_create_rcl_bo(struct drm_
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rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG);
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rcl_u32(setup,
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- (setup->color_ms_write ?
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- (setup->color_ms_write->paddr +
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- args->color_ms_write.offset) :
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+ (setup->color_write ? (setup->color_write->paddr +
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+ args->color_write.offset) :
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0));
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rcl_u16(setup, args->width);
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rcl_u16(setup, args->height);
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- rcl_u16(setup, args->color_ms_write.bits);
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+ rcl_u16(setup, args->color_write.bits);
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/* The tile buffer gets cleared when the previous tile is stored. If
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* the clear values changed between frames, then the tile buffer has
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@@ -267,6 +365,56 @@ static int vc4_create_rcl_bo(struct drm_
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return 0;
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}
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+static int vc4_full_res_bounds_check(struct vc4_exec_info *exec,
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+ struct drm_gem_cma_object *obj,
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+ struct drm_vc4_submit_rcl_surface *surf)
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+{
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+ struct drm_vc4_submit_cl *args = exec->args;
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+ u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width, 32);
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+
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+ if (surf->offset > obj->base.size) {
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+ DRM_ERROR("surface offset %d > BO size %zd\n",
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+ surf->offset, obj->base.size);
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+ return -EINVAL;
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+ }
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+
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+ if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE <
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+ render_tiles_stride * args->max_y_tile + args->max_x_tile) {
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+ DRM_ERROR("MSAA tile %d, %d out of bounds "
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+ "(bo size %zd, offset %d).\n",
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+ args->max_x_tile, args->max_y_tile,
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+ obj->base.size,
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+ surf->offset);
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec,
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+ struct drm_gem_cma_object **obj,
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+ struct drm_vc4_submit_rcl_surface *surf)
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+{
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+ if (surf->flags != 0 || surf->bits != 0) {
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+ DRM_ERROR("MSAA surface had nonzero flags/bits\n");
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+ return -EINVAL;
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+ }
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+
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+ if (surf->hindex == ~0)
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+ return 0;
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+
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+ *obj = vc4_use_bo(exec, surf->hindex);
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+ if (!*obj)
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+ return -EINVAL;
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+
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+ if (surf->offset & 0xf) {
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+ DRM_ERROR("MSAA write must be 16b aligned.\n");
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+ return -EINVAL;
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+ }
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+
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+ return vc4_full_res_bounds_check(exec, *obj, surf);
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+}
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+
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static int vc4_rcl_surface_setup(struct vc4_exec_info *exec,
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struct drm_gem_cma_object **obj,
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struct drm_vc4_submit_rcl_surface *surf)
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@@ -278,9 +426,10 @@ static int vc4_rcl_surface_setup(struct
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uint8_t format = VC4_GET_FIELD(surf->bits,
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VC4_LOADSTORE_TILE_BUFFER_FORMAT);
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int cpp;
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+ int ret;
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- if (surf->pad != 0) {
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- DRM_ERROR("Padding unset\n");
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+ if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
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+ DRM_ERROR("Extra flags set\n");
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return -EINVAL;
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}
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@@ -290,6 +439,25 @@ static int vc4_rcl_surface_setup(struct
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if (!vc4_use_bo(exec, surf->hindex, VC4_MODE_RENDER, obj))
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return -EINVAL;
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+ if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) {
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+ if (surf == &exec->args->zs_write) {
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+ DRM_ERROR("general zs write may not be a full-res.\n");
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+ return -EINVAL;
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+ }
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+
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+ if (surf->bits != 0) {
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+ DRM_ERROR("load/store general bits set with "
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+ "full res load/store.\n");
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+ return -EINVAL;
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+ }
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+
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+ ret = vc4_full_res_bounds_check(exec, *obj, surf);
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+ if (!ret)
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+ return ret;
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+
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+ return 0;
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+ }
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+
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if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK |
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VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK |
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VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK)) {
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@@ -341,9 +509,10 @@ static int vc4_rcl_surface_setup(struct
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}
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static int
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-vc4_rcl_ms_surface_setup(struct vc4_exec_info *exec,
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- struct drm_gem_cma_object **obj,
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- struct drm_vc4_submit_rcl_surface *surf)
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+vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec,
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+ struct vc4_rcl_setup *setup,
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+ struct drm_gem_cma_object **obj,
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+ struct drm_vc4_submit_rcl_surface *surf)
|
|
{
|
|
uint8_t tiling = VC4_GET_FIELD(surf->bits,
|
|
VC4_RENDER_CONFIG_MEMORY_FORMAT);
|
|
@@ -351,13 +520,15 @@ vc4_rcl_ms_surface_setup(struct vc4_exec
|
|
VC4_RENDER_CONFIG_FORMAT);
|
|
int cpp;
|
|
|
|
- if (surf->pad != 0) {
|
|
- DRM_ERROR("Padding unset\n");
|
|
+ if (surf->flags != 0) {
|
|
+ DRM_ERROR("No flags supported on render config.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (surf->bits & ~(VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK |
|
|
- VC4_RENDER_CONFIG_FORMAT_MASK)) {
|
|
+ VC4_RENDER_CONFIG_FORMAT_MASK |
|
|
+ VC4_RENDER_CONFIG_MS_MODE_4X |
|
|
+ VC4_RENDER_CONFIG_DECIMATE_MODE_4X)) {
|
|
DRM_ERROR("Unknown bits in render config: 0x%04x\n",
|
|
surf->bits);
|
|
return -EINVAL;
|
|
@@ -413,18 +584,20 @@ int vc4_get_rcl(struct drm_device *dev,
|
|
if (has_bin &&
|
|
(args->max_x_tile > exec->bin_tiles_x ||
|
|
args->max_y_tile > exec->bin_tiles_y)) {
|
|
- DRM_ERROR("Render tiles (%d,%d) outside of bin config (%d,%d)\n",
|
|
+ DRM_ERROR("Render tiles (%d,%d) outside of bin config "
|
|
+ "(%d,%d)\n",
|
|
args->max_x_tile, args->max_y_tile,
|
|
exec->bin_tiles_x, exec->bin_tiles_y);
|
|
return -EINVAL;
|
|
}
|
|
|
|
- ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read);
|
|
+ ret = vc4_rcl_render_config_surface_setup(exec, &setup,
|
|
+ &setup.color_write,
|
|
+ &args->color_write);
|
|
if (ret)
|
|
return ret;
|
|
|
|
- ret = vc4_rcl_ms_surface_setup(exec, &setup.color_ms_write,
|
|
- &args->color_ms_write);
|
|
+ ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read);
|
|
if (ret)
|
|
return ret;
|
|
|
|
@@ -436,10 +609,21 @@ int vc4_get_rcl(struct drm_device *dev,
|
|
if (ret)
|
|
return ret;
|
|
|
|
+ ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_color_write,
|
|
+ &args->msaa_color_write);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_zs_write,
|
|
+ &args->msaa_zs_write);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
/* We shouldn't even have the job submitted to us if there's no
|
|
* surface to write out.
|
|
*/
|
|
- if (!setup.color_ms_write && !setup.zs_write) {
|
|
+ if (!setup.color_write && !setup.zs_write &&
|
|
+ !setup.msaa_color_write && !setup.msaa_zs_write) {
|
|
DRM_ERROR("RCL requires color or Z/S write\n");
|
|
return -EINVAL;
|
|
}
|
|
--- a/drivers/gpu/drm/vc4/vc4_validate.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_validate.c
|
|
@@ -400,9 +400,8 @@ validate_tile_binning_config(VALIDATE_AR
|
|
}
|
|
|
|
if (flags & (VC4_BIN_CONFIG_DB_NON_MS |
|
|
- VC4_BIN_CONFIG_TILE_BUFFER_64BIT |
|
|
- VC4_BIN_CONFIG_MS_MODE_4X)) {
|
|
- DRM_ERROR("unsupported bining config flags 0x%02x\n", flags);
|
|
+ VC4_BIN_CONFIG_TILE_BUFFER_64BIT)) {
|
|
+ DRM_ERROR("unsupported binning config flags 0x%02x\n", flags);
|
|
return -EINVAL;
|
|
}
|
|
|
|
--- a/include/uapi/drm/vc4_drm.h
|
|
+++ b/include/uapi/drm/vc4_drm.h
|
|
@@ -46,10 +46,13 @@ struct drm_vc4_submit_rcl_surface {
|
|
uint32_t hindex; /* Handle index, or ~0 if not present. */
|
|
uint32_t offset; /* Offset to start of buffer. */
|
|
/*
|
|
- * Bits for either render config (color_ms_write) or load/store packet.
|
|
+ * Bits for either render config (color_write) or load/store packet.
|
|
+ * Bits should all be 0 for MSAA load/stores.
|
|
*/
|
|
uint16_t bits;
|
|
- uint16_t pad;
|
|
+
|
|
+#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
|
|
+ uint16_t flags;
|
|
};
|
|
|
|
/**
|
|
@@ -128,9 +131,11 @@ struct drm_vc4_submit_cl {
|
|
uint8_t max_x_tile;
|
|
uint8_t max_y_tile;
|
|
struct drm_vc4_submit_rcl_surface color_read;
|
|
- struct drm_vc4_submit_rcl_surface color_ms_write;
|
|
+ struct drm_vc4_submit_rcl_surface color_write;
|
|
struct drm_vc4_submit_rcl_surface zs_read;
|
|
struct drm_vc4_submit_rcl_surface zs_write;
|
|
+ struct drm_vc4_submit_rcl_surface msaa_color_write;
|
|
+ struct drm_vc4_submit_rcl_surface msaa_zs_write;
|
|
uint32_t clear_color[2];
|
|
uint32_t clear_z;
|
|
uint8_t clear_s;
|