mirror of https://github.com/hak5/openwrt.git
321 lines
9.4 KiB
Diff
321 lines
9.4 KiB
Diff
From c9f03ab8241d445daebd5fb8c4cf63c976460e2d Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Noralf=20Tr=C3=B8nnes?= <noralf@tronnes.org>
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Date: Thu, 9 Apr 2015 12:34:11 +0200
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Subject: [PATCH] dmaengine: bcm2835: Add slave dma support
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Add slave transfer capability to BCM2835 dmaengine driver.
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This patch is pulled from the bcm2708-dmaengine driver in the
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Raspberry Pi repo. The work was done by Gellert Weisz.
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Tested using the bcm2835-mmc driver from the same repo.
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Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
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---
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drivers/dma/bcm2835-dma.c | 206 ++++++++++++++++++++++++++++++++++++++++++----
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1 file changed, 192 insertions(+), 14 deletions(-)
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--- a/drivers/dma/bcm2835-dma.c
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+++ b/drivers/dma/bcm2835-dma.c
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@@ -1,11 +1,10 @@
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/*
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* BCM2835 DMA engine support
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*
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- * This driver only supports cyclic DMA transfers
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- * as needed for the I2S module.
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- *
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* Author: Florian Meier <florian.meier@koalo.de>
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* Copyright 2013
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+ * Gellert Weisz <gellert@raspberrypi.org>
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+ * Copyright 2013-2014
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*
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* Based on
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* OMAP DMAengine support by Russell King
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@@ -95,6 +94,8 @@ struct bcm2835_desc {
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size_t size;
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};
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+#define BCM2835_DMA_WAIT_CYCLES 0 /* Slow down DMA transfers: 0-31 */
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+
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#define BCM2835_DMA_CS 0x00
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#define BCM2835_DMA_ADDR 0x04
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#define BCM2835_DMA_SOURCE_AD 0x0c
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@@ -111,12 +112,16 @@ struct bcm2835_desc {
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#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
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#define BCM2835_DMA_INT_EN BIT(0)
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+#define BCM2835_DMA_WAIT_RESP BIT(3)
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#define BCM2835_DMA_D_INC BIT(4)
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+#define BCM2835_DMA_D_WIDTH BIT(5)
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#define BCM2835_DMA_D_DREQ BIT(6)
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#define BCM2835_DMA_S_INC BIT(8)
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+#define BCM2835_DMA_S_WIDTH BIT(9)
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#define BCM2835_DMA_S_DREQ BIT(10)
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#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
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+#define BCM2835_DMA_WAITS(x) (((x) & 0x1f) << 21)
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#define BCM2835_DMA_DATA_TYPE_S8 1
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#define BCM2835_DMA_DATA_TYPE_S16 2
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@@ -130,6 +135,14 @@ struct bcm2835_desc {
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#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
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#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
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+#define MAX_NORMAL_TRANSFER SZ_1G
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+/*
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+ * Max length on a Lite channel is 65535 bytes.
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+ * DMA handles byte-enables on SDRAM reads and writes even on 128-bit accesses,
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+ * but byte-enables don't exist on peripheral addresses, so align to 32-bit.
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+ */
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+#define MAX_LITE_TRANSFER (SZ_64K - 4)
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+
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static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
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{
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return container_of(d, struct bcm2835_dmadev, ddev);
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@@ -226,12 +239,18 @@ static irqreturn_t bcm2835_dma_callback(
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d = c->desc;
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if (d) {
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- /* TODO Only works for cyclic DMA */
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- vchan_cyclic_callback(&d->vd);
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- }
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+ if (c->cyclic) {
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+ vchan_cyclic_callback(&d->vd);
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- /* Keep the DMA engine running */
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- writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
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+ /* Keep the DMA engine running */
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+ writel(BCM2835_DMA_ACTIVE,
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+ c->chan_base + BCM2835_DMA_CS);
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+
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+ } else {
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+ vchan_cookie_complete(&c->desc->vd);
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+ bcm2835_dma_start_desc(c);
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+ }
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+ }
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spin_unlock_irqrestore(&c->vc.lock, flags);
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@@ -339,8 +358,6 @@ static void bcm2835_dma_issue_pending(st
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struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
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unsigned long flags;
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- c->cyclic = true; /* Nothing else is implemented */
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-
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spin_lock_irqsave(&c->vc.lock, flags);
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if (vchan_issue_pending(&c->vc) && !c->desc)
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bcm2835_dma_start_desc(c);
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@@ -358,7 +375,7 @@ static struct dma_async_tx_descriptor *b
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struct bcm2835_desc *d;
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dma_addr_t dev_addr;
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unsigned int es, sync_type;
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- unsigned int frame;
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+ unsigned int frame, max_size;
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int i;
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/* Grab configuration */
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@@ -393,7 +410,12 @@ static struct dma_async_tx_descriptor *b
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d->c = c;
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d->dir = direction;
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- d->frames = buf_len / period_len;
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+ if (c->ch >= 8) /* LITE channel */
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+ max_size = MAX_LITE_TRANSFER;
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+ else
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+ max_size = MAX_NORMAL_TRANSFER;
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+ period_len = min(period_len, max_size);
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+ d->frames = (buf_len - 1) / (period_len + 1);
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d->cb_list = kcalloc(d->frames, sizeof(*d->cb_list), GFP_KERNEL);
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if (!d->cb_list) {
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@@ -441,17 +463,171 @@ static struct dma_async_tx_descriptor *b
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BCM2835_DMA_PER_MAP(c->dreq);
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/* Length of a frame */
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- control_block->length = period_len;
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+ if (frame != d->frames - 1)
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+ control_block->length = period_len;
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+ else
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+ control_block->length = buf_len - (d->frames - 1) *
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+ period_len;
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d->size += control_block->length;
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/*
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* Next block is the next frame.
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- * This DMA engine driver currently only supports cyclic DMA.
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+ * This function is called on cyclic DMA transfers.
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* Therefore, wrap around at number of frames.
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*/
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control_block->next = d->cb_list[((frame + 1) % d->frames)].paddr;
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}
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+ c->cyclic = true;
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+
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+ return vchan_tx_prep(&c->vc, &d->vd, flags);
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+}
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+
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+static struct dma_async_tx_descriptor *
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+bcm2835_dma_prep_slave_sg(struct dma_chan *chan,
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+ struct scatterlist *sgl,
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+ unsigned int sg_len,
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+ enum dma_transfer_direction direction,
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+ unsigned long flags, void *context)
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+{
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+ struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
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+ enum dma_slave_buswidth dev_width;
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+ struct bcm2835_desc *d;
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+ dma_addr_t dev_addr;
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+ struct scatterlist *sgent;
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+ unsigned int i, sync_type, split_cnt, max_size;
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+
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+ if (!is_slave_direction(direction)) {
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+ dev_err(chan->device->dev, "direction not supported\n");
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+ return NULL;
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+ }
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+
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+ if (direction == DMA_DEV_TO_MEM) {
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+ dev_addr = c->cfg.src_addr;
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+ dev_width = c->cfg.src_addr_width;
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+ sync_type = BCM2835_DMA_S_DREQ;
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+ } else {
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+ dev_addr = c->cfg.dst_addr;
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+ dev_width = c->cfg.dst_addr_width;
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+ sync_type = BCM2835_DMA_D_DREQ;
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+ }
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+
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+ /* Bus width translates to the element size (ES) */
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+ switch (dev_width) {
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+ case DMA_SLAVE_BUSWIDTH_4_BYTES:
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+ break;
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+ default:
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+ dev_err(chan->device->dev, "buswidth not supported: %i\n",
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+ dev_width);
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+ return NULL;
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+ }
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+
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+ /* Allocate and setup the descriptor. */
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+ d = kzalloc(sizeof(*d), GFP_NOWAIT);
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+ if (!d)
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+ return NULL;
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+
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+ d->dir = direction;
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+
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+ if (c->ch >= 8) /* LITE channel */
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+ max_size = MAX_LITE_TRANSFER;
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+ else
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+ max_size = MAX_NORMAL_TRANSFER;
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+
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+ /*
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+ * Store the length of the SG list in d->frames
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+ * taking care to account for splitting up transfers
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+ * too large for a LITE channel
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+ */
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+ d->frames = 0;
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+ for_each_sg(sgl, sgent, sg_len, i) {
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+ unsigned int len = sg_dma_len(sgent);
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+
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+ d->frames += len / max_size + 1;
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+ }
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+
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+ /* Allocate memory for control blocks */
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+ d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
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+ d->control_block_base = dma_zalloc_coherent(chan->device->dev,
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+ d->control_block_size, &d->control_block_base_phys,
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+ GFP_NOWAIT);
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+ if (!d->control_block_base) {
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+ kfree(d);
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+ return NULL;
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+ }
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+
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+ /*
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+ * Iterate over all SG entries, create a control block
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+ * for each frame and link them together.
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+ * Count the number of times an SG entry had to be split
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+ * as a result of using a LITE channel
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+ */
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+ split_cnt = 0;
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+
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+ for_each_sg(sgl, sgent, sg_len, i) {
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+ unsigned int j;
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+ dma_addr_t addr = sg_dma_address(sgent);
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+ unsigned int len = sg_dma_len(sgent);
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+
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+ for (j = 0; j < len; j += max_size) {
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+ struct bcm2835_dma_cb *control_block =
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+ &d->control_block_base[i + split_cnt];
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+
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+ /* Setup addresses */
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+ if (d->dir == DMA_DEV_TO_MEM) {
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+ control_block->info = BCM2835_DMA_D_INC |
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+ BCM2835_DMA_D_WIDTH |
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+ BCM2835_DMA_S_DREQ;
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+ control_block->src = dev_addr;
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+ control_block->dst = addr + (dma_addr_t)j;
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+ } else {
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+ control_block->info = BCM2835_DMA_S_INC |
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+ BCM2835_DMA_S_WIDTH |
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+ BCM2835_DMA_D_DREQ;
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+ control_block->src = addr + (dma_addr_t)j;
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+ control_block->dst = dev_addr;
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+ }
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+
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+ /* Common part */
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+ control_block->info |=
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+ BCM2835_DMA_WAITS(BCM2835_DMA_WAIT_CYCLES);
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+ control_block->info |= BCM2835_DMA_WAIT_RESP;
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+
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+ /* Enable */
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+ if (i == sg_len - 1 && len - j <= max_size)
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+ control_block->info |= BCM2835_DMA_INT_EN;
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+
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+ /* Setup synchronization */
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+ if (sync_type)
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+ control_block->info |= sync_type;
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+
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+ /* Setup DREQ channel */
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+ if (c->dreq)
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+ control_block->info |=
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+ BCM2835_DMA_PER_MAP(c->dreq);
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+
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+ /* Length of a frame */
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+ control_block->length = min(len - j, max_size);
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+ d->size += control_block->length;
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+
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+ if (i < sg_len - 1 || len - j > max_size) {
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+ /* Next block is the next frame. */
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+ control_block->next =
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+ d->control_block_base_phys +
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+ sizeof(struct bcm2835_dma_cb) *
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+ (i + split_cnt + 1);
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+ } else {
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+ /* Next block is empty. */
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+ control_block->next = 0;
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+ }
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+
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+ if (len - j > max_size)
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+ split_cnt++;
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+ }
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+ }
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+
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+ c->cyclic = false;
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+
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return vchan_tx_prep(&c->vc, &d->vd, flags);
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error_cb:
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i--;
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@@ -620,6 +796,7 @@ static int bcm2835_dma_probe(struct plat
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od->ddev.device_tx_status = bcm2835_dma_tx_status;
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od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
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od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
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+ od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
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od->ddev.device_config = bcm2835_dma_slave_config;
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od->ddev.device_terminate_all = bcm2835_dma_terminate_all;
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od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
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@@ -708,4 +885,5 @@ module_platform_driver(bcm2835_dma_drive
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MODULE_ALIAS("platform:bcm2835-dma");
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MODULE_DESCRIPTION("BCM2835 DMA engine driver");
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MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
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+MODULE_AUTHOR("Gellert Weisz <gellert@raspberrypi.org>");
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MODULE_LICENSE("GPL v2");
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