mirror of https://github.com/hak5/openwrt.git
131 lines
3.3 KiB
Diff
131 lines
3.3 KiB
Diff
From ea5f4d6f4716f3a0bb4fc3614b7a0e8c0df1cb81 Mon Sep 17 00:00:00 2001
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From: Matthew McClintock <mmcclint@codeaurora.org>
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Date: Thu, 17 Mar 2016 16:22:28 -0500
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Subject: [PATCH] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
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This adds the SoC nodes to the ipq4019 device tree and
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enable it for the DK01.1 board.
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Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
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---
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Changes:
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- replaced space with tab
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- added sleep and mock_utmi clocks
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- added registers for usb2 and usb3 parent node
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- changed compatible to qca,ipa4019-dwc3
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- updated usb2 and usb3 names
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(included the reg - in case they become necessary later)
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---
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arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 ++++++++
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 71 +++++++++++++++++++++++++++
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2 files changed, 91 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
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@@ -108,5 +108,25 @@
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watchdog@b017000 {
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status = "ok";
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};
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+
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+ usb3_ss_phy: ssphy@9a000 {
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+ status = "ok";
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+ };
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+
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+ usb3_hs_phy: hsphy@a6000 {
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+ status = "ok";
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+ };
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+
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+ usb3: usb3@8af8800 {
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+ status = "ok";
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+ };
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+
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+ usb2_hs_phy: hsphy@a8000 {
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+ status = "ok";
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+ };
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+
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+ usb2: usb2@60f8800 {
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+ status = "ok";
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+ };
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -313,5 +313,76 @@
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compatible = "qcom,pshold";
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reg = <0x4ab000 0x4>;
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};
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+
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+ usb3_ss_phy: ssphy@9a000 {
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+ compatible = "qca,uni-ssphy";
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+ reg = <0x9a000 0x800>;
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+ reg-names = "phy_base";
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+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
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+ reset-names = "por_rst";
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+ status = "disabled";
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+ };
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+
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+ usb3_hs_phy: hsphy@a6000 {
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+ compatible = "qca,baldur-usb3-hsphy";
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+ reg = <0xa6000 0x40>;
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+ reg-names = "phy_base";
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+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
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+ reset-names = "por_rst", "srif_rst";
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+ status = "disabled";
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+ };
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+
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+ usb3@8af8800 {
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+ compatible = "qca,ipq4019-dwc3";
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+ reg = <0x8af8800 0x100>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
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+ <&gcc GCC_USB3_SLEEP_CLK>,
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+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
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+ clock-names = "master", "sleep", "mock_utmi";
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+ ranges;
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+ status = "disabled";
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+
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+ dwc3@8a00000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x8a00000 0xf8000>;
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+ interrupts = <0 132 0>;
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+ usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ dr_mode = "host";
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+ };
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+ };
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+
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+ usb2_hs_phy: hsphy@a8000 {
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+ compatible = "qca,baldur-usb2-hsphy";
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+ reg = <0xa8000 0x40>;
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+ reg-names = "phy_base";
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+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
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+ reset-names = "por_rst", "srif_rst";
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+ status = "disabled";
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+ };
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+
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+ usb2@60f8800 {
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+ compatible = "qca,ipq4019-dwc3";
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+ reg = <0x60f8800 0x100>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
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+ <&gcc GCC_USB2_SLEEP_CLK>,
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+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
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+ clock-names = "master", "sleep", "mock_utmi";
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+ ranges;
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+ status = "disabled";
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+
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+ dwc3@6000000 {
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+ compatible = "snps,dwc3";
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+ reg = <0x6000000 0xf8000>;
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+ interrupts = <0 136 0>;
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+ usb-phy = <&usb2_hs_phy>;
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+ phy-names = "usb2-phy";
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+ dr_mode = "host";
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+ };
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+ };
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};
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};
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