mirror of https://github.com/hak5/openwrt.git
359 lines
12 KiB
Diff
359 lines
12 KiB
Diff
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
@@ -21,6 +21,10 @@
|
|
#include <linux/bitops.h>
|
|
|
|
#define AR71XX_APB_BASE 0x18000000
|
|
+#define AR71XX_GE0_BASE 0x19000000
|
|
+#define AR71XX_GE0_SIZE 0x10000
|
|
+#define AR71XX_GE1_BASE 0x1a000000
|
|
+#define AR71XX_GE1_SIZE 0x10000
|
|
#define AR71XX_EHCI_BASE 0x1b000000
|
|
#define AR71XX_EHCI_SIZE 0x1000
|
|
#define AR71XX_OHCI_BASE 0x1c000000
|
|
@@ -40,6 +44,8 @@
|
|
#define AR71XX_PLL_SIZE 0x100
|
|
#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
|
|
#define AR71XX_RESET_SIZE 0x100
|
|
+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
|
|
+#define AR71XX_MII_SIZE 0x100
|
|
|
|
#define AR71XX_PCI_MEM_BASE 0x10000000
|
|
#define AR71XX_PCI_MEM_SIZE 0x07000000
|
|
@@ -82,15 +88,21 @@
|
|
|
|
#define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
|
|
#define AR933X_UART_SIZE 0x14
|
|
+#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
|
|
+#define AR933X_GMAC_SIZE 0x04
|
|
#define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
|
|
#define AR933X_WMAC_SIZE 0x20000
|
|
#define AR933X_EHCI_BASE 0x1b000000
|
|
#define AR933X_EHCI_SIZE 0x1000
|
|
|
|
+#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
|
|
+#define AR934X_GMAC_SIZE 0x14
|
|
#define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
|
|
#define AR934X_WMAC_SIZE 0x20000
|
|
#define AR934X_EHCI_BASE 0x1b000000
|
|
#define AR934X_EHCI_SIZE 0x200
|
|
+#define AR934X_NFC_BASE 0x1b000200
|
|
+#define AR934X_NFC_SIZE 0xb8
|
|
#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
|
|
#define AR934X_SRIF_SIZE 0x1000
|
|
|
|
@@ -107,11 +119,15 @@
|
|
#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
|
|
#define QCA955X_PCI_CTRL_SIZE 0x100
|
|
|
|
+#define QCA955X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
|
|
+#define QCA955X_GMAC_SIZE 0x40
|
|
#define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
|
|
#define QCA955X_WMAC_SIZE 0x20000
|
|
#define QCA955X_EHCI0_BASE 0x1b000000
|
|
#define QCA955X_EHCI1_BASE 0x1b400000
|
|
#define QCA955X_EHCI_SIZE 0x1000
|
|
+#define QCA955X_NFC_BASE 0x1b800200
|
|
+#define QCA955X_NFC_SIZE 0xb8
|
|
|
|
#define AR9300_OTP_BASE 0x14000
|
|
#define AR9300_OTP_STATUS 0x15f18
|
|
@@ -175,6 +191,9 @@
|
|
#define AR71XX_AHB_DIV_SHIFT 20
|
|
#define AR71XX_AHB_DIV_MASK 0x7
|
|
|
|
+#define AR71XX_ETH0_PLL_SHIFT 17
|
|
+#define AR71XX_ETH1_PLL_SHIFT 19
|
|
+
|
|
#define AR724X_PLL_REG_CPU_CONFIG 0x00
|
|
#define AR724X_PLL_REG_PCIE_CONFIG 0x18
|
|
|
|
@@ -187,6 +206,8 @@
|
|
#define AR724X_DDR_DIV_SHIFT 22
|
|
#define AR724X_DDR_DIV_MASK 0x3
|
|
|
|
+#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
|
|
+
|
|
#define AR913X_PLL_REG_CPU_CONFIG 0x00
|
|
#define AR913X_PLL_REG_ETH_CONFIG 0x04
|
|
#define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
|
|
@@ -199,6 +220,9 @@
|
|
#define AR913X_AHB_DIV_SHIFT 19
|
|
#define AR913X_AHB_DIV_MASK 0x1
|
|
|
|
+#define AR913X_ETH0_PLL_SHIFT 20
|
|
+#define AR913X_ETH1_PLL_SHIFT 22
|
|
+
|
|
#define AR933X_PLL_CPU_CONFIG_REG 0x00
|
|
#define AR933X_PLL_CLOCK_CTRL_REG 0x08
|
|
|
|
@@ -220,6 +244,8 @@
|
|
#define AR934X_PLL_CPU_CONFIG_REG 0x00
|
|
#define AR934X_PLL_DDR_CONFIG_REG 0x04
|
|
#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
|
|
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
|
|
+#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
|
|
|
|
#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
|
|
#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
|
|
@@ -252,9 +278,13 @@
|
|
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
|
|
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
|
|
|
|
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
|
|
+
|
|
#define QCA955X_PLL_CPU_CONFIG_REG 0x00
|
|
#define QCA955X_PLL_DDR_CONFIG_REG 0x04
|
|
#define QCA955X_PLL_CLK_CTRL_REG 0x08
|
|
+#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
|
|
+#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
|
|
|
|
#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
|
|
#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
|
|
@@ -379,16 +409,83 @@
|
|
#define AR913X_RESET_USB_HOST BIT(5)
|
|
#define AR913X_RESET_USB_PHY BIT(4)
|
|
|
|
+#define AR933X_RESET_GE1_MDIO BIT(23)
|
|
+#define AR933X_RESET_GE0_MDIO BIT(22)
|
|
+#define AR933X_RESET_GE1_MAC BIT(13)
|
|
#define AR933X_RESET_WMAC BIT(11)
|
|
+#define AR933X_RESET_GE0_MAC BIT(9)
|
|
#define AR933X_RESET_USB_HOST BIT(5)
|
|
#define AR933X_RESET_USB_PHY BIT(4)
|
|
#define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
|
|
|
|
+#define AR934X_RESET_HOST BIT(31)
|
|
+#define AR934X_RESET_SLIC BIT(30)
|
|
+#define AR934X_RESET_HDMA BIT(29)
|
|
+#define AR934X_RESET_EXTERNAL BIT(28)
|
|
+#define AR934X_RESET_RTC BIT(27)
|
|
+#define AR934X_RESET_PCIE_EP_INT BIT(26)
|
|
+#define AR934X_RESET_CHKSUM_ACC BIT(25)
|
|
+#define AR934X_RESET_FULL_CHIP BIT(24)
|
|
+#define AR934X_RESET_GE1_MDIO BIT(23)
|
|
+#define AR934X_RESET_GE0_MDIO BIT(22)
|
|
+#define AR934X_RESET_CPU_NMI BIT(21)
|
|
+#define AR934X_RESET_CPU_COLD BIT(20)
|
|
+#define AR934X_RESET_HOST_RESET_INT BIT(19)
|
|
+#define AR934X_RESET_PCIE_EP BIT(18)
|
|
+#define AR934X_RESET_UART1 BIT(17)
|
|
+#define AR934X_RESET_DDR BIT(16)
|
|
+#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
|
|
+#define AR934X_RESET_NANDF BIT(14)
|
|
+#define AR934X_RESET_GE1_MAC BIT(13)
|
|
+#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
|
|
#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
|
|
+#define AR934X_RESET_HOST_DMA_INT BIT(10)
|
|
+#define AR934X_RESET_GE0_MAC BIT(9)
|
|
+#define AR934X_RESET_ETH_SWITCH BIT(8)
|
|
+#define AR934X_RESET_PCIE_PHY BIT(7)
|
|
+#define AR934X_RESET_PCIE BIT(6)
|
|
#define AR934X_RESET_USB_HOST BIT(5)
|
|
#define AR934X_RESET_USB_PHY BIT(4)
|
|
#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
|
|
+#define AR934X_RESET_LUT BIT(2)
|
|
+#define AR934X_RESET_MBOX BIT(1)
|
|
+#define AR934X_RESET_I2S BIT(0)
|
|
+
|
|
+#define QCA955X_RESET_HOST BIT(31)
|
|
+#define QCA955X_RESET_SLIC BIT(30)
|
|
+#define QCA955X_RESET_HDMA BIT(29)
|
|
+#define QCA955X_RESET_EXTERNAL BIT(28)
|
|
+#define QCA955X_RESET_RTC BIT(27)
|
|
+#define QCA955X_RESET_PCIE_EP_INT BIT(26)
|
|
+#define QCA955X_RESET_CHKSUM_ACC BIT(25)
|
|
+#define QCA955X_RESET_FULL_CHIP BIT(24)
|
|
+#define QCA955X_RESET_GE1_MDIO BIT(23)
|
|
+#define QCA955X_RESET_GE0_MDIO BIT(22)
|
|
+#define QCA955X_RESET_CPU_NMI BIT(21)
|
|
+#define QCA955X_RESET_CPU_COLD BIT(20)
|
|
+#define QCA955X_RESET_HOST_RESET_INT BIT(19)
|
|
+#define QCA955X_RESET_PCIE_EP BIT(18)
|
|
+#define QCA955X_RESET_UART1 BIT(17)
|
|
+#define QCA955X_RESET_DDR BIT(16)
|
|
+#define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
|
|
+#define QCA955X_RESET_NANDF BIT(14)
|
|
+#define QCA955X_RESET_GE1_MAC BIT(13)
|
|
+#define QCA955X_RESET_SGMII_ANALOG BIT(12)
|
|
+#define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
|
|
+#define QCA955X_RESET_HOST_DMA_INT BIT(10)
|
|
+#define QCA955X_RESET_GE0_MAC BIT(9)
|
|
+#define QCA955X_RESET_SGMII BIT(8)
|
|
+#define QCA955X_RESET_PCIE_PHY BIT(7)
|
|
+#define QCA955X_RESET_PCIE BIT(6)
|
|
+#define QCA955X_RESET_USB_HOST BIT(5)
|
|
+#define QCA955X_RESET_USB_PHY BIT(4)
|
|
+#define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
|
|
+#define QCA955X_RESET_LUT BIT(2)
|
|
+#define QCA955X_RESET_MBOX BIT(1)
|
|
+#define QCA955X_RESET_I2S BIT(0)
|
|
|
|
+#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
|
|
+#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
|
|
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
|
|
|
|
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
|
|
@@ -530,6 +627,12 @@
|
|
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
|
|
#define AR71XX_GPIO_REG_FUNC 0x28
|
|
|
|
+#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
|
|
+#define AR934X_GPIO_REG_OUT_FUNC1 0x30
|
|
+#define AR934X_GPIO_REG_OUT_FUNC2 0x34
|
|
+#define AR934X_GPIO_REG_OUT_FUNC3 0x38
|
|
+#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
|
|
+#define AR934X_GPIO_REG_OUT_FUNC5 0x40
|
|
#define AR934X_GPIO_REG_FUNC 0x6c
|
|
|
|
#define AR71XX_GPIO_COUNT 16
|
|
@@ -561,4 +664,148 @@
|
|
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
|
|
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
|
|
|
|
+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
|
|
+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
|
|
+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
|
|
+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
|
|
+#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
|
|
+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
|
|
+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
|
|
+
|
|
+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
|
|
+#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
|
|
+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
|
|
+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
|
|
+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
|
|
+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
|
|
+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
|
|
+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
|
|
+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
|
|
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
|
|
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
|
|
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
|
|
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
|
|
+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
|
|
+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
|
|
+#define AR724X_GPIO_FUNC_UART_EN BIT(1)
|
|
+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
|
|
+
|
|
+#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
|
|
+#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
|
|
+#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
|
|
+#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
|
|
+#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
|
|
+#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
|
|
+#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
|
|
+#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
|
|
+#define AR913X_GPIO_FUNC_UART_EN BIT(8)
|
|
+#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
|
|
+
|
|
+#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
|
|
+#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
|
|
+#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
|
|
+#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
|
|
+#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
|
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
|
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
|
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
|
|
+#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
|
|
+#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
|
|
+#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
|
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
|
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
|
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
|
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
|
|
+#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
|
|
+#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
|
|
+#define AR933X_GPIO_FUNC_UART_EN BIT(1)
|
|
+#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
|
|
+
|
|
+#define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
|
|
+#define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
|
|
+#define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
|
|
+#define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
|
|
+#define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
|
|
+#define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
|
|
+#define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
|
|
+#define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
|
|
+#define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
|
|
+
|
|
+#define AR934X_GPIO_OUT_GPIO 0
|
|
+#define AR934X_GPIO_OUT_LED_LINK0 41
|
|
+#define AR934X_GPIO_OUT_LED_LINK1 42
|
|
+#define AR934X_GPIO_OUT_LED_LINK2 43
|
|
+#define AR934X_GPIO_OUT_LED_LINK3 44
|
|
+#define AR934X_GPIO_OUT_LED_LINK4 45
|
|
+#define AR934X_GPIO_OUT_EXT_LNA0 46
|
|
+#define AR934X_GPIO_OUT_EXT_LNA1 47
|
|
+
|
|
+/*
|
|
+ * MII_CTRL block
|
|
+ */
|
|
+#define AR71XX_MII_REG_MII0_CTRL 0x00
|
|
+#define AR71XX_MII_REG_MII1_CTRL 0x04
|
|
+
|
|
+#define AR71XX_MII_CTRL_IF_MASK 3
|
|
+#define AR71XX_MII_CTRL_SPEED_SHIFT 4
|
|
+#define AR71XX_MII_CTRL_SPEED_MASK 3
|
|
+#define AR71XX_MII_CTRL_SPEED_10 0
|
|
+#define AR71XX_MII_CTRL_SPEED_100 1
|
|
+#define AR71XX_MII_CTRL_SPEED_1000 2
|
|
+
|
|
+#define AR71XX_MII0_CTRL_IF_GMII 0
|
|
+#define AR71XX_MII0_CTRL_IF_MII 1
|
|
+#define AR71XX_MII0_CTRL_IF_RGMII 2
|
|
+#define AR71XX_MII0_CTRL_IF_RMII 3
|
|
+
|
|
+#define AR71XX_MII1_CTRL_IF_RGMII 0
|
|
+#define AR71XX_MII1_CTRL_IF_RMII 1
|
|
+
|
|
+/*
|
|
+ * AR933X GMAC interface
|
|
+ */
|
|
+#define AR933X_GMAC_REG_ETH_CFG 0x00
|
|
+
|
|
+#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
|
|
+#define AR933X_ETH_CFG_MII_GE0 BIT(1)
|
|
+#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
|
|
+#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
|
|
+#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
|
|
+#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
|
|
+#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
|
|
+#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
|
|
+#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
|
|
+#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
|
|
+#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
|
|
+
|
|
+/*
|
|
+ * AR934X GMAC Interface
|
|
+ */
|
|
+#define AR934X_GMAC_REG_ETH_CFG 0x00
|
|
+
|
|
+#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
|
|
+#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
|
|
+#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
|
|
+#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
|
|
+#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
|
|
+#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
|
|
+#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
|
|
+#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
|
|
+#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
|
|
+#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
|
|
+#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
|
|
+#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
|
|
+#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
|
|
+#define AR934X_ETH_CFG_RXD_DELAY BIT(14)
|
|
+#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
|
|
+
|
|
+/*
|
|
+ * QCA955X GMAC Interface
|
|
+ */
|
|
+
|
|
+#define QCA955X_GMAC_REG_ETH_CFG 0x00
|
|
+
|
|
+#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
|
|
+#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
|
|
+
|
|
#endif /* __ASM_MACH_AR71XX_REGS_H */
|