mirror of https://github.com/hak5/openwrt.git
272 lines
7.8 KiB
Diff
272 lines
7.8 KiB
Diff
From 77e664940f6daa86965d16a2047188519341a31a Mon Sep 17 00:00:00 2001
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From: YH Huang <yh.huang@mediatek.com>
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Date: Mon, 11 May 2015 17:26:22 +0800
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Subject: [PATCH 28/76] pwm: add Mediatek display PWM driver support
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Add display PWM driver support to modify backlight for MT8173/MT6595.
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Signed-off-by: YH Huang <yh.huang@mediatek.com>
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---
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drivers/pwm/Kconfig | 9 ++
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drivers/pwm/Makefile | 1 +
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drivers/pwm/pwm-disp-mediatek.c | 225 +++++++++++++++++++++++++++++++++++++++
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3 files changed, 235 insertions(+)
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create mode 100644 drivers/pwm/pwm-disp-mediatek.c
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--- a/drivers/pwm/Kconfig
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+++ b/drivers/pwm/Kconfig
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@@ -111,6 +111,15 @@ config PWM_CLPS711X
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To compile this driver as a module, choose M here: the module
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will be called pwm-clps711x.
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+config PWM_DISP_MEDIATEK
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+ tristate "MEDIATEK display PWM driver"
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+ depends on OF
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+ help
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+ Generic PWM framework driver for mediatek disp-pwm device.
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+
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+ To compile this driver as a module, choose M here: the module
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+ will be called pwm-disp-mediatek.
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+
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config PWM_EP93XX
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tristate "Cirrus Logic EP93xx PWM support"
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depends on ARCH_EP93XX
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--- a/drivers/pwm/Makefile
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+++ b/drivers/pwm/Makefile
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@@ -8,6 +8,7 @@ obj-$(CONFIG_PWM_BCM_KONA) += pwm-bcm-ko
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obj-$(CONFIG_PWM_BCM2835) += pwm-bcm2835.o
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obj-$(CONFIG_PWM_BFIN) += pwm-bfin.o
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obj-$(CONFIG_PWM_CLPS711X) += pwm-clps711x.o
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+obj-$(CONFIG_PWM_DISP_MEDIATEK) += pwm-disp-mediatek.o
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obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o
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obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o
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obj-$(CONFIG_PWM_IMG) += pwm-img.o
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--- /dev/null
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+++ b/drivers/pwm/pwm-disp-mediatek.c
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@@ -0,0 +1,225 @@
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+/*
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+ * Mediatek display pulse-width-modulation controller driver.
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+ * Copyright (c) 2015 MediaTek Inc.
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+ * Author: YH Huang <yh.huang@mediatek.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/pwm.h>
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+#include <linux/platform_device.h>
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+#include <linux/slab.h>
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+
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+#define DISP_PWM_EN_OFF (0x0)
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+#define PWM_ENABLE_SHIFT (0x0)
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+#define PWM_ENABLE_MASK (0x1 << PWM_ENABLE_SHIFT)
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+
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+#define DISP_PWM_COMMIT_OFF (0x08)
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+#define PWM_COMMIT_SHIFT (0x0)
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+#define PWM_COMMIT_MASK (0x1 << PWM_COMMIT_SHIFT)
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+
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+#define DISP_PWM_CON_0_OFF (0x10)
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+#define PWM_CLKDIV_SHIFT (0x10)
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+#define PWM_CLKDIV_MASK (0x3ff << PWM_CLKDIV_SHIFT)
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+#define PWM_CLKDIV_MAX (0x000003ff)
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+
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+#define DISP_PWM_CON_1_OFF (0x14)
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+#define PWM_PERIOD_SHIFT (0x0)
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+#define PWM_PERIOD_MASK (0xfff << PWM_PERIOD_SHIFT)
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+#define PWM_PERIOD_MAX (0x00000fff)
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+/* Shift log2(PWM_PERIOD_MAX + 1) as divisor */
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+#define PWM_PERIOD_BIT_SHIFT 12
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+
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+#define PWM_HIGH_WIDTH_SHIFT (0x10)
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+#define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT)
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+
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+#define NUM_PWM 1
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+
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+struct mtk_disp_pwm_chip {
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+ struct pwm_chip chip;
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+ struct device *dev;
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+ struct clk *clk_main;
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+ struct clk *clk_mm;
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+ void __iomem *mmio_base;
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+};
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+
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+static void mtk_disp_pwm_setting(void __iomem *address, u32 value, u32 mask)
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+{
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+ u32 val;
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+
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+ val = readl(address);
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+ val &= ~mask;
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+ val |= value;
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+ writel(val, address);
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+}
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+
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+static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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+ int duty_ns, int period_ns)
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+{
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+ struct mtk_disp_pwm_chip *mpc;
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+ u64 div, rate;
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+ u32 clk_div, period, high_width, rem;
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+
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+ /*
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+ * Find period, high_width and clk_div to suit duty_ns and period_ns.
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+ * Calculate proper div value to keep period value in the bound.
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+ *
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+ * period_ns = 10^9 * (clk_div + 1) * (period +1) / PWM_CLK_RATE
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+ * duty_ns = 10^9 * (clk_div + 1) * (high_width + 1) / PWM_CLK_RATE
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+ *
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+ * period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
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+ * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1)) - 1
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+ */
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+ mpc = container_of(chip, struct mtk_disp_pwm_chip, chip);
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+ rate = clk_get_rate(mpc->clk_main);
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+ clk_div = div_u64_rem(rate * period_ns, NSEC_PER_SEC, &rem) >>
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+ PWM_PERIOD_BIT_SHIFT;
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+ if (clk_div > PWM_CLKDIV_MAX)
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+ return -EINVAL;
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+
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+ div = clk_div + 1;
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+ period = div64_u64(rate * period_ns, NSEC_PER_SEC * div);
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+ if (period > 0)
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+ period--;
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+ high_width = div64_u64(rate * duty_ns, NSEC_PER_SEC * div);
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+ if (high_width > 0)
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+ high_width--;
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+
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+ mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_CON_0_OFF,
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+ clk_div << PWM_CLKDIV_SHIFT, PWM_CLKDIV_MASK);
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+ mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_CON_1_OFF,
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+ (period << PWM_PERIOD_SHIFT) |
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+ (high_width << PWM_HIGH_WIDTH_SHIFT),
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+ PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK);
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+
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+ mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_COMMIT_OFF,
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+ 1 << PWM_COMMIT_SHIFT, PWM_COMMIT_MASK);
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+ mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_COMMIT_OFF,
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+ 0 << PWM_COMMIT_SHIFT, PWM_COMMIT_MASK);
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+
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+ return 0;
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+}
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+
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+static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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+{
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+ struct mtk_disp_pwm_chip *mpc;
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+
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+ mpc = container_of(chip, struct mtk_disp_pwm_chip, chip);
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+ mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_EN_OFF,
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+ 1 << PWM_ENABLE_SHIFT, PWM_ENABLE_MASK);
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+
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+ return 0;
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+}
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+
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+static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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+{
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+ struct mtk_disp_pwm_chip *mpc;
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+
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+ mpc = container_of(chip, struct mtk_disp_pwm_chip, chip);
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+ mtk_disp_pwm_setting(mpc->mmio_base + DISP_PWM_EN_OFF,
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+ 0 << PWM_ENABLE_SHIFT, PWM_ENABLE_MASK);
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+}
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+
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+static const struct pwm_ops mtk_disp_pwm_ops = {
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+ .config = mtk_disp_pwm_config,
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+ .enable = mtk_disp_pwm_enable,
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+ .disable = mtk_disp_pwm_disable,
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+ .owner = THIS_MODULE,
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+};
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+
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+static int mtk_disp_pwm_probe(struct platform_device *pdev)
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+{
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+ struct mtk_disp_pwm_chip *pwm;
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+ struct resource *r;
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+ int ret;
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+
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+ pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
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+ if (!pwm)
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+ return -ENOMEM;
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+
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+ pwm->dev = &pdev->dev;
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+
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+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ pwm->mmio_base = devm_ioremap_resource(&pdev->dev, r);
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+ if (IS_ERR(pwm->mmio_base))
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+ return PTR_ERR(pwm->mmio_base);
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+
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+ pwm->clk_main = devm_clk_get(&pdev->dev, "main");
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+ if (IS_ERR(pwm->clk_main))
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+ return PTR_ERR(pwm->clk_main);
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+ pwm->clk_mm = devm_clk_get(&pdev->dev, "mm");
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+ if (IS_ERR(pwm->clk_mm))
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+ return PTR_ERR(pwm->clk_mm);
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+
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+ ret = clk_prepare_enable(pwm->clk_main);
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+ if (ret < 0)
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+ return ret;
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+ ret = clk_prepare_enable(pwm->clk_mm);
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+ if (ret < 0) {
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+ clk_disable_unprepare(pwm->clk_main);
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+ return ret;
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+ }
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+
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+ platform_set_drvdata(pdev, pwm);
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+
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+ pwm->chip.dev = &pdev->dev;
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+ pwm->chip.ops = &mtk_disp_pwm_ops;
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+ pwm->chip.base = -1;
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+ pwm->chip.npwm = NUM_PWM;
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+
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+ ret = pwmchip_add(&pwm->chip);
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+ if (ret < 0) {
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+ dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+static int mtk_disp_pwm_remove(struct platform_device *pdev)
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+{
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+ struct mtk_disp_pwm_chip *pc = platform_get_drvdata(pdev);
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+
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+ if (WARN_ON(!pc))
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+ return -ENODEV;
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+
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+ clk_disable_unprepare(pc->clk_main);
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+ clk_disable_unprepare(pc->clk_mm);
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+
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+ return pwmchip_remove(&pc->chip);
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+}
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+
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+static const struct of_device_id mtk_disp_pwm_of_match[] = {
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+ { .compatible = "mediatek,mt6595-disp-pwm" },
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+ { }
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+};
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+
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+MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
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+
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+static struct platform_driver mtk_disp_pwm_driver = {
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+ .driver = {
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+ .name = "mediatek-disp-pwm",
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+ .owner = THIS_MODULE,
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+ .of_match_table = mtk_disp_pwm_of_match,
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+ },
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+ .probe = mtk_disp_pwm_probe,
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+ .remove = mtk_disp_pwm_remove,
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+};
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+
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+module_platform_driver(mtk_disp_pwm_driver);
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+
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+MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
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+MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
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+MODULE_LICENSE("GPL v2");
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