mirror of https://github.com/hak5/openwrt.git
127 lines
3.3 KiB
C
127 lines
3.3 KiB
C
/*
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* Ralink RT305x SoC specific setup
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*
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* Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/gpio.h>
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#include <asm/mach-ralink/common.h>
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#include <asm/mach-ralink/rt305x.h>
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#include <asm/mach-ralink/rt305x_regs.h>
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unsigned long rt305x_cpu_freq;
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EXPORT_SYMBOL_GPL(rt305x_cpu_freq);
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unsigned long rt305x_sys_freq;
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EXPORT_SYMBOL_GPL(rt305x_sys_freq);
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void __iomem * rt305x_sysc_base;
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void __iomem * rt305x_memc_base;
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void __init rt305x_detect_sys_type(void)
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{
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u32 n0;
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u32 n1;
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u32 id;
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n0 = rt305x_sysc_rr(SYSC_REG_CHIP_NAME0);
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n1 = rt305x_sysc_rr(SYSC_REG_CHIP_NAME1);
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id = rt305x_sysc_rr(SYSC_REG_CHIP_ID);
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snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
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"Ralink %c%c%c%c%c%c%c%c id:%u rev:%u",
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(char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff),
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(char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff),
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(char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff),
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(char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff),
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(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
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(id & CHIP_ID_REV_MASK));
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}
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void __init rt305x_detect_sys_freq(void)
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{
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u32 t;
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t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
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t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
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switch (t) {
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case SYSTEM_CONFIG_CPUCLK_320:
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rt305x_cpu_freq = 320000000;
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break;
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case SYSTEM_CONFIG_CPUCLK_384:
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rt305x_cpu_freq = 384000000;
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break;
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}
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rt305x_sys_freq = rt305x_cpu_freq / 3;
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}
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static void rt305x_gpio_reserve(int first, int last)
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{
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for (; first <= last; first++)
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gpio_request(first, "reserved");
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}
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void __init rt305x_gpio_init(u32 mode)
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{
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u32 t;
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rt305x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
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ramips_gpio_init();
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if ((mode & RT305X_GPIO_MODE_I2C) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_I2C_SD, RT305X_GPIO_I2C_SCLK);
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if ((mode & RT305X_GPIO_MODE_SPI) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_SPI_EN, RT305X_GPIO_SPI_CLK);
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t = mode >> RT305X_GPIO_MODE_UART0_SHIFT;
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t &= RT305X_GPIO_MODE_UART0_MASK;
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switch (t) {
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case RT305X_GPIO_MODE_UARTF:
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case RT305X_GPIO_MODE_PCM_UARTF:
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case RT305X_GPIO_MODE_PCM_I2S:
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case RT305X_GPIO_MODE_I2S_UARTF:
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rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_14);
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break;
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case RT305X_GPIO_MODE_PCM_GPIO:
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rt305x_gpio_reserve(RT305X_GPIO_10, RT305X_GPIO_14);
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break;
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case RT305X_GPIO_MODE_GPIO_UARTF:
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case RT305X_GPIO_MODE_GPIO_I2S:
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rt305x_gpio_reserve(RT305X_GPIO_7, RT305X_GPIO_10);
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break;
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}
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if ((mode & RT305X_GPIO_MODE_UART1) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_UART1_TXD,
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RT305X_GPIO_UART1_RXD);
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if ((mode & RT305X_GPIO_MODE_JTAG) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_JTAG_TDO, RT305X_GPIO_JTAG_TDI);
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if ((mode & RT305X_GPIO_MODE_MDIO) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_MDIO_MDC,
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RT305X_GPIO_MDIO_MDIO);
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if ((mode & RT305X_GPIO_MODE_SDRAM) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_SDRAM_MD16,
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RT305X_GPIO_SDRAM_MD31);
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if ((mode & RT305X_GPIO_MODE_RGMII) == 0)
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rt305x_gpio_reserve(RT305X_GPIO_GE0_TXD0,
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RT305X_GPIO_GE0_RXCLK);
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}
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