mirror of https://github.com/hak5/openwrt.git
477 lines
12 KiB
Diff
477 lines
12 KiB
Diff
From ae6e941c5d58262c0a09c355ae384b7109977053 Mon Sep 17 00:00:00 2001
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From: Lars-Peter Clausen <lars@metafoo.de>
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Date: Mon, 12 Jul 2010 03:48:08 +0200
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Subject: [PATCH] mfd: Add JZ4740 ADC driver
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This patch adds a MFD driver for the JZ4740 ADC unit. The driver is used to
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demultiplex IRQs and synchronize access to shared registers between the
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battery, hwmon and (future) touchscreen driver.
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Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
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---
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drivers/mfd/Kconfig | 8 +
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drivers/mfd/Makefile | 1 +
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drivers/mfd/jz4740-adc.c | 394 ++++++++++++++++++++++++++++++++++++++++++++
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include/linux/jz4740-adc.h | 32 ++++
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4 files changed, 435 insertions(+), 0 deletions(-)
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create mode 100644 drivers/mfd/jz4740-adc.c
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create mode 100644 include/linux/jz4740-adc.h
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--- a/drivers/mfd/Kconfig
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+++ b/drivers/mfd/Kconfig
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@@ -482,6 +482,14 @@ config MFD_JANZ_CMODIO
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host many different types of MODULbus daughterboards, including
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CAN and GPIO controllers.
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+config MFD_JZ4740_ADC
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+ tristate "Support for the JZ4740 SoC ADC core"
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+ select MFD_CORE
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+ depends on MACH_JZ4740
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+ help
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+ Say yes here if you want support for the ADC unit in the JZ4740 SoC.
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+ This driver is necessary for jz4740-battery and jz4740-hwmon driver.
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+
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endif # MFD_SUPPORT
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menu "Multimedia Capabilities Port drivers"
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--- a/drivers/mfd/Makefile
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+++ b/drivers/mfd/Makefile
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@@ -71,3 +71,4 @@ obj-$(CONFIG_PMIC_ADP5520) += adp5520.o
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obj-$(CONFIG_LPC_SCH) += lpc_sch.o
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obj-$(CONFIG_MFD_RDC321X) += rdc321x-southbridge.o
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obj-$(CONFIG_MFD_JANZ_CMODIO) += janz-cmodio.o
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+obj-$(CONFIG_MFD_JZ4740_ADC) += jz4740-adc.o
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--- /dev/null
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+++ b/drivers/mfd/jz4740-adc.c
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@@ -0,0 +1,394 @@
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+/*
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+ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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+ * JZ4740 SoC ADC driver
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ * This driver synchronizes access to the JZ4740 ADC core between the
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+ * JZ4740 battery and hwmon drivers.
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+ */
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+
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+#include <linux/err.h>
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+#include <linux/irq.h>
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+#include <linux/interrupt.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/slab.h>
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+#include <linux/spinlock.h>
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+
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+#include <linux/clk.h>
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+#include <linux/mfd/core.h>
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+
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+#include <linux/jz4740-adc.h>
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+
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+
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+#define JZ_REG_ADC_ENABLE 0x00
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+#define JZ_REG_ADC_CFG 0x04
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+#define JZ_REG_ADC_CTRL 0x08
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+#define JZ_REG_ADC_STATUS 0x0c
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+
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+#define JZ_REG_ADC_TOUCHSCREEN_BASE 0x10
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+#define JZ_REG_ADC_BATTERY_BASE 0x1c
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+#define JZ_REG_ADC_HWMON_BASE 0x20
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+
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+#define JZ_ADC_ENABLE_TOUCH BIT(2)
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+#define JZ_ADC_ENABLE_BATTERY BIT(1)
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+#define JZ_ADC_ENABLE_ADCIN BIT(0)
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+
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+enum {
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+ JZ_ADC_IRQ_ADCIN = 0,
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+ JZ_ADC_IRQ_BATTERY,
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+ JZ_ADC_IRQ_TOUCH,
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+ JZ_ADC_IRQ_PENUP,
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+ JZ_ADC_IRQ_PENDOWN,
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+};
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+
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+struct jz4740_adc {
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+ struct resource *mem;
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+ void __iomem *base;
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+
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+ int irq;
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+ int irq_base;
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+
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+ struct clk *clk;
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+ atomic_t clk_ref;
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+
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+ spinlock_t lock;
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+};
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+
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+static inline void jz4740_adc_irq_set_masked(struct jz4740_adc *adc, int irq,
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+ bool masked)
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+{
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+ unsigned long flags;
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+ uint8_t val;
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+
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+ irq -= adc->irq_base;
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+
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+ spin_lock_irqsave(&adc->lock, flags);
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+
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+ val = readb(adc->base + JZ_REG_ADC_CTRL);
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+ if (masked)
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+ val |= BIT(irq);
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+ else
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+ val &= ~BIT(irq);
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+ writeb(val, adc->base + JZ_REG_ADC_CTRL);
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+
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+ spin_unlock_irqrestore(&adc->lock, flags);
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+}
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+
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+static void jz4740_adc_irq_mask(unsigned int irq)
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+{
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+ struct jz4740_adc *adc = get_irq_chip_data(irq);
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+ jz4740_adc_irq_set_masked(adc, irq, true);
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+}
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+
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+static void jz4740_adc_irq_unmask(unsigned int irq)
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+{
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+ struct jz4740_adc *adc = get_irq_chip_data(irq);
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+ jz4740_adc_irq_set_masked(adc, irq, false);
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+}
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+
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+static void jz4740_adc_irq_ack(unsigned int irq)
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+{
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+ struct jz4740_adc *adc = get_irq_chip_data(irq);
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+
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+ irq -= adc->irq_base;
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+ writeb(BIT(irq), adc->base + JZ_REG_ADC_STATUS);
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+}
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+
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+static struct irq_chip jz4740_adc_irq_chip = {
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+ .name = "jz4740-adc",
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+ .mask = jz4740_adc_irq_mask,
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+ .unmask = jz4740_adc_irq_unmask,
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+ .ack = jz4740_adc_irq_ack,
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+};
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+
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+static void jz4740_adc_irq_demux(unsigned int irq, struct irq_desc *desc)
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+{
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+ struct jz4740_adc *adc = get_irq_desc_data(desc);
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+ uint8_t status;
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+ unsigned int i;
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+
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+ status = readb(adc->base + JZ_REG_ADC_STATUS);
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+
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+ for (i = 0; i < 5; ++i) {
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+ if (status & BIT(i))
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+ generic_handle_irq(adc->irq_base + i);
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+ }
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+}
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+
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+
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+/* Refcounting for the ADC clock is done in here instead of in the clock
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+ * framework, because it is the only clock which is shared between multiple
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+ * devices and thus is the only clock which needs refcounting */
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+static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc)
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+{
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+ if (atomic_inc_return(&adc->clk_ref) == 1)
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+ clk_enable(adc->clk);
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+}
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+
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+static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc)
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+{
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+ if (atomic_dec_return(&adc->clk_ref) == 0)
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+ clk_disable(adc->clk);
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+}
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+
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+static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine,
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+ bool enabled)
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+{
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+ unsigned long flags;
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+ uint8_t val;
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+
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+ spin_lock_irqsave(&adc->lock, flags);
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+
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+ val = readb(adc->base + JZ_REG_ADC_ENABLE);
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+ if (enabled)
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+ val |= BIT(engine);
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+ else
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+ val &= BIT(engine);
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+ writeb(val, adc->base + JZ_REG_ADC_ENABLE);
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+
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+ spin_unlock_irqrestore(&adc->lock, flags);
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+}
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+
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+static int jz4740_adc_cell_enable(struct platform_device *pdev)
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+{
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+ struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
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+
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+ jz4740_adc_clk_enable(adc);
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+ jz4740_adc_set_enabled(adc, pdev->id, true);
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+
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+ return 0;
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+}
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+
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+static int jz4740_adc_cell_disable(struct platform_device *pdev)
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+{
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+ struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
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+
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+ jz4740_adc_set_enabled(adc, pdev->id, false);
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+ jz4740_adc_clk_disable(adc);
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+
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+ return 0;
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+}
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+
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+int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val)
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+{
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+ struct jz4740_adc *adc = dev_get_drvdata(dev);
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+ unsigned long flags;
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+ uint32_t cfg;
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+
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+ if (!adc)
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+ return -ENODEV;
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+
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+ spin_lock_irqsave(&adc->lock, flags);
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+
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+ cfg = readl(adc->base + JZ_REG_ADC_CFG);
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+
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+ cfg &= ~mask;
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+ cfg |= val;
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+
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+ writel(cfg, adc->base + JZ_REG_ADC_CFG);
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+
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+ spin_unlock_irqrestore(&adc->lock, flags);
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(jz4740_adc_set_config);
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+
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+static struct resource jz4740_hwmon_resources[] = {
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+ {
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+ .start = JZ_ADC_IRQ_ADCIN,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+ {
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+ .start = JZ_REG_ADC_HWMON_BASE,
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+ .end = JZ_REG_ADC_HWMON_BASE + 3,
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+ .flags = IORESOURCE_MEM,
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+ },
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+};
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+
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+static struct resource jz4740_battery_resources[] = {
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+ {
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+ .start = JZ_ADC_IRQ_BATTERY,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+ {
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+ .start = JZ_REG_ADC_BATTERY_BASE,
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+ .end = JZ_REG_ADC_BATTERY_BASE + 3,
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+ .flags = IORESOURCE_MEM,
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+ },
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+};
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+
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+const struct mfd_cell jz4740_adc_cells[] = {
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+ {
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+ .id = 0,
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+ .name = "jz4740-hwmon",
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+ .num_resources = ARRAY_SIZE(jz4740_hwmon_resources),
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+ .resources = jz4740_hwmon_resources,
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+ .platform_data = (void *)&jz4740_adc_cells[0],
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+ .data_size = sizeof(struct mfd_cell),
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+
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+ .enable = jz4740_adc_cell_enable,
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+ .disable = jz4740_adc_cell_disable,
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+ },
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+ {
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+ .id = 1,
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+ .name = "jz4740-battery",
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+ .num_resources = ARRAY_SIZE(jz4740_battery_resources),
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+ .resources = jz4740_battery_resources,
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+ .platform_data = (void *)&jz4740_adc_cells[1],
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+ .data_size = sizeof(struct mfd_cell),
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+
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+ .enable = jz4740_adc_cell_enable,
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+ .disable = jz4740_adc_cell_disable,
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+ },
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+};
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+
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+static int __devinit jz4740_adc_probe(struct platform_device *pdev)
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+{
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+ int ret;
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+ struct jz4740_adc *adc;
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+ struct resource *mem_base;
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+ int irq;
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+
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+ adc = kmalloc(sizeof(*adc), GFP_KERNEL);
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+ if (!adc) {
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+ dev_err(&pdev->dev, "Failed to allocate driver structure\n");
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+ return -ENOMEM;
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+ }
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+
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+ adc->irq = platform_get_irq(pdev, 0);
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+ if (adc->irq < 0) {
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+ ret = adc->irq;
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+ dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
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+ goto err_free;
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+ }
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+
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+ adc->irq_base = platform_get_irq(pdev, 1);
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+ if (adc->irq_base < 0) {
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+ ret = adc->irq_base;
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+ dev_err(&pdev->dev, "Failed to get irq base: %d\n", ret);
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+ goto err_free;
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+ }
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+
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+ mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ if (!mem_base) {
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+ ret = -ENOENT;
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+ dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
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+ goto err_free;
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+ }
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+
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+ /* Only request the shared registers for the MFD driver */
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+ adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS,
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+ pdev->name);
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+ if (!adc->mem) {
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+ ret = -EBUSY;
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+ dev_err(&pdev->dev, "Failed to request mmio memory region\n");
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+ goto err_free;
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+ }
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+
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+ adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
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+ if (!adc->base) {
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+ ret = -EBUSY;
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+ dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
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+ goto err_release_mem_region;
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+ }
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+
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+ adc->clk = clk_get(&pdev->dev, "adc");
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+ if (IS_ERR(adc->clk)) {
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+ ret = PTR_ERR(adc->clk);
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+ dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
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+ goto err_iounmap;
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+ }
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+
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+ spin_lock_init(&adc->lock);
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+ atomic_set(&adc->clk_ref, 0);
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+
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+ platform_set_drvdata(pdev, adc);
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+
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+ for (irq = adc->irq_base; irq < adc->irq_base + 5; ++irq) {
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+ set_irq_chip_data(irq, adc);
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+ set_irq_chip_and_handler(irq, &jz4740_adc_irq_chip,
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+ handle_level_irq);
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+ }
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+
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+ set_irq_data(adc->irq, adc);
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+ set_irq_chained_handler(adc->irq, jz4740_adc_irq_demux);
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+
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+ writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
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+ writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
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+
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+ ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells,
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+ ARRAY_SIZE(jz4740_adc_cells), mem_base, adc->irq_base);
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+ if (ret < 0)
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+ goto err_clk_put;
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+
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+ return 0;
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+
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+err_clk_put:
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+ clk_put(adc->clk);
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+err_iounmap:
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+ platform_set_drvdata(pdev, NULL);
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+ iounmap(adc->base);
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+err_release_mem_region:
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+ release_mem_region(adc->mem->start, resource_size(adc->mem));
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+err_free:
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+ kfree(adc);
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+
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+ return ret;
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+}
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+
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+static int __devexit jz4740_adc_remove(struct platform_device *pdev)
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+{
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+ struct jz4740_adc *adc = platform_get_drvdata(pdev);
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+
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+ mfd_remove_devices(&pdev->dev);
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+
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+ set_irq_data(adc->irq, NULL);
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+ set_irq_chained_handler(adc->irq, NULL);
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+
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+ iounmap(adc->base);
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+ release_mem_region(adc->mem->start, resource_size(adc->mem));
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+
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+ clk_put(adc->clk);
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+
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+ platform_set_drvdata(pdev, NULL);
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+
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+ kfree(adc);
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+
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+ return 0;
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+}
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+
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+struct platform_driver jz4740_adc_driver = {
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+ .probe = jz4740_adc_probe,
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+ .remove = __devexit_p(jz4740_adc_remove),
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+ .driver = {
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+ .name = "jz4740-adc",
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+ .owner = THIS_MODULE,
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+ },
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+};
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+
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+static int __init jz4740_adc_init(void)
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+{
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+ return platform_driver_register(&jz4740_adc_driver);
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+}
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+module_init(jz4740_adc_init);
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+
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+static void __exit jz4740_adc_exit(void)
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+{
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+ platform_driver_unregister(&jz4740_adc_driver);
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+}
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+module_exit(jz4740_adc_exit);
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+
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+MODULE_DESCRIPTION("JZ4740 SoC ADC driver");
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+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
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+MODULE_LICENSE("GPL");
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+MODULE_ALIAS("platform:jz4740-adc");
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--- /dev/null
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+++ b/include/linux/jz4740-adc.h
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@@ -0,0 +1,32 @@
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+
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+#ifndef __LINUX_JZ4740_ADC
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+#define __LINUX_JZ4740_ADC
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+
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+#include <linux/device.h>
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+
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+/*
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+ * jz4740_adc_set_config - Configure a JZ4740 adc device
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+ * @dev: Pointer to a jz4740-adc device
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+ * @mask: Mask for the config value to be set
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+ * @val: Value to be set
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+ *
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+ * This function can be used by the JZ4740 ADC mfd cells to configure their
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+ * options in the shared config register.
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+*/
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+int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val);
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+
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+#define JZ_ADC_CONFIG_SPZZ BIT(31)
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+#define JZ_ADC_CONFIG_EX_IN BIT(30)
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+#define JZ_ADC_CONFIG_DNUM_MASK (0x7 << 16)
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+#define JZ_ADC_CONFIG_DMA_ENABLE BIT(15)
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+#define JZ_ADC_CONFIG_XYZ_MASK (0x2 << 13)
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+#define JZ_ADC_CONFIG_SAMPLE_NUM_MASK (0x7 << 10)
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+#define JZ_ADC_CONFIG_CLKDIV_MASK (0xf << 5)
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+#define JZ_ADC_CONFIG_BAT_MB BIT(4)
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+
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+#define JZ_ADC_CONFIG_DNUM(dnum) ((dnum) << 16)
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+#define JZ_ADC_CONFIG_XYZ_OFFSET(dnum) ((xyz) << 13)
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+#define JZ_ADC_CONFIG_SAMPLE_NUM(x) ((x) << 10)
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+#define JZ_ADC_CONFIG_CLKDIV(div) ((div) << 5)
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+
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+#endif
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