mirror of https://github.com/hak5/openwrt.git
456 lines
16 KiB
Diff
456 lines
16 KiB
Diff
From 03839951515b0ea2b21d649b1fe7b63f9817d0c8 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <dgolle@allnet.de>
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Date: Sun, 9 Sep 2012 14:24:39 +0300
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Subject: [PATCH] rt2x00: add MediaTek/RaLink Rt3352 WiSoC
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Support for the RT3352 WiSoC was developed for and tested with the ALL5002
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devboard running OpenWrt. For now, this supports only devices with internal
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TXALC. Corrections were made according to the remarks of Stanislaw Gruszka and
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Gertjan van Wingerde, thank you guys for reviewing!
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Signed-off-by: Daniel Golle <dgolle@allnet.de>
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Signed-off-by: John W. Linville <linville@tuxdriver.com>
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---
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drivers/net/wireless/rt2x00/rt2800.h | 5 +
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drivers/net/wireless/rt2x00/rt2800lib.c | 211 +++++++++++++++++++++++++++++++-
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drivers/net/wireless/rt2x00/rt2x00.h | 1 +
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3 files changed, 212 insertions(+), 5 deletions(-)
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--- a/drivers/net/wireless/rt2x00/rt2800.h
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+++ b/drivers/net/wireless/rt2x00/rt2800.h
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@@ -1943,6 +1943,11 @@ struct mac_iveiv_entry {
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#define BBP47_TSSI_ADC6 FIELD8(0x80)
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/*
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+ * BBP 49
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+ */
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+#define BBP49_UPDATE_FLAG FIELD8(0x01)
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+
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+/*
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* BBP 109
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*/
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#define BBP109_TX0_POWER FIELD8(0x0f)
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--- a/drivers/net/wireless/rt2x00/rt2800lib.c
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+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
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@@ -1615,6 +1615,7 @@ void rt2800_config_ant(struct rt2x00_dev
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case 1:
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if (rt2x00_rt(rt2x00dev, RT3070) ||
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rt2x00_rt(rt2x00dev, RT3090) ||
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+ rt2x00_rt(rt2x00dev, RT3352) ||
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rt2x00_rt(rt2x00dev, RT3390)) {
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rt2x00_eeprom_read(rt2x00dev,
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EEPROM_NIC_CONF1, &eeprom);
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@@ -2053,6 +2054,60 @@ static void rt2800_config_channel_rf3290
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}
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}
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+static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
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+ struct ieee80211_conf *conf,
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+ struct rf_channel *rf,
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+ struct channel_info *info)
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+{
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+ u8 rfcsr;
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+
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+ rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
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+ rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
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+
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+ rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
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+ rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
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+ rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
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+
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+ if (info->default_power1 > POWER_BOUND)
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+ rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
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+ else
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+ rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
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+
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+ if (info->default_power2 > POWER_BOUND)
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+ rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
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+ else
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+ rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
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+
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+ rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
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+ if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
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+ rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
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+ else
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+ rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
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+
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+ rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
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+
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+ rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
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+ rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
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+ rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
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+
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+ if ( rt2x00dev->default_ant.tx_chain_num == 2 )
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+ rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
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+ else
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+ rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
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+
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+ if ( rt2x00dev->default_ant.rx_chain_num == 2 )
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+ rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
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+ else
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+ rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
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+
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+ rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
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+ rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
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+
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+ rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
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+
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+ rt2800_rfcsr_write(rt2x00dev, 31, 80);
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+}
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+
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static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
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struct ieee80211_conf *conf,
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struct rf_channel *rf,
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@@ -2182,6 +2237,9 @@ static void rt2800_config_channel(struct
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case RF3290:
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rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
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break;
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+ case RF3322:
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+ rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
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+ break;
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case RF5360:
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case RF5370:
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case RF5372:
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@@ -2194,6 +2252,7 @@ static void rt2800_config_channel(struct
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}
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if (rt2x00_rf(rt2x00dev, RF3290) ||
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+ rt2x00_rf(rt2x00dev, RF3322) ||
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rt2x00_rf(rt2x00dev, RF5360) ||
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rt2x00_rf(rt2x00dev, RF5370) ||
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rt2x00_rf(rt2x00dev, RF5372) ||
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@@ -2212,10 +2271,17 @@ static void rt2800_config_channel(struct
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/*
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* Change BBP settings
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*/
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- rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
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- rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
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- rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
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- rt2800_bbp_write(rt2x00dev, 86, 0);
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+ if (rt2x00_rt(rt2x00dev, RT3352)) {
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+ rt2800_bbp_write(rt2x00dev, 27, 0x0);
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+ rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
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+ rt2800_bbp_write(rt2x00dev, 27, 0x20);
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+ rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
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+ } else {
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+ rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
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+ rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
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+ rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
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+ rt2800_bbp_write(rt2x00dev, 86, 0);
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+ }
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if (rf->channel <= 14) {
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if (!rt2x00_rt(rt2x00dev, RT5390) &&
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@@ -2310,6 +2376,15 @@ static void rt2800_config_channel(struct
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rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®);
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rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®);
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rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®);
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+
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+ /*
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+ * Clear update flag
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+ */
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+ if (rt2x00_rt(rt2x00dev, RT3352)) {
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+ rt2800_bbp_read(rt2x00dev, 49, &bbp);
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+ rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
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+ rt2800_bbp_write(rt2x00dev, 49, bbp);
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+ }
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}
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static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
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@@ -2998,6 +3073,10 @@ static int rt2800_init_registers(struct
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rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
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rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
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rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
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+ } else if (rt2x00_rt(rt2x00dev, RT3352)) {
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+ rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
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+ rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
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+ rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
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} else if (rt2x00_rt(rt2x00dev, RT3572)) {
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rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
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rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
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@@ -3378,6 +3457,11 @@ static int rt2800_init_bbp(struct rt2x00
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rt2800_wait_bbp_ready(rt2x00dev)))
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return -EACCES;
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+ if (rt2x00_rt(rt2x00dev, RT3352)) {
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+ rt2800_bbp_write(rt2x00dev, 3, 0x00);
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+ rt2800_bbp_write(rt2x00dev, 4, 0x50);
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+ }
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+
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if (rt2x00_rt(rt2x00dev, RT3290) ||
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rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392)) {
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@@ -3388,15 +3472,20 @@ static int rt2800_init_bbp(struct rt2x00
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if (rt2800_is_305x_soc(rt2x00dev) ||
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rt2x00_rt(rt2x00dev, RT3290) ||
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+ rt2x00_rt(rt2x00dev, RT3352) ||
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rt2x00_rt(rt2x00dev, RT3572) ||
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rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392))
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rt2800_bbp_write(rt2x00dev, 31, 0x08);
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+ if (rt2x00_rt(rt2x00dev, RT3352))
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+ rt2800_bbp_write(rt2x00dev, 47, 0x48);
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+
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rt2800_bbp_write(rt2x00dev, 65, 0x2c);
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rt2800_bbp_write(rt2x00dev, 66, 0x38);
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if (rt2x00_rt(rt2x00dev, RT3290) ||
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+ rt2x00_rt(rt2x00dev, RT3352) ||
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rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392))
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rt2800_bbp_write(rt2x00dev, 68, 0x0b);
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@@ -3405,6 +3494,7 @@ static int rt2800_init_bbp(struct rt2x00
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rt2800_bbp_write(rt2x00dev, 69, 0x16);
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rt2800_bbp_write(rt2x00dev, 73, 0x12);
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} else if (rt2x00_rt(rt2x00dev, RT3290) ||
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+ rt2x00_rt(rt2x00dev, RT3352) ||
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rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392)) {
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rt2800_bbp_write(rt2x00dev, 69, 0x12);
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@@ -3436,6 +3526,10 @@ static int rt2800_init_bbp(struct rt2x00
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} else if (rt2800_is_305x_soc(rt2x00dev)) {
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rt2800_bbp_write(rt2x00dev, 78, 0x0e);
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rt2800_bbp_write(rt2x00dev, 80, 0x08);
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+ } else if (rt2x00_rt(rt2x00dev, RT3352)) {
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+ rt2800_bbp_write(rt2x00dev, 78, 0x0e);
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+ rt2800_bbp_write(rt2x00dev, 80, 0x08);
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+ rt2800_bbp_write(rt2x00dev, 81, 0x37);
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} else {
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rt2800_bbp_write(rt2x00dev, 81, 0x37);
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}
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@@ -3465,18 +3559,21 @@ static int rt2800_init_bbp(struct rt2x00
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rt2800_bbp_write(rt2x00dev, 84, 0x99);
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if (rt2x00_rt(rt2x00dev, RT3290) ||
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+ rt2x00_rt(rt2x00dev, RT3352) ||
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rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392))
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rt2800_bbp_write(rt2x00dev, 86, 0x38);
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else
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rt2800_bbp_write(rt2x00dev, 86, 0x00);
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- if (rt2x00_rt(rt2x00dev, RT5392))
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+ if (rt2x00_rt(rt2x00dev, RT3352) ||
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+ rt2x00_rt(rt2x00dev, RT5392))
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rt2800_bbp_write(rt2x00dev, 88, 0x90);
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rt2800_bbp_write(rt2x00dev, 91, 0x04);
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if (rt2x00_rt(rt2x00dev, RT3290) ||
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+ rt2x00_rt(rt2x00dev, RT3352) ||
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rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392))
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rt2800_bbp_write(rt2x00dev, 92, 0x02);
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@@ -3493,6 +3590,7 @@ static int rt2800_init_bbp(struct rt2x00
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rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
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rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
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rt2x00_rt(rt2x00dev, RT3290) ||
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+ rt2x00_rt(rt2x00dev, RT3352) ||
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rt2x00_rt(rt2x00dev, RT3572) ||
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rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392) ||
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@@ -3502,6 +3600,7 @@ static int rt2800_init_bbp(struct rt2x00
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rt2800_bbp_write(rt2x00dev, 103, 0x00);
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if (rt2x00_rt(rt2x00dev, RT3290) ||
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+ rt2x00_rt(rt2x00dev, RT3352) ||
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rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392))
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rt2800_bbp_write(rt2x00dev, 104, 0x92);
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@@ -3510,6 +3609,8 @@ static int rt2800_init_bbp(struct rt2x00
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rt2800_bbp_write(rt2x00dev, 105, 0x01);
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else if (rt2x00_rt(rt2x00dev, RT3290))
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rt2800_bbp_write(rt2x00dev, 105, 0x1c);
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+ else if (rt2x00_rt(rt2x00dev, RT3352))
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+ rt2800_bbp_write(rt2x00dev, 105, 0x34);
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else if (rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392))
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rt2800_bbp_write(rt2x00dev, 105, 0x3c);
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@@ -3519,11 +3620,16 @@ static int rt2800_init_bbp(struct rt2x00
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if (rt2x00_rt(rt2x00dev, RT3290) ||
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rt2x00_rt(rt2x00dev, RT5390))
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rt2800_bbp_write(rt2x00dev, 106, 0x03);
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+ else if (rt2x00_rt(rt2x00dev, RT3352))
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+ rt2800_bbp_write(rt2x00dev, 106, 0x05);
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else if (rt2x00_rt(rt2x00dev, RT5392))
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rt2800_bbp_write(rt2x00dev, 106, 0x12);
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else
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rt2800_bbp_write(rt2x00dev, 106, 0x35);
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+ if (rt2x00_rt(rt2x00dev, RT3352))
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+ rt2800_bbp_write(rt2x00dev, 120, 0x50);
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+
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if (rt2x00_rt(rt2x00dev, RT3290) ||
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rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392))
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@@ -3534,6 +3640,9 @@ static int rt2800_init_bbp(struct rt2x00
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rt2800_bbp_write(rt2x00dev, 135, 0xf6);
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}
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+ if (rt2x00_rt(rt2x00dev, RT3352))
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+ rt2800_bbp_write(rt2x00dev, 137, 0x0f);
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+
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if (rt2x00_rt(rt2x00dev, RT3071) ||
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rt2x00_rt(rt2x00dev, RT3090) ||
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rt2x00_rt(rt2x00dev, RT3390) ||
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@@ -3574,6 +3683,28 @@ static int rt2800_init_bbp(struct rt2x00
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rt2800_bbp_write(rt2x00dev, 3, value);
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}
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+ if (rt2x00_rt(rt2x00dev, RT3352)) {
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+ rt2800_bbp_write(rt2x00dev, 163, 0xbd);
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+ /* Set ITxBF timeout to 0x9c40=1000msec */
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+ rt2800_bbp_write(rt2x00dev, 179, 0x02);
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+ rt2800_bbp_write(rt2x00dev, 180, 0x00);
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+ rt2800_bbp_write(rt2x00dev, 182, 0x40);
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+ rt2800_bbp_write(rt2x00dev, 180, 0x01);
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+ rt2800_bbp_write(rt2x00dev, 182, 0x9c);
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+ rt2800_bbp_write(rt2x00dev, 179, 0x00);
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+ /* Reprogram the inband interface to put right values in RXWI */
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+ rt2800_bbp_write(rt2x00dev, 142, 0x04);
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+ rt2800_bbp_write(rt2x00dev, 143, 0x3b);
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+ rt2800_bbp_write(rt2x00dev, 142, 0x06);
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+ rt2800_bbp_write(rt2x00dev, 143, 0xa0);
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+ rt2800_bbp_write(rt2x00dev, 142, 0x07);
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+ rt2800_bbp_write(rt2x00dev, 143, 0xa1);
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+ rt2800_bbp_write(rt2x00dev, 142, 0x08);
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+ rt2800_bbp_write(rt2x00dev, 143, 0xa2);
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+
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+ rt2800_bbp_write(rt2x00dev, 148, 0xc8);
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+ }
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+
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if (rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392)) {
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int ant, div_mode;
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@@ -3707,6 +3838,7 @@ static int rt2800_init_rfcsr(struct rt2x
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!rt2x00_rt(rt2x00dev, RT3071) &&
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!rt2x00_rt(rt2x00dev, RT3090) &&
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!rt2x00_rt(rt2x00dev, RT3290) &&
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+ !rt2x00_rt(rt2x00dev, RT3352) &&
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!rt2x00_rt(rt2x00dev, RT3390) &&
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!rt2x00_rt(rt2x00dev, RT3572) &&
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!rt2x00_rt(rt2x00dev, RT5390) &&
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@@ -3903,6 +4035,70 @@ static int rt2800_init_rfcsr(struct rt2x
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rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
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rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
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return 0;
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+ } else if (rt2x00_rt(rt2x00dev, RT3352)) {
|
|
+ rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
|
|
+ rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
|
|
} else if (rt2x00_rt(rt2x00dev, RT5390)) {
|
|
rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
|
|
rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
|
|
@@ -4104,6 +4300,7 @@ static int rt2800_init_rfcsr(struct rt2x
|
|
rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
|
|
} else if (rt2x00_rt(rt2x00dev, RT3071) ||
|
|
rt2x00_rt(rt2x00dev, RT3090) ||
|
|
+ rt2x00_rt(rt2x00dev, RT3352) ||
|
|
rt2x00_rt(rt2x00dev, RT3390) ||
|
|
rt2x00_rt(rt2x00dev, RT3572)) {
|
|
drv_data->calibration_bw20 =
|
|
@@ -4566,6 +4763,7 @@ static int rt2800_init_eeprom(struct rt2
|
|
case RT3071:
|
|
case RT3090:
|
|
case RT3290:
|
|
+ case RT3352:
|
|
case RT3390:
|
|
case RT3572:
|
|
case RT5390:
|
|
@@ -4588,6 +4786,7 @@ static int rt2800_init_eeprom(struct rt2
|
|
case RF3052:
|
|
case RF3290:
|
|
case RF3320:
|
|
+ case RF3322:
|
|
case RF5360:
|
|
case RF5370:
|
|
case RF5372:
|
|
@@ -4612,6 +4811,7 @@ static int rt2800_init_eeprom(struct rt2
|
|
|
|
if (rt2x00_rt(rt2x00dev, RT3070) ||
|
|
rt2x00_rt(rt2x00dev, RT3090) ||
|
|
+ rt2x00_rt(rt2x00dev, RT3352) ||
|
|
rt2x00_rt(rt2x00dev, RT3390)) {
|
|
value = rt2x00_get_field16(eeprom,
|
|
EEPROM_NIC_CONF1_ANT_DIVERSITY);
|
|
@@ -4904,6 +5104,7 @@ static int rt2800_probe_hw_mode(struct r
|
|
rt2x00_rf(rt2x00dev, RF3022) ||
|
|
rt2x00_rf(rt2x00dev, RF3290) ||
|
|
rt2x00_rf(rt2x00dev, RF3320) ||
|
|
+ rt2x00_rf(rt2x00dev, RF3322) ||
|
|
rt2x00_rf(rt2x00dev, RF5360) ||
|
|
rt2x00_rf(rt2x00dev, RF5370) ||
|
|
rt2x00_rf(rt2x00dev, RF5372) ||
|
|
--- a/drivers/net/wireless/rt2x00/rt2x00.h
|
|
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
|
|
@@ -189,6 +189,7 @@ struct rt2x00_chip {
|
|
#define RT3071 0x3071
|
|
#define RT3090 0x3090 /* 2.4GHz PCIe */
|
|
#define RT3290 0x3290
|
|
+#define RT3352 0x3352 /* WSOC */
|
|
#define RT3390 0x3390
|
|
#define RT3572 0x3572
|
|
#define RT3593 0x3593
|