mirror of https://github.com/hak5/openwrt.git
2419 lines
76 KiB
Diff
2419 lines
76 KiB
Diff
From 75ae3f717d7598a6eb1582097923ee0838a02a8b Mon Sep 17 00:00:00 2001
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From: popcornmix <popcornmix@gmail.com>
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Date: Sun, 12 May 2013 12:24:19 +0100
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Subject: [PATCH 027/127] Main bcm2708/bcm2709 linux port
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Signed-off-by: popcornmix <popcornmix@gmail.com>
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Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
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---
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arch/arm/Kconfig | 49 +++
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arch/arm/Kconfig.debug | 8 +
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arch/arm/Makefile | 2 +
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arch/arm/kernel/head.S | 8 +
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arch/arm/kernel/process.c | 10 +
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arch/arm/mach-bcm2708/Kconfig | 23 ++
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arch/arm/mach-bcm2708/Makefile | 5 +
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arch/arm/mach-bcm2708/Makefile.boot | 3 +
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arch/arm/mach-bcm2708/bcm2708.c | 231 ++++++++++++
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arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 ++
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arch/arm/mach-bcm2708/include/mach/io.h | 27 ++
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arch/arm/mach-bcm2708/include/mach/memory.h | 57 +++
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arch/arm/mach-bcm2708/include/mach/platform.h | 112 ++++++
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arch/arm/mach-bcm2708/include/mach/system.h | 37 ++
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arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 +++++
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arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 ++
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arch/arm/mach-bcm2709/Kconfig | 16 +
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arch/arm/mach-bcm2709/Makefile | 5 +
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arch/arm/mach-bcm2709/Makefile.boot | 3 +
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arch/arm/mach-bcm2709/bcm2709.c | 380 ++++++++++++++++++++
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arch/arm/mach-bcm2709/include/mach/debug-macro.S | 22 ++
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arch/arm/mach-bcm2709/include/mach/entry-macro.S | 123 +++++++
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arch/arm/mach-bcm2709/include/mach/io.h | 27 ++
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arch/arm/mach-bcm2709/include/mach/memory.h | 57 +++
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arch/arm/mach-bcm2709/include/mach/platform.h | 188 ++++++++++
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arch/arm/mach-bcm2709/include/mach/system.h | 37 ++
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arch/arm/mach-bcm2709/include/mach/uncompress.h | 84 +++++
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arch/arm/mach-bcm2709/include/mach/vc_mem.h | 35 ++
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arch/arm/mach-bcm2709/include/mach/vmalloc.h | 20 ++
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arch/arm/mach-bcm2709/vc_mem.c | 431 +++++++++++++++++++++++
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arch/arm/mm/Kconfig | 2 +-
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arch/arm/mm/proc-v6.S | 15 +-
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arch/arm/mm/proc-v7.S | 1 +
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arch/arm/tools/mach-types | 2 +
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drivers/clocksource/Makefile | 2 +-
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drivers/irqchip/Makefile | 3 +
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include/linux/mmc/host.h | 1 +
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37 files changed, 2147 insertions(+), 5 deletions(-)
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create mode 100644 arch/arm/mach-bcm2708/Kconfig
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create mode 100644 arch/arm/mach-bcm2708/Makefile
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create mode 100644 arch/arm/mach-bcm2708/Makefile.boot
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create mode 100644 arch/arm/mach-bcm2708/bcm2708.c
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create mode 100644 arch/arm/mach-bcm2708/include/mach/debug-macro.S
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create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h
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create mode 100644 arch/arm/mach-bcm2708/include/mach/memory.h
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create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h
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create mode 100644 arch/arm/mach-bcm2708/include/mach/system.h
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create mode 100644 arch/arm/mach-bcm2708/include/mach/uncompress.h
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create mode 100644 arch/arm/mach-bcm2708/include/mach/vmalloc.h
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create mode 100644 arch/arm/mach-bcm2709/Kconfig
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create mode 100644 arch/arm/mach-bcm2709/Makefile
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create mode 100644 arch/arm/mach-bcm2709/Makefile.boot
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create mode 100644 arch/arm/mach-bcm2709/bcm2709.c
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create mode 100644 arch/arm/mach-bcm2709/include/mach/debug-macro.S
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create mode 100644 arch/arm/mach-bcm2709/include/mach/entry-macro.S
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create mode 100644 arch/arm/mach-bcm2709/include/mach/io.h
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create mode 100644 arch/arm/mach-bcm2709/include/mach/memory.h
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create mode 100644 arch/arm/mach-bcm2709/include/mach/platform.h
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create mode 100644 arch/arm/mach-bcm2709/include/mach/system.h
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create mode 100644 arch/arm/mach-bcm2709/include/mach/uncompress.h
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create mode 100644 arch/arm/mach-bcm2709/include/mach/vc_mem.h
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create mode 100644 arch/arm/mach-bcm2709/include/mach/vmalloc.h
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create mode 100644 arch/arm/mach-bcm2709/vc_mem.c
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--- a/arch/arm/Kconfig
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+++ b/arch/arm/Kconfig
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@@ -317,6 +317,52 @@ choice
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default ARCH_VERSATILE if !MMU
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default ARCH_MULTIPLATFORM if MMU
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+config ARCH_BCM2708
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+ bool "Broadcom BCM2708 family"
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+ select CPU_V6
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+ select ARM_AMBA
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+ select CLKSRC_MMIO
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+ select CLKSRC_OF if OF
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+ select HAVE_SCHED_CLOCK
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+ select NEED_MACH_GPIO_H
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+ select NEED_MACH_MEMORY_H
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+ select COMMON_CLK
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+ select ARCH_HAS_CPUFREQ
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+ select GENERIC_CLOCKEVENTS
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+ select ARM_ERRATA_411920
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+ select MACH_BCM2708
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+ select MULTI_IRQ_HANDLER
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+ select SPARSE_IRQ
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+ select VC4
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+ select FIQ
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+ help
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+ This enables support for Broadcom BCM2708 boards.
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+
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+config ARCH_BCM2709
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+ bool "Broadcom BCM2709 family"
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+ select CPU_V7
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+ select HAVE_SMP
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+ select ARM_AMBA
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+ select MIGHT_HAVE_CACHE_L2X0
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+ select HAVE_SCHED_CLOCK
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+ select NEED_MACH_MEMORY_H
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+ select NEED_MACH_IO_H
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+ select COMMON_CLK
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+ select ARCH_HAS_CPUFREQ
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+ select GENERIC_CLOCKEVENTS
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+ select MACH_BCM2709
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+ select MULTI_IRQ_HANDLER
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+ select SPARSE_IRQ
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+ select MFD_SYSCON
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+ select VC4
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+ select FIQ
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+ select USE_OF
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+ select ARCH_REQUIRE_GPIOLIB
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+ select PINCTRL
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+ select PINCTRL_BCM2835
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+ help
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+ This enables support for Broadcom BCM2709 boards.
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+
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config ARCH_MULTIPLATFORM
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bool "Allow multiple platforms to be selected"
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depends on MMU
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@@ -808,6 +854,9 @@ config ARCH_VIRT
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# Kconfigs may be included either alphabetically (according to the
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# plat- suffix) or along side the corresponding mach-* source.
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#
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+source "arch/arm/mach-bcm2708/Kconfig"
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+source "arch/arm/mach-bcm2709/Kconfig"
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+
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source "arch/arm/mach-mvebu/Kconfig"
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source "arch/arm/mach-alpine/Kconfig"
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--- a/arch/arm/Kconfig.debug
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+++ b/arch/arm/Kconfig.debug
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@@ -1241,6 +1241,14 @@ choice
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options; the platform specific options are deprecated
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and will be soon removed.
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+ config DEBUG_BCM2708_UART0
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+ bool "Broadcom BCM270X UART0 (PL011)"
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+ depends on ARCH_BCM2708 || ARCH_BCM2709
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+ help
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+ Say Y here if you want the debug print routines to direct
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+ their output to UART 0. The port must have been initialised
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+ by the boot-loader before use.
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+
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endchoice
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config DEBUG_EXYNOS_UART
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--- a/arch/arm/Makefile
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+++ b/arch/arm/Makefile
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@@ -159,6 +159,8 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x003080
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# Machine directory name. This list is sorted alphanumerically
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# by CONFIG_* macro name.
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+machine-$(CONFIG_ARCH_BCM2708) += bcm2708
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+machine-$(CONFIG_ARCH_BCM2709) += bcm2709
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machine-$(CONFIG_ARCH_ALPINE) += alpine
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machine-$(CONFIG_ARCH_AT91) += at91
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machine-$(CONFIG_ARCH_AXXIA) += axxia
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--- a/arch/arm/kernel/head.S
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+++ b/arch/arm/kernel/head.S
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@@ -700,6 +700,14 @@ ARM_BE8(rev16 ip, ip)
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ldrcc r7, [r4], #4 @ use branch for delay slot
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bcc 1b
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ret lr
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+ nop
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+ nop
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+ nop
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+ nop
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+ nop
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+ nop
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+ nop
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+ nop
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#endif
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ENDPROC(__fixup_a_pv_table)
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--- a/arch/arm/kernel/process.c
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+++ b/arch/arm/kernel/process.c
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@@ -91,6 +91,16 @@ void arch_cpu_idle_exit(void)
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ledtrig_cpu(CPU_LED_IDLE_END);
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}
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+char bcm2708_reboot_mode = 'h';
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+
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+int __init reboot_setup(char *str)
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+{
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+ bcm2708_reboot_mode = str[0];
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+ return 1;
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+}
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+
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+__setup("reboot=", reboot_setup);
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+
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void __show_regs(struct pt_regs *regs)
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{
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unsigned long flags;
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--- /dev/null
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+++ b/arch/arm/mach-bcm2708/Kconfig
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@@ -0,0 +1,23 @@
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+menu "Broadcom BCM2708 Implementations"
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+ depends on ARCH_BCM2708
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+
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+config MACH_BCM2708
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+ bool "Broadcom BCM2708 Development Platform"
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+ select NEED_MACH_MEMORY_H
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+ select NEED_MACH_IO_H
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+ select CPU_V6
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+ select USE_OF
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+ select ARCH_REQUIRE_GPIOLIB
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+ select PINCTRL
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+ select PINCTRL_BCM2835
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+ help
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+ Include support for the Broadcom(R) BCM2708 platform.
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+
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+config BCM2708_NOL2CACHE
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+ bool "Videocore L2 cache disable"
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+ depends on MACH_BCM2708
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+ default n
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+ help
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+ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
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+
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+endmenu
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--- /dev/null
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+++ b/arch/arm/mach-bcm2708/Makefile
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@@ -0,0 +1,5 @@
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+#
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+# Makefile for the linux kernel.
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+#
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+
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+obj-$(CONFIG_MACH_BCM2708) += bcm2708.o
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--- /dev/null
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+++ b/arch/arm/mach-bcm2708/Makefile.boot
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@@ -0,0 +1,3 @@
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+ zreladdr-y := 0x00008000
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+params_phys-y := 0x00000100
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+initrd_phys-y := 0x00800000
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--- /dev/null
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+++ b/arch/arm/mach-bcm2708/bcm2708.c
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@@ -0,0 +1,231 @@
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+/*
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+ * linux/arch/arm/mach-bcm2708/bcm2708.c
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+ *
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+ * Copyright (C) 2010 Broadcom
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/module.h>
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+#include <linux/of_platform.h>
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+#include <asm/system_info.h>
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+#include <asm/mach-types.h>
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+#include <asm/mach/arch.h>
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+#include <asm/mach/map.h>
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+
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+#include <mach/system.h>
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+
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+#include <linux/broadcom/vc_cma.h>
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+
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+/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
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+ * give us IO access only to 64Mbytes of physical memory (26 bits). We could
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+ * represent this window by setting our dmamasks to 26 bits but, in fact
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+ * we're not going to use addresses outside this range (they're not in real
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+ * memory) so we don't bother.
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+ *
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+ * In the future we might include code to use this IOMMU to remap other
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+ * physical addresses onto VideoCore memory then the use of 32-bits would be
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+ * more legitimate.
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+ */
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+
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+/* command line parameters */
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+static unsigned boardrev, serial;
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+static unsigned reboot_part = 0;
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+
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+static struct map_desc bcm2708_io_desc[] __initdata = {
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+ {
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+ .virtual = IO_ADDRESS(ARMCTRL_BASE),
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+ .pfn = __phys_to_pfn(ARMCTRL_BASE),
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+ .length = SZ_4K,
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+ .type = MT_DEVICE},
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+ {
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+ .virtual = IO_ADDRESS(UART0_BASE),
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+ .pfn = __phys_to_pfn(UART0_BASE),
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+ .length = SZ_4K,
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+ .type = MT_DEVICE},
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+ {
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+ .virtual = IO_ADDRESS(UART1_BASE),
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+ .pfn = __phys_to_pfn(UART1_BASE),
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+ .length = SZ_4K,
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+ .type = MT_DEVICE},
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+ {
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+ .virtual = IO_ADDRESS(DMA_BASE),
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+ .pfn = __phys_to_pfn(DMA_BASE),
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+ .length = SZ_4K,
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+ .type = MT_DEVICE},
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+ {
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+ .virtual = IO_ADDRESS(MCORE_BASE),
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+ .pfn = __phys_to_pfn(MCORE_BASE),
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+ .length = SZ_4K,
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+ .type = MT_DEVICE},
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+ {
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+ .virtual = IO_ADDRESS(ST_BASE),
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+ .pfn = __phys_to_pfn(ST_BASE),
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+ .length = SZ_4K,
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+ .type = MT_DEVICE},
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+ {
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+ .virtual = IO_ADDRESS(USB_BASE),
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+ .pfn = __phys_to_pfn(USB_BASE),
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+ .length = SZ_128K,
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+ .type = MT_DEVICE},
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+ {
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+ .virtual = IO_ADDRESS(PM_BASE),
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+ .pfn = __phys_to_pfn(PM_BASE),
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+ .length = SZ_4K,
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+ .type = MT_DEVICE},
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+ {
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+ .virtual = IO_ADDRESS(GPIO_BASE),
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+ .pfn = __phys_to_pfn(GPIO_BASE),
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+ .length = SZ_4K,
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+ .type = MT_DEVICE}
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+};
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+
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+void __init bcm2708_map_io(void)
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+{
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+ iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
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+}
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+
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+int calc_rsts(int partition)
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+{
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+ return PM_PASSWORD |
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+ ((partition & (1 << 0)) << 0) |
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+ ((partition & (1 << 1)) << 1) |
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+ ((partition & (1 << 2)) << 2) |
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+ ((partition & (1 << 3)) << 3) |
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+ ((partition & (1 << 4)) << 4) |
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+ ((partition & (1 << 5)) << 5);
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+}
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+
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+static void bcm2708_restart(enum reboot_mode mode, const char *cmd)
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+{
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+ extern char bcm2708_reboot_mode;
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+ uint32_t pm_rstc, pm_wdog;
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+ uint32_t timeout = 10;
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+ uint32_t pm_rsts = 0;
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+
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+ if(bcm2708_reboot_mode == 'q')
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+ {
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+ // NOOBS < 1.3 booting with reboot=q
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+ pm_rsts = readl(__io_address(PM_RSTS));
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+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
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+ }
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+ else if(bcm2708_reboot_mode == 'p')
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+ {
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+ // NOOBS < 1.3 halting
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+ pm_rsts = readl(__io_address(PM_RSTS));
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+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
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+ }
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+ else
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+ {
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+ pm_rsts = calc_rsts(reboot_part);
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+ }
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+
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+ writel(pm_rsts, __io_address(PM_RSTS));
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+
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+ /* Setup watchdog for reset */
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+ pm_rstc = readl(__io_address(PM_RSTC));
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+
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+ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
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+ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
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+
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+ writel(pm_wdog, __io_address(PM_WDOG));
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+ writel(pm_rstc, __io_address(PM_RSTC));
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+}
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+
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+/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
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+static void bcm2708_power_off(void)
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+{
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+ extern char bcm2708_reboot_mode;
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+ if(bcm2708_reboot_mode == 'q')
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+ {
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+ // NOOBS < v1.3
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+ bcm2708_restart('p', "");
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+ }
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+ else
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+ {
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+ /* partition 63 is special code for HALT the bootloader knows not to boot*/
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+ reboot_part = 63;
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+ /* continue with normal reset mechanism */
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+ bcm2708_restart(0, "");
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+ }
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+}
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+
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+static void __init bcm2708_init_uart1(void)
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+{
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+ struct device_node *np;
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+
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+ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart");
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+ if (of_device_is_available(np)) {
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+ pr_info("bcm2708: Mini UART enabled\n");
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+ writel(1, __io_address(UART1_BASE + 0x4));
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+ }
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+}
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+
|
|
+void __init bcm2708_init(void)
|
|
+{
|
|
+ int ret;
|
|
+
|
|
+ vc_cma_early_init();
|
|
+
|
|
+ pm_power_off = bcm2708_power_off;
|
|
+
|
|
+ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
|
|
+ NULL);
|
|
+ if (ret) {
|
|
+ pr_err("of_platform_populate failed: %d\n", ret);
|
|
+ BUG();
|
|
+ }
|
|
+
|
|
+ bcm2708_init_uart1();
|
|
+
|
|
+ system_rev = boardrev;
|
|
+ system_serial_low = serial;
|
|
+}
|
|
+
|
|
+void __init bcm2708_init_early(void)
|
|
+{
|
|
+ /*
|
|
+ * Some devices allocate their coherent buffers from atomic
|
|
+ * context. Increase size of atomic coherent pool to make sure such
|
|
+ * the allocations won't fail.
|
|
+ */
|
|
+ init_dma_coherent_pool_size(SZ_4M);
|
|
+}
|
|
+
|
|
+static void __init board_reserve(void)
|
|
+{
|
|
+ vc_cma_reserve();
|
|
+}
|
|
+
|
|
+static const char * const bcm2708_compat[] = {
|
|
+ "brcm,bcm2708",
|
|
+ NULL
|
|
+};
|
|
+
|
|
+MACHINE_START(BCM2708, "BCM2708")
|
|
+ /* Maintainer: Broadcom Europe Ltd. */
|
|
+ .map_io = bcm2708_map_io,
|
|
+ .init_machine = bcm2708_init,
|
|
+ .init_early = bcm2708_init_early,
|
|
+ .reserve = board_reserve,
|
|
+ .restart = bcm2708_restart,
|
|
+ .dt_compat = bcm2708_compat,
|
|
+MACHINE_END
|
|
+
|
|
+module_param(boardrev, uint, 0644);
|
|
+module_param(serial, uint, 0644);
|
|
+module_param(reboot_part, uint, 0644);
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
|
|
@@ -0,0 +1,22 @@
|
|
+/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
|
|
+ *
|
|
+ * Debugging macro include header
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ * Copyright (C) 1994-1999 Russell King
|
|
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License version 2 as
|
|
+ * published by the Free Software Foundation.
|
|
+ *
|
|
+*/
|
|
+
|
|
+#include <mach/platform.h>
|
|
+
|
|
+ .macro addruart, rp, rv, tmp
|
|
+ ldr \rp, =UART0_BASE
|
|
+ ldr \rv, =IO_ADDRESS(UART0_BASE)
|
|
+ .endm
|
|
+
|
|
+#include <debug/pl01x.S>
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2708/include/mach/io.h
|
|
@@ -0,0 +1,27 @@
|
|
+/*
|
|
+ * arch/arm/mach-bcm2708/include/mach/io.h
|
|
+ *
|
|
+ * Copyright (C) 2003 ARM Limited
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+#ifndef __ASM_ARM_ARCH_IO_H
|
|
+#define __ASM_ARM_ARCH_IO_H
|
|
+
|
|
+#define IO_SPACE_LIMIT 0xffffffff
|
|
+
|
|
+#define __io(a) __typesafe_io(a)
|
|
+
|
|
+#endif
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2708/include/mach/memory.h
|
|
@@ -0,0 +1,57 @@
|
|
+/*
|
|
+ * arch/arm/mach-bcm2708/include/mach/memory.h
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+#ifndef __ASM_ARCH_MEMORY_H
|
|
+#define __ASM_ARCH_MEMORY_H
|
|
+
|
|
+/* Memory overview:
|
|
+
|
|
+ [ARMcore] <--virtual addr-->
|
|
+ [ARMmmu] <--physical addr-->
|
|
+ [GERTmap] <--bus add-->
|
|
+ [VCperiph]
|
|
+
|
|
+*/
|
|
+
|
|
+/*
|
|
+ * Physical DRAM offset.
|
|
+ */
|
|
+#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
|
|
+#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
|
|
+
|
|
+#ifdef CONFIG_BCM2708_NOL2CACHE
|
|
+ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
|
|
+#else
|
|
+ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
|
|
+#endif
|
|
+
|
|
+/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
|
|
+ * will provide the offset into this area as well as setting the bits that
|
|
+ * stop the L1 and L2 cache from being used
|
|
+ *
|
|
+ * WARNING: this only works because the ARM is given memory at a fixed location
|
|
+ * (ARMMEM_OFFSET)
|
|
+ */
|
|
+#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
|
|
+#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
|
|
+#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
|
|
+#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
|
|
+#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
|
|
+
|
|
+#endif
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2708/include/mach/platform.h
|
|
@@ -0,0 +1,112 @@
|
|
+/*
|
|
+ * arch/arm/mach-bcm2708/include/mach/platform.h
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+
|
|
+#ifndef _BCM2708_PLATFORM_H
|
|
+#define _BCM2708_PLATFORM_H
|
|
+
|
|
+
|
|
+/* macros to get at IO space when running virtually */
|
|
+#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
|
|
+
|
|
+#define __io_address(n) IOMEM(IO_ADDRESS(n))
|
|
+
|
|
+
|
|
+/*
|
|
+ * SDRAM
|
|
+ */
|
|
+#define BCM2708_SDRAM_BASE 0x00000000
|
|
+
|
|
+/*
|
|
+ * Logic expansion modules
|
|
+ *
|
|
+ */
|
|
+
|
|
+
|
|
+/* ------------------------------------------------------------------------
|
|
+ * BCM2708 ARMCTRL Registers
|
|
+ * ------------------------------------------------------------------------
|
|
+ */
|
|
+
|
|
+#define HW_REGISTER_RW(addr) (addr)
|
|
+#define HW_REGISTER_RO(addr) (addr)
|
|
+
|
|
+/*
|
|
+ * Definitions and addresses for the ARM CONTROL logic
|
|
+ * This file is manually generated.
|
|
+ */
|
|
+
|
|
+#define BCM2708_PERI_BASE 0x20000000
|
|
+#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
|
|
+#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
|
|
+#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
|
|
+#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
|
|
+#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
|
|
+#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
|
|
+#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
|
|
+#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
|
|
+#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
|
|
+#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
|
|
+#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
|
|
+#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
|
|
+#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
|
|
+#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
|
|
+#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
|
|
+#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
|
|
+#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
|
|
+#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
|
|
+#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
|
|
+#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
|
|
+
|
|
+#define ARMCTRL_BASE (ARM_BASE + 0x000)
|
|
+#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
|
|
+#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
|
|
+#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
|
|
+
|
|
+/*
|
|
+ * Watchdog
|
|
+ */
|
|
+#define PM_RSTC (PM_BASE+0x1c)
|
|
+#define PM_RSTS (PM_BASE+0x20)
|
|
+#define PM_WDOG (PM_BASE+0x24)
|
|
+
|
|
+#define PM_WDOG_RESET 0000000000
|
|
+#define PM_PASSWORD 0x5a000000
|
|
+#define PM_WDOG_TIME_SET 0x000fffff
|
|
+#define PM_RSTC_WRCFG_CLR 0xffffffcf
|
|
+#define PM_RSTC_WRCFG_SET 0x00000030
|
|
+#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
|
|
+#define PM_RSTC_RESET 0x00000102
|
|
+
|
|
+#define PM_RSTS_HADPOR_SET 0x00001000
|
|
+#define PM_RSTS_HADSRH_SET 0x00000400
|
|
+#define PM_RSTS_HADSRF_SET 0x00000200
|
|
+#define PM_RSTS_HADSRQ_SET 0x00000100
|
|
+#define PM_RSTS_HADWRH_SET 0x00000040
|
|
+#define PM_RSTS_HADWRF_SET 0x00000020
|
|
+#define PM_RSTS_HADWRQ_SET 0x00000010
|
|
+#define PM_RSTS_HADDRH_SET 0x00000004
|
|
+#define PM_RSTS_HADDRF_SET 0x00000002
|
|
+#define PM_RSTS_HADDRQ_SET 0x00000001
|
|
+
|
|
+#define UART0_CLOCK 3000000
|
|
+
|
|
+#endif
|
|
+
|
|
+/* END */
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2708/include/mach/system.h
|
|
@@ -0,0 +1,37 @@
|
|
+/*
|
|
+ * arch/arm/mach-bcm2708/include/mach/system.h
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ * Copyright (C) 2003 ARM Limited
|
|
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+#ifndef __ASM_ARCH_SYSTEM_H
|
|
+#define __ASM_ARCH_SYSTEM_H
|
|
+
|
|
+#include <linux/io.h>
|
|
+#include <mach/platform.h>
|
|
+
|
|
+static inline void arch_idle(void)
|
|
+{
|
|
+ /*
|
|
+ * This should do all the clock switching
|
|
+ * and wait for interrupt tricks
|
|
+ */
|
|
+ cpu_do_idle();
|
|
+}
|
|
+
|
|
+#endif
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2708/include/mach/uncompress.h
|
|
@@ -0,0 +1,84 @@
|
|
+/*
|
|
+ * arch/arm/mach-bcn2708/include/mach/uncompress.h
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ * Copyright (C) 2003 ARM Limited
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+
|
|
+#include <linux/io.h>
|
|
+#include <linux/amba/serial.h>
|
|
+#include <mach/platform.h>
|
|
+
|
|
+#define UART_BAUD 115200
|
|
+
|
|
+#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
|
|
+#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
|
|
+#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
|
|
+#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
|
|
+#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
|
|
+#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
|
|
+
|
|
+/*
|
|
+ * This does not append a newline
|
|
+ */
|
|
+static inline void putc(int c)
|
|
+{
|
|
+ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
|
|
+ barrier();
|
|
+
|
|
+ __raw_writel(c, BCM2708_UART_DR);
|
|
+}
|
|
+
|
|
+static inline void flush(void)
|
|
+{
|
|
+ int fr;
|
|
+
|
|
+ do {
|
|
+ fr = __raw_readl(BCM2708_UART_FR);
|
|
+ barrier();
|
|
+ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
|
|
+}
|
|
+
|
|
+static inline void arch_decomp_setup(void)
|
|
+{
|
|
+ int temp, div, rem, frac;
|
|
+
|
|
+ temp = 16 * UART_BAUD;
|
|
+ div = UART0_CLOCK / temp;
|
|
+ rem = UART0_CLOCK % temp;
|
|
+ temp = (8 * rem) / UART_BAUD;
|
|
+ frac = (temp >> 1) + (temp & 1);
|
|
+
|
|
+ /* Make sure the UART is disabled before we start */
|
|
+ __raw_writel(0, BCM2708_UART_CR);
|
|
+
|
|
+ /* Set the baud rate */
|
|
+ __raw_writel(div, BCM2708_UART_IBRD);
|
|
+ __raw_writel(frac, BCM2708_UART_FBRD);
|
|
+
|
|
+ /* Set the UART to 8n1, FIFO enabled */
|
|
+ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
|
|
+
|
|
+ /* Enable the UART */
|
|
+ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
|
|
+ BCM2708_UART_CR);
|
|
+}
|
|
+
|
|
+/*
|
|
+ * nothing to do
|
|
+ */
|
|
+#define arch_decomp_wdog()
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2708/include/mach/vmalloc.h
|
|
@@ -0,0 +1,20 @@
|
|
+/*
|
|
+ * arch/arm/mach-bcm2708/include/mach/vmalloc.h
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+#define VMALLOC_END (0xe8000000)
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/Kconfig
|
|
@@ -0,0 +1,16 @@
|
|
+menu "Broadcom BCM2709 Implementations"
|
|
+ depends on ARCH_BCM2709
|
|
+
|
|
+config MACH_BCM2709
|
|
+ bool "Broadcom BCM2709 Development Platform"
|
|
+ help
|
|
+ Include support for the Broadcom(R) BCM2709 platform.
|
|
+
|
|
+config BCM2708_NOL2CACHE
|
|
+ bool "Videocore L2 cache disable"
|
|
+ depends on MACH_BCM2709
|
|
+ default y
|
|
+ help
|
|
+ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
|
|
+
|
|
+endmenu
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/Makefile
|
|
@@ -0,0 +1,5 @@
|
|
+#
|
|
+# Makefile for the linux kernel.
|
|
+#
|
|
+
|
|
+obj-$(CONFIG_MACH_BCM2709) += bcm2709.o
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/Makefile.boot
|
|
@@ -0,0 +1,3 @@
|
|
+ zreladdr-y := 0x00008000
|
|
+params_phys-y := 0x00000100
|
|
+initrd_phys-y := 0x00800000
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/bcm2709.c
|
|
@@ -0,0 +1,380 @@
|
|
+/*
|
|
+ * linux/arch/arm/mach-bcm2709/bcm2709.c
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+
|
|
+#include <linux/init.h>
|
|
+#include <linux/dma-mapping.h>
|
|
+#include <linux/interrupt.h>
|
|
+#include <linux/clk-provider.h>
|
|
+#include <linux/clocksource.h>
|
|
+#include <linux/io.h>
|
|
+#include <linux/module.h>
|
|
+#include <linux/of_platform.h>
|
|
+
|
|
+#include <asm/system_info.h>
|
|
+#include <asm/mach-types.h>
|
|
+#include <asm/cputype.h>
|
|
+
|
|
+#include <asm/mach/arch.h>
|
|
+#include <asm/mach/map.h>
|
|
+
|
|
+#include <mach/system.h>
|
|
+
|
|
+#include <linux/broadcom/vc_cma.h>
|
|
+
|
|
+/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
|
|
+ * give us IO access only to 64Mbytes of physical memory (26 bits). We could
|
|
+ * represent this window by setting our dmamasks to 26 bits but, in fact
|
|
+ * we're not going to use addresses outside this range (they're not in real
|
|
+ * memory) so we don't bother.
|
|
+ *
|
|
+ * In the future we might include code to use this IOMMU to remap other
|
|
+ * physical addresses onto VideoCore memory then the use of 32-bits would be
|
|
+ * more legitimate.
|
|
+ */
|
|
+
|
|
+/* command line parameters */
|
|
+static unsigned boardrev, serial;
|
|
+static unsigned reboot_part = 0;
|
|
+
|
|
+static struct map_desc bcm2709_io_desc[] __initdata = {
|
|
+ {
|
|
+ .virtual = IO_ADDRESS(ARMCTRL_BASE),
|
|
+ .pfn = __phys_to_pfn(ARMCTRL_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE},
|
|
+ {
|
|
+ .virtual = IO_ADDRESS(UART0_BASE),
|
|
+ .pfn = __phys_to_pfn(UART0_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE},
|
|
+ {
|
|
+ .virtual = IO_ADDRESS(UART1_BASE),
|
|
+ .pfn = __phys_to_pfn(UART1_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE},
|
|
+ {
|
|
+ .virtual = IO_ADDRESS(DMA_BASE),
|
|
+ .pfn = __phys_to_pfn(DMA_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE},
|
|
+ {
|
|
+ .virtual = IO_ADDRESS(MCORE_BASE),
|
|
+ .pfn = __phys_to_pfn(MCORE_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE},
|
|
+ {
|
|
+ .virtual = IO_ADDRESS(ST_BASE),
|
|
+ .pfn = __phys_to_pfn(ST_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE},
|
|
+ {
|
|
+ .virtual = IO_ADDRESS(USB_BASE),
|
|
+ .pfn = __phys_to_pfn(USB_BASE),
|
|
+ .length = SZ_128K,
|
|
+ .type = MT_DEVICE},
|
|
+ {
|
|
+ .virtual = IO_ADDRESS(PM_BASE),
|
|
+ .pfn = __phys_to_pfn(PM_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE},
|
|
+ {
|
|
+ .virtual = IO_ADDRESS(GPIO_BASE),
|
|
+ .pfn = __phys_to_pfn(GPIO_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE},
|
|
+ {
|
|
+ .virtual = IO_ADDRESS(ARM_LOCAL_BASE),
|
|
+ .pfn = __phys_to_pfn(ARM_LOCAL_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE},
|
|
+};
|
|
+
|
|
+void __init bcm2709_map_io(void)
|
|
+{
|
|
+ iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc));
|
|
+}
|
|
+
|
|
+int calc_rsts(int partition)
|
|
+{
|
|
+ return PM_PASSWORD |
|
|
+ ((partition & (1 << 0)) << 0) |
|
|
+ ((partition & (1 << 1)) << 1) |
|
|
+ ((partition & (1 << 2)) << 2) |
|
|
+ ((partition & (1 << 3)) << 3) |
|
|
+ ((partition & (1 << 4)) << 4) |
|
|
+ ((partition & (1 << 5)) << 5);
|
|
+}
|
|
+
|
|
+static void bcm2709_restart(enum reboot_mode mode, const char *cmd)
|
|
+{
|
|
+ extern char bcm2708_reboot_mode;
|
|
+ uint32_t pm_rstc, pm_wdog;
|
|
+ uint32_t timeout = 10;
|
|
+ uint32_t pm_rsts = 0;
|
|
+
|
|
+ if(bcm2708_reboot_mode == 'q')
|
|
+ {
|
|
+ // NOOBS < 1.3 booting with reboot=q
|
|
+ pm_rsts = readl(__io_address(PM_RSTS));
|
|
+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
|
|
+ }
|
|
+ else if(bcm2708_reboot_mode == 'p')
|
|
+ {
|
|
+ // NOOBS < 1.3 halting
|
|
+ pm_rsts = readl(__io_address(PM_RSTS));
|
|
+ pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
|
|
+ }
|
|
+ else
|
|
+ {
|
|
+ pm_rsts = calc_rsts(reboot_part);
|
|
+ }
|
|
+
|
|
+ writel(pm_rsts, __io_address(PM_RSTS));
|
|
+
|
|
+ /* Setup watchdog for reset */
|
|
+ pm_rstc = readl(__io_address(PM_RSTC));
|
|
+
|
|
+ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
|
|
+ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
|
|
+
|
|
+ writel(pm_wdog, __io_address(PM_WDOG));
|
|
+ writel(pm_rstc, __io_address(PM_RSTC));
|
|
+}
|
|
+
|
|
+/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
|
|
+static void bcm2709_power_off(void)
|
|
+{
|
|
+ extern char bcm2708_reboot_mode;
|
|
+ if(bcm2708_reboot_mode == 'q')
|
|
+ {
|
|
+ // NOOBS < v1.3
|
|
+ bcm2709_restart('p', "");
|
|
+ }
|
|
+ else
|
|
+ {
|
|
+ /* partition 63 is special code for HALT the bootloader knows not to boot*/
|
|
+ reboot_part = 63;
|
|
+ /* continue with normal reset mechanism */
|
|
+ bcm2709_restart(0, "");
|
|
+ }
|
|
+}
|
|
+
|
|
+static void __init bcm2709_init_uart1(void)
|
|
+{
|
|
+ struct device_node *np;
|
|
+
|
|
+ np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart");
|
|
+ if (of_device_is_available(np)) {
|
|
+ pr_info("bcm2709: Mini UART enabled\n");
|
|
+ writel(1, __io_address(UART1_BASE + 0x4));
|
|
+ }
|
|
+}
|
|
+
|
|
+void __init bcm2709_init(void)
|
|
+{
|
|
+ int ret;
|
|
+
|
|
+ vc_cma_early_init();
|
|
+
|
|
+ pm_power_off = bcm2709_power_off;
|
|
+
|
|
+ ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
|
|
+ NULL);
|
|
+ if (ret) {
|
|
+ pr_err("of_platform_populate failed: %d\n", ret);
|
|
+ BUG();
|
|
+ }
|
|
+
|
|
+ bcm2709_init_uart1();
|
|
+
|
|
+ system_rev = boardrev;
|
|
+ system_serial_low = serial;
|
|
+}
|
|
+
|
|
+static void __init bcm2709_timer_init(void)
|
|
+{
|
|
+ // timer control
|
|
+ writel(0, __io_address(ARM_LOCAL_CONTROL));
|
|
+ // timer pre_scaler
|
|
+ writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz
|
|
+ //writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz
|
|
+
|
|
+ of_clk_init(NULL);
|
|
+ clocksource_probe();
|
|
+}
|
|
+
|
|
+
|
|
+void __init bcm2709_init_early(void)
|
|
+{
|
|
+ /*
|
|
+ * Some devices allocate their coherent buffers from atomic
|
|
+ * context. Increase size of atomic coherent pool to make sure such
|
|
+ * the allocations won't fail.
|
|
+ */
|
|
+ init_dma_coherent_pool_size(SZ_4M);
|
|
+}
|
|
+
|
|
+static void __init board_reserve(void)
|
|
+{
|
|
+ vc_cma_reserve();
|
|
+}
|
|
+
|
|
+
|
|
+#ifdef CONFIG_SMP
|
|
+#include <linux/smp.h>
|
|
+
|
|
+#include <asm/cacheflush.h>
|
|
+#include <asm/smp_plat.h>
|
|
+int dc4=0;
|
|
+//void dc4_log(unsigned x) { if (dc4) writel((x), __io_address(ST_BASE+10 + raw_smp_processor_id()*4)); }
|
|
+void dc4_log_dead(unsigned x) { if (dc4) writel((readl(__io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)) & 0xffff) | ((x)<<16), __io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)); }
|
|
+
|
|
+static void bcm2835_send_doorbell(const struct cpumask *mask, unsigned int irq)
|
|
+{
|
|
+ int cpu;
|
|
+ /*
|
|
+ * Ensure that stores to Normal memory are visible to the
|
|
+ * other CPUs before issuing the IPI.
|
|
+ */
|
|
+ dsb();
|
|
+
|
|
+ /* Convert our logical CPU mask into a physical one. */
|
|
+ for_each_cpu(cpu, mask)
|
|
+ {
|
|
+ /* submit softirq */
|
|
+ writel(1<<irq, __io_address(ARM_LOCAL_MAILBOX0_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)));
|
|
+ }
|
|
+}
|
|
+
|
|
+void __init bcm2709_smp_init_cpus(void)
|
|
+{
|
|
+ void secondary_startup(void);
|
|
+ unsigned int i, ncores;
|
|
+
|
|
+ ncores = 4; // xxx scu_get_core_count(NULL);
|
|
+ printk("[%s] enter (%x->%x)\n", __FUNCTION__, (unsigned)virt_to_phys((void *)secondary_startup), (unsigned)__io_address(ST_BASE + 0x10));
|
|
+ printk("[%s] ncores=%d\n", __FUNCTION__, ncores);
|
|
+
|
|
+ for (i = 0; i < ncores; i++) {
|
|
+ set_cpu_possible(i, true);
|
|
+ /* enable IRQ (not FIQ) */
|
|
+ writel(0x1, __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 0x4 * i));
|
|
+ //writel(0xf, __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 0x4 * i));
|
|
+ }
|
|
+ set_smp_cross_call(bcm2835_send_doorbell);
|
|
+}
|
|
+
|
|
+/*
|
|
+ * for arch/arm/kernel/smp.c:smp_prepare_cpus(unsigned int max_cpus)
|
|
+ */
|
|
+void __init bcm2709_smp_prepare_cpus(unsigned int max_cpus)
|
|
+{
|
|
+ //void __iomem *scu_base;
|
|
+
|
|
+ printk("[%s] enter\n", __FUNCTION__);
|
|
+ //scu_base = scu_base_addr();
|
|
+ //scu_enable(scu_base);
|
|
+}
|
|
+
|
|
+/*
|
|
+ * for linux/arch/arm/kernel/smp.c:secondary_start_kernel(void)
|
|
+ */
|
|
+void __init bcm2709_secondary_init(unsigned int cpu)
|
|
+{
|
|
+ printk("[%s] enter cpu:%d\n", __FUNCTION__, cpu);
|
|
+ //gic_secondary_init(0);
|
|
+}
|
|
+
|
|
+/*
|
|
+ * for linux/arch/arm/kernel/smp.c:__cpu_up(..)
|
|
+ */
|
|
+int __init bcm2709_boot_secondary(unsigned int cpu, struct task_struct *idle)
|
|
+{
|
|
+ void secondary_startup(void);
|
|
+ void *mbox_set = __io_address(ARM_LOCAL_MAILBOX3_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
|
|
+ void *mbox_clr = __io_address(ARM_LOCAL_MAILBOX3_CLR0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
|
|
+ unsigned secondary_boot = (unsigned)virt_to_phys((void *)secondary_startup);
|
|
+ int timeout=20;
|
|
+ unsigned t = -1;
|
|
+ //printk("[%s] enter cpu:%d (%x->%p) %x\n", __FUNCTION__, cpu, secondary_boot, wake, readl(wake));
|
|
+
|
|
+ dsb();
|
|
+ BUG_ON(readl(mbox_clr) != 0);
|
|
+ writel(secondary_boot, mbox_set);
|
|
+
|
|
+ while (--timeout > 0) {
|
|
+ t = readl(mbox_clr);
|
|
+ if (t == 0) break;
|
|
+ cpu_relax();
|
|
+ }
|
|
+ if (timeout==0)
|
|
+ printk("[%s] cpu:%d failed to start (%x)\n", __FUNCTION__, cpu, t);
|
|
+ else
|
|
+ printk("[%s] cpu:%d started (%x) %d\n", __FUNCTION__, cpu, t, timeout);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+
|
|
+struct smp_operations bcm2709_smp_ops __initdata = {
|
|
+ .smp_init_cpus = bcm2709_smp_init_cpus,
|
|
+ .smp_prepare_cpus = bcm2709_smp_prepare_cpus,
|
|
+ .smp_secondary_init = bcm2709_secondary_init,
|
|
+ .smp_boot_secondary = bcm2709_boot_secondary,
|
|
+};
|
|
+#endif
|
|
+
|
|
+static const char * const bcm2709_compat[] = {
|
|
+ "brcm,bcm2709",
|
|
+ "brcm,bcm2708", /* Could use bcm2708 in a pinch */
|
|
+ NULL
|
|
+};
|
|
+
|
|
+MACHINE_START(BCM2709, "BCM2709")
|
|
+ /* Maintainer: Broadcom Europe Ltd. */
|
|
+#ifdef CONFIG_SMP
|
|
+ .smp = smp_ops(bcm2709_smp_ops),
|
|
+#endif
|
|
+ .map_io = bcm2709_map_io,
|
|
+ .init_time = bcm2709_timer_init,
|
|
+ .init_machine = bcm2709_init,
|
|
+ .init_early = bcm2709_init_early,
|
|
+ .reserve = board_reserve,
|
|
+ .restart = bcm2709_restart,
|
|
+ .dt_compat = bcm2709_compat,
|
|
+MACHINE_END
|
|
+
|
|
+MACHINE_START(BCM2708, "BCM2709")
|
|
+ /* Maintainer: Broadcom Europe Ltd. */
|
|
+#ifdef CONFIG_SMP
|
|
+ .smp = smp_ops(bcm2709_smp_ops),
|
|
+#endif
|
|
+ .map_io = bcm2709_map_io,
|
|
+ .init_time = bcm2709_timer_init,
|
|
+ .init_machine = bcm2709_init,
|
|
+ .init_early = bcm2709_init_early,
|
|
+ .reserve = board_reserve,
|
|
+ .restart = bcm2709_restart,
|
|
+ .dt_compat = bcm2709_compat,
|
|
+MACHINE_END
|
|
+
|
|
+module_param(boardrev, uint, 0644);
|
|
+module_param(serial, uint, 0644);
|
|
+module_param(reboot_part, uint, 0644);
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/include/mach/debug-macro.S
|
|
@@ -0,0 +1,22 @@
|
|
+/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
|
|
+ *
|
|
+ * Debugging macro include header
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ * Copyright (C) 1994-1999 Russell King
|
|
+ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License version 2 as
|
|
+ * published by the Free Software Foundation.
|
|
+ *
|
|
+*/
|
|
+
|
|
+#include <mach/platform.h>
|
|
+
|
|
+ .macro addruart, rp, rv, tmp
|
|
+ ldr \rp, =UART0_BASE
|
|
+ ldr \rv, =IO_ADDRESS(UART0_BASE)
|
|
+ .endm
|
|
+
|
|
+#include <debug/pl01x.S>
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S
|
|
@@ -0,0 +1,123 @@
|
|
+/*
|
|
+ * arch/arm/mach-bcm2708/include/mach/entry-macro.S
|
|
+ *
|
|
+ * Low-level IRQ helper macros for BCM2708 platforms
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+#include <mach/hardware.h>
|
|
+#include <mach/irqs.h>
|
|
+
|
|
+ .macro disable_fiq
|
|
+ .endm
|
|
+
|
|
+ .macro get_irqnr_preamble, base, tmp
|
|
+ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
|
|
+ .endm
|
|
+
|
|
+ .macro arch_ret_to_user, tmp1, tmp2
|
|
+ .endm
|
|
+
|
|
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
|
+ /* get core number */
|
|
+ mrc p15, 0, \tmp, c0, c0, 5
|
|
+ ubfx \tmp, \tmp, #0, #2
|
|
+
|
|
+ /* get core's local interrupt controller */
|
|
+ ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
|
|
+ add \irqstat, \irqstat, \tmp, lsl #2
|
|
+ ldr \tmp, [\irqstat]
|
|
+ /* ignore gpu interrupt */
|
|
+ bic \tmp, #0x100
|
|
+ /* ignore mailbox interrupts */
|
|
+ bics \tmp, #0xf0
|
|
+ beq 1005f
|
|
+
|
|
+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
|
|
+ @ N.B. CLZ is an ARM5 instruction.
|
|
+ mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
|
|
+ sub \irqstat, \tmp, #1
|
|
+ eor \irqstat, \irqstat, \tmp
|
|
+ clz \tmp, \irqstat
|
|
+ sub \irqnr, \tmp
|
|
+ b 1020f
|
|
+1005:
|
|
+ /* get core number */
|
|
+ mrc p15, 0, \tmp, c0, c0, 5
|
|
+ ubfx \tmp, \tmp, #0, #2
|
|
+
|
|
+ cmp \tmp, #1
|
|
+ beq 1020f
|
|
+ cmp \tmp, #2
|
|
+ beq 1020f
|
|
+ cmp \tmp, #3
|
|
+ beq 1020f
|
|
+
|
|
+ /* get masked status */
|
|
+ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
|
|
+ mov \irqnr, #(ARM_IRQ0_BASE + 31)
|
|
+ and \tmp, \irqstat, #0x300 @ save bits 8 and 9
|
|
+ /* clear bits 8 and 9, and test */
|
|
+ bics \irqstat, \irqstat, #0x300
|
|
+ bne 1010f
|
|
+
|
|
+ tst \tmp, #0x100
|
|
+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
|
|
+ movne \irqnr, #(ARM_IRQ1_BASE + 31)
|
|
+ @ Mask out the interrupts also present in PEND0 - see SW-5809
|
|
+ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
|
|
+ bicne \irqstat, #((1<<18) | (1<<19))
|
|
+ bne 1010f
|
|
+
|
|
+ tst \tmp, #0x200
|
|
+ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
|
|
+ movne \irqnr, #(ARM_IRQ2_BASE + 31)
|
|
+ @ Mask out the interrupts also present in PEND0 - see SW-5809
|
|
+ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
|
|
+ bicne \irqstat, #((1<<30))
|
|
+ beq 1020f
|
|
+
|
|
+1010:
|
|
+ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
|
|
+ @ N.B. CLZ is an ARM5 instruction.
|
|
+ sub \tmp, \irqstat, #1
|
|
+ eor \irqstat, \irqstat, \tmp
|
|
+ clz \tmp, \irqstat
|
|
+ sub \irqnr, \tmp
|
|
+
|
|
+1020: @ EQ will be set if no irqs pending
|
|
+
|
|
+ .endm
|
|
+
|
|
+ .macro test_for_ipi, irqnr, irqstat, base, tmp
|
|
+ /* get core number */
|
|
+ mrc p15, 0, \tmp, c0, c0, 5
|
|
+ ubfx \tmp, \tmp, #0, #2
|
|
+ /* get core's mailbox interrupt control */
|
|
+ ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
|
|
+ add \irqstat, \irqstat, \tmp, lsl #4
|
|
+ ldr \tmp, [\irqstat]
|
|
+ cmp \tmp, #0
|
|
+ beq 1030f
|
|
+ clz \tmp, \tmp
|
|
+ rsb \irqnr, \tmp, #31
|
|
+ mov \tmp, #1
|
|
+ lsl \tmp, \irqnr
|
|
+ str \tmp, [\irqstat] @ clear interrupt source
|
|
+ dsb
|
|
+1030: @ EQ will be set if no irqs pending
|
|
+ .endm
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/include/mach/io.h
|
|
@@ -0,0 +1,27 @@
|
|
+/*
|
|
+ * arch/arm/mach-bcm2708/include/mach/io.h
|
|
+ *
|
|
+ * Copyright (C) 2003 ARM Limited
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+#ifndef __ASM_ARM_ARCH_IO_H
|
|
+#define __ASM_ARM_ARCH_IO_H
|
|
+
|
|
+#define IO_SPACE_LIMIT 0xffffffff
|
|
+
|
|
+#define __io(a) __typesafe_io(a)
|
|
+
|
|
+#endif
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/include/mach/memory.h
|
|
@@ -0,0 +1,57 @@
|
|
+/*
|
|
+ * arch/arm/mach-bcm2708/include/mach/memory.h
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+#ifndef __ASM_ARCH_MEMORY_H
|
|
+#define __ASM_ARCH_MEMORY_H
|
|
+
|
|
+/* Memory overview:
|
|
+
|
|
+ [ARMcore] <--virtual addr-->
|
|
+ [ARMmmu] <--physical addr-->
|
|
+ [GERTmap] <--bus add-->
|
|
+ [VCperiph]
|
|
+
|
|
+*/
|
|
+
|
|
+/*
|
|
+ * Physical DRAM offset.
|
|
+ */
|
|
+#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
|
|
+#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
|
|
+
|
|
+#ifdef CONFIG_BCM2708_NOL2CACHE
|
|
+ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
|
|
+#else
|
|
+ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
|
|
+#endif
|
|
+
|
|
+/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
|
|
+ * will provide the offset into this area as well as setting the bits that
|
|
+ * stop the L1 and L2 cache from being used
|
|
+ *
|
|
+ * WARNING: this only works because the ARM is given memory at a fixed location
|
|
+ * (ARMMEM_OFFSET)
|
|
+ */
|
|
+#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
|
|
+#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
|
|
+#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
|
|
+#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
|
|
+#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
|
|
+
|
|
+#endif
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/include/mach/platform.h
|
|
@@ -0,0 +1,188 @@
|
|
+/*
|
|
+ * arch/arm/mach-bcm2708/include/mach/platform.h
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+
|
|
+#ifndef _BCM2708_PLATFORM_H
|
|
+#define _BCM2708_PLATFORM_H
|
|
+
|
|
+
|
|
+/* macros to get at IO space when running virtually */
|
|
+#define IO_ADDRESS(x) (((x) & 0x00ffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
|
|
+
|
|
+#define __io_address(n) IOMEM(IO_ADDRESS(n))
|
|
+
|
|
+
|
|
+/*
|
|
+ * SDRAM
|
|
+ */
|
|
+#define BCM2708_SDRAM_BASE 0x00000000
|
|
+
|
|
+/*
|
|
+ * Logic expansion modules
|
|
+ *
|
|
+ */
|
|
+
|
|
+
|
|
+/* ------------------------------------------------------------------------
|
|
+ * BCM2708 ARMCTRL Registers
|
|
+ * ------------------------------------------------------------------------
|
|
+ */
|
|
+
|
|
+#define HW_REGISTER_RW(addr) (addr)
|
|
+#define HW_REGISTER_RO(addr) (addr)
|
|
+
|
|
+/*
|
|
+ * Definitions and addresses for the ARM CONTROL logic
|
|
+ * This file is manually generated.
|
|
+ */
|
|
+
|
|
+#define BCM2708_PERI_BASE 0x3F000000
|
|
+#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
|
|
+#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
|
|
+#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
|
|
+#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
|
|
+#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
|
|
+#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
|
|
+#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
|
|
+#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
|
|
+#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
|
|
+#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
|
|
+#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
|
|
+#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
|
|
+#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
|
|
+#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
|
|
+#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
|
|
+#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
|
|
+#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
|
|
+#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
|
|
+#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
|
|
+#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
|
|
+
|
|
+#define ARMCTRL_BASE (ARM_BASE + 0x000)
|
|
+#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
|
|
+#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
|
|
+#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
|
|
+
|
|
+/*
|
|
+ * Watchdog
|
|
+ */
|
|
+#define PM_RSTC (PM_BASE+0x1c)
|
|
+#define PM_RSTS (PM_BASE+0x20)
|
|
+#define PM_WDOG (PM_BASE+0x24)
|
|
+
|
|
+#define PM_WDOG_RESET 0000000000
|
|
+#define PM_PASSWORD 0x5a000000
|
|
+#define PM_WDOG_TIME_SET 0x000fffff
|
|
+#define PM_RSTC_WRCFG_CLR 0xffffffcf
|
|
+#define PM_RSTC_WRCFG_SET 0x00000030
|
|
+#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
|
|
+#define PM_RSTC_RESET 0x00000102
|
|
+
|
|
+#define PM_RSTS_HADPOR_SET 0x00001000
|
|
+#define PM_RSTS_HADSRH_SET 0x00000400
|
|
+#define PM_RSTS_HADSRF_SET 0x00000200
|
|
+#define PM_RSTS_HADSRQ_SET 0x00000100
|
|
+#define PM_RSTS_HADWRH_SET 0x00000040
|
|
+#define PM_RSTS_HADWRF_SET 0x00000020
|
|
+#define PM_RSTS_HADWRQ_SET 0x00000010
|
|
+#define PM_RSTS_HADDRH_SET 0x00000004
|
|
+#define PM_RSTS_HADDRF_SET 0x00000002
|
|
+#define PM_RSTS_HADDRQ_SET 0x00000001
|
|
+
|
|
+#define UART0_CLOCK 3000000
|
|
+
|
|
+#define ARM_LOCAL_BASE 0x40000000
|
|
+#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000)
|
|
+
|
|
+#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000)
|
|
+#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008)
|
|
+#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C)
|
|
+#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010)
|
|
+#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014)
|
|
+#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C)
|
|
+#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020)
|
|
+#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024)
|
|
+#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C)
|
|
+#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030)
|
|
+#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034)
|
|
+#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038)
|
|
+
|
|
+#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040)
|
|
+#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044)
|
|
+#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048)
|
|
+#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C)
|
|
+
|
|
+#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050)
|
|
+#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054)
|
|
+#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058)
|
|
+#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C)
|
|
+
|
|
+#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060)
|
|
+#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064)
|
|
+#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068)
|
|
+#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C)
|
|
+
|
|
+#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070)
|
|
+#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074)
|
|
+#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078)
|
|
+#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C)
|
|
+
|
|
+#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080)
|
|
+#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084)
|
|
+#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088)
|
|
+#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C)
|
|
+
|
|
+#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090)
|
|
+#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094)
|
|
+#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098)
|
|
+#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C)
|
|
+
|
|
+#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0)
|
|
+#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4)
|
|
+#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8)
|
|
+#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC)
|
|
+
|
|
+#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0)
|
|
+#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4)
|
|
+#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8)
|
|
+#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC)
|
|
+
|
|
+#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0)
|
|
+#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4)
|
|
+#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8)
|
|
+#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC)
|
|
+
|
|
+#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0)
|
|
+#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4)
|
|
+#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8)
|
|
+#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC)
|
|
+
|
|
+#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0)
|
|
+#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4)
|
|
+#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8)
|
|
+#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC)
|
|
+
|
|
+#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0)
|
|
+#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4)
|
|
+#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8)
|
|
+#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC)
|
|
+
|
|
+#endif
|
|
+
|
|
+/* END */
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/include/mach/system.h
|
|
@@ -0,0 +1,37 @@
|
|
+/*
|
|
+ * arch/arm/mach-bcm2708/include/mach/system.h
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ * Copyright (C) 2003 ARM Limited
|
|
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+#ifndef __ASM_ARCH_SYSTEM_H
|
|
+#define __ASM_ARCH_SYSTEM_H
|
|
+
|
|
+#include <linux/io.h>
|
|
+#include <mach/platform.h>
|
|
+
|
|
+static inline void arch_idle(void)
|
|
+{
|
|
+ /*
|
|
+ * This should do all the clock switching
|
|
+ * and wait for interrupt tricks
|
|
+ */
|
|
+ cpu_do_idle();
|
|
+}
|
|
+
|
|
+#endif
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/include/mach/uncompress.h
|
|
@@ -0,0 +1,84 @@
|
|
+/*
|
|
+ * arch/arm/mach-bcn2708/include/mach/uncompress.h
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ * Copyright (C) 2003 ARM Limited
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+
|
|
+#include <linux/io.h>
|
|
+#include <linux/amba/serial.h>
|
|
+#include <mach/platform.h>
|
|
+
|
|
+#define UART_BAUD 115200
|
|
+
|
|
+#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
|
|
+#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
|
|
+#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
|
|
+#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
|
|
+#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
|
|
+#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
|
|
+
|
|
+/*
|
|
+ * This does not append a newline
|
|
+ */
|
|
+static inline void putc(int c)
|
|
+{
|
|
+ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
|
|
+ barrier();
|
|
+
|
|
+ __raw_writel(c, BCM2708_UART_DR);
|
|
+}
|
|
+
|
|
+static inline void flush(void)
|
|
+{
|
|
+ int fr;
|
|
+
|
|
+ do {
|
|
+ fr = __raw_readl(BCM2708_UART_FR);
|
|
+ barrier();
|
|
+ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
|
|
+}
|
|
+
|
|
+static inline void arch_decomp_setup(void)
|
|
+{
|
|
+ int temp, div, rem, frac;
|
|
+
|
|
+ temp = 16 * UART_BAUD;
|
|
+ div = UART0_CLOCK / temp;
|
|
+ rem = UART0_CLOCK % temp;
|
|
+ temp = (8 * rem) / UART_BAUD;
|
|
+ frac = (temp >> 1) + (temp & 1);
|
|
+
|
|
+ /* Make sure the UART is disabled before we start */
|
|
+ __raw_writel(0, BCM2708_UART_CR);
|
|
+
|
|
+ /* Set the baud rate */
|
|
+ __raw_writel(div, BCM2708_UART_IBRD);
|
|
+ __raw_writel(frac, BCM2708_UART_FBRD);
|
|
+
|
|
+ /* Set the UART to 8n1, FIFO enabled */
|
|
+ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
|
|
+
|
|
+ /* Enable the UART */
|
|
+ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
|
|
+ BCM2708_UART_CR);
|
|
+}
|
|
+
|
|
+/*
|
|
+ * nothing to do
|
|
+ */
|
|
+#define arch_decomp_wdog()
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/include/mach/vc_mem.h
|
|
@@ -0,0 +1,35 @@
|
|
+/*****************************************************************************
|
|
+* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
|
|
+*
|
|
+* Unless you and Broadcom execute a separate written software license
|
|
+* agreement governing use of this software, this software is licensed to you
|
|
+* under the terms of the GNU General Public License version 2, available at
|
|
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
|
|
+*
|
|
+* Notwithstanding the above, under no circumstances may you combine this
|
|
+* software in any way with any other Broadcom software provided under a
|
|
+* license other than the GPL, without Broadcom's express prior written
|
|
+* consent.
|
|
+*****************************************************************************/
|
|
+
|
|
+#if !defined( VC_MEM_H )
|
|
+#define VC_MEM_H
|
|
+
|
|
+#include <linux/ioctl.h>
|
|
+
|
|
+#define VC_MEM_IOC_MAGIC 'v'
|
|
+
|
|
+#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
|
|
+#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
|
|
+#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
|
|
+#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
|
|
+
|
|
+#if defined( __KERNEL__ )
|
|
+#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
|
|
+
|
|
+extern unsigned long mm_vc_mem_phys_addr;
|
|
+extern unsigned int mm_vc_mem_size;
|
|
+extern int vc_mem_get_current_size( void );
|
|
+#endif
|
|
+
|
|
+#endif /* VC_MEM_H */
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/include/mach/vmalloc.h
|
|
@@ -0,0 +1,20 @@
|
|
+/*
|
|
+ * arch/arm/mach-bcm2708/include/mach/vmalloc.h
|
|
+ *
|
|
+ * Copyright (C) 2010 Broadcom
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ */
|
|
+#define VMALLOC_END (0xff000000)
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-bcm2709/vc_mem.c
|
|
@@ -0,0 +1,431 @@
|
|
+/*****************************************************************************
|
|
+* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
|
|
+*
|
|
+* Unless you and Broadcom execute a separate written software license
|
|
+* agreement governing use of this software, this software is licensed to you
|
|
+* under the terms of the GNU General Public License version 2, available at
|
|
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
|
|
+*
|
|
+* Notwithstanding the above, under no circumstances may you combine this
|
|
+* software in any way with any other Broadcom software provided under a
|
|
+* license other than the GPL, without Broadcom's express prior written
|
|
+* consent.
|
|
+*****************************************************************************/
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/module.h>
|
|
+#include <linux/fs.h>
|
|
+#include <linux/device.h>
|
|
+#include <linux/cdev.h>
|
|
+#include <linux/mm.h>
|
|
+#include <linux/slab.h>
|
|
+#include <linux/debugfs.h>
|
|
+#include <asm/uaccess.h>
|
|
+#include <linux/dma-mapping.h>
|
|
+#include <linux/platform_data/mailbox-bcm2708.h>
|
|
+
|
|
+#ifdef CONFIG_ARCH_KONA
|
|
+#include <chal/chal_ipc.h>
|
|
+#elif defined(CONFIG_ARCH_BCM2708) || defined(CONFIG_ARCH_BCM2709)
|
|
+#else
|
|
+#include <csp/chal_ipc.h>
|
|
+#endif
|
|
+
|
|
+#include "mach/vc_mem.h"
|
|
+
|
|
+#define DRIVER_NAME "vc-mem"
|
|
+
|
|
+// Device (/dev) related variables
|
|
+static dev_t vc_mem_devnum = 0;
|
|
+static struct class *vc_mem_class = NULL;
|
|
+static struct cdev vc_mem_cdev;
|
|
+static int vc_mem_inited = 0;
|
|
+
|
|
+#ifdef CONFIG_DEBUG_FS
|
|
+static struct dentry *vc_mem_debugfs_entry;
|
|
+#endif
|
|
+
|
|
+/*
|
|
+ * Videocore memory addresses and size
|
|
+ *
|
|
+ * Drivers that wish to know the videocore memory addresses and sizes should
|
|
+ * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
|
|
+ * headers. This allows the other drivers to not be tied down to a a certain
|
|
+ * address/size at compile time.
|
|
+ *
|
|
+ * In the future, the goal is to have the videocore memory virtual address and
|
|
+ * size be calculated at boot time rather than at compile time. The decision of
|
|
+ * where the videocore memory resides and its size would be in the hands of the
|
|
+ * bootloader (and/or kernel). When that happens, the values of these variables
|
|
+ * would be calculated and assigned in the init function.
|
|
+ */
|
|
+// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
|
|
+unsigned long mm_vc_mem_phys_addr = 0x00000000;
|
|
+unsigned int mm_vc_mem_size = 0;
|
|
+unsigned int mm_vc_mem_base = 0;
|
|
+
|
|
+EXPORT_SYMBOL(mm_vc_mem_phys_addr);
|
|
+EXPORT_SYMBOL(mm_vc_mem_size);
|
|
+EXPORT_SYMBOL(mm_vc_mem_base);
|
|
+
|
|
+static uint phys_addr = 0;
|
|
+static uint mem_size = 0;
|
|
+static uint mem_base = 0;
|
|
+
|
|
+
|
|
+/****************************************************************************
|
|
+*
|
|
+* vc_mem_open
|
|
+*
|
|
+***************************************************************************/
|
|
+
|
|
+static int
|
|
+vc_mem_open(struct inode *inode, struct file *file)
|
|
+{
|
|
+ (void) inode;
|
|
+ (void) file;
|
|
+
|
|
+ pr_debug("%s: called file = 0x%p\n", __func__, file);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/****************************************************************************
|
|
+*
|
|
+* vc_mem_release
|
|
+*
|
|
+***************************************************************************/
|
|
+
|
|
+static int
|
|
+vc_mem_release(struct inode *inode, struct file *file)
|
|
+{
|
|
+ (void) inode;
|
|
+ (void) file;
|
|
+
|
|
+ pr_debug("%s: called file = 0x%p\n", __func__, file);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+/****************************************************************************
|
|
+*
|
|
+* vc_mem_get_size
|
|
+*
|
|
+***************************************************************************/
|
|
+
|
|
+static void
|
|
+vc_mem_get_size(void)
|
|
+{
|
|
+}
|
|
+
|
|
+/****************************************************************************
|
|
+*
|
|
+* vc_mem_get_base
|
|
+*
|
|
+***************************************************************************/
|
|
+
|
|
+static void
|
|
+vc_mem_get_base(void)
|
|
+{
|
|
+}
|
|
+
|
|
+/****************************************************************************
|
|
+*
|
|
+* vc_mem_get_current_size
|
|
+*
|
|
+***************************************************************************/
|
|
+
|
|
+int
|
|
+vc_mem_get_current_size(void)
|
|
+{
|
|
+ return mm_vc_mem_size;
|
|
+}
|
|
+
|
|
+EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
|
|
+
|
|
+/****************************************************************************
|
|
+*
|
|
+* vc_mem_ioctl
|
|
+*
|
|
+***************************************************************************/
|
|
+
|
|
+static long
|
|
+vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
|
+{
|
|
+ int rc = 0;
|
|
+
|
|
+ (void) cmd;
|
|
+ (void) arg;
|
|
+
|
|
+ pr_debug("%s: called file = 0x%p\n", __func__, file);
|
|
+
|
|
+ switch (cmd) {
|
|
+ case VC_MEM_IOC_MEM_PHYS_ADDR:
|
|
+ {
|
|
+ pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
|
|
+ __func__, (void *) mm_vc_mem_phys_addr);
|
|
+
|
|
+ if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
|
|
+ sizeof (mm_vc_mem_phys_addr)) != 0) {
|
|
+ rc = -EFAULT;
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+ case VC_MEM_IOC_MEM_SIZE:
|
|
+ {
|
|
+ // Get the videocore memory size first
|
|
+ vc_mem_get_size();
|
|
+
|
|
+ pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
|
|
+ mm_vc_mem_size);
|
|
+
|
|
+ if (copy_to_user((void *) arg, &mm_vc_mem_size,
|
|
+ sizeof (mm_vc_mem_size)) != 0) {
|
|
+ rc = -EFAULT;
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+ case VC_MEM_IOC_MEM_BASE:
|
|
+ {
|
|
+ // Get the videocore memory base
|
|
+ vc_mem_get_base();
|
|
+
|
|
+ pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
|
|
+ mm_vc_mem_base);
|
|
+
|
|
+ if (copy_to_user((void *) arg, &mm_vc_mem_base,
|
|
+ sizeof (mm_vc_mem_base)) != 0) {
|
|
+ rc = -EFAULT;
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+ case VC_MEM_IOC_MEM_LOAD:
|
|
+ {
|
|
+ // Get the videocore memory base
|
|
+ vc_mem_get_base();
|
|
+
|
|
+ pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
|
|
+ mm_vc_mem_base);
|
|
+
|
|
+ if (copy_to_user((void *) arg, &mm_vc_mem_base,
|
|
+ sizeof (mm_vc_mem_base)) != 0) {
|
|
+ rc = -EFAULT;
|
|
+ }
|
|
+ break;
|
|
+ }
|
|
+ default:
|
|
+ {
|
|
+ return -ENOTTY;
|
|
+ }
|
|
+ }
|
|
+ pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
|
|
+
|
|
+ return rc;
|
|
+}
|
|
+
|
|
+/****************************************************************************
|
|
+*
|
|
+* vc_mem_mmap
|
|
+*
|
|
+***************************************************************************/
|
|
+
|
|
+static int
|
|
+vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
|
|
+{
|
|
+ int rc = 0;
|
|
+ unsigned long length = vma->vm_end - vma->vm_start;
|
|
+ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
|
|
+
|
|
+ pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
|
|
+ __func__, (long) vma->vm_start, (long) vma->vm_end,
|
|
+ (long) vma->vm_pgoff);
|
|
+
|
|
+ if (offset + length > mm_vc_mem_size) {
|
|
+ pr_err("%s: length %ld is too big\n", __func__, length);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+ // Do not cache the memory map
|
|
+ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
|
|
+
|
|
+ rc = remap_pfn_range(vma, vma->vm_start,
|
|
+ (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
|
|
+ vma->vm_pgoff, length, vma->vm_page_prot);
|
|
+ if (rc != 0) {
|
|
+ pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
|
|
+ }
|
|
+
|
|
+ return rc;
|
|
+}
|
|
+
|
|
+/****************************************************************************
|
|
+*
|
|
+* File Operations for the driver.
|
|
+*
|
|
+***************************************************************************/
|
|
+
|
|
+static const struct file_operations vc_mem_fops = {
|
|
+ .owner = THIS_MODULE,
|
|
+ .open = vc_mem_open,
|
|
+ .release = vc_mem_release,
|
|
+ .unlocked_ioctl = vc_mem_ioctl,
|
|
+ .mmap = vc_mem_mmap,
|
|
+};
|
|
+
|
|
+#ifdef CONFIG_DEBUG_FS
|
|
+static void vc_mem_debugfs_deinit(void)
|
|
+{
|
|
+ debugfs_remove_recursive(vc_mem_debugfs_entry);
|
|
+ vc_mem_debugfs_entry = NULL;
|
|
+}
|
|
+
|
|
+
|
|
+static int vc_mem_debugfs_init(
|
|
+ struct device *dev)
|
|
+{
|
|
+ vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
|
|
+ if (!vc_mem_debugfs_entry) {
|
|
+ dev_warn(dev, "could not create debugfs entry\n");
|
|
+ return -EFAULT;
|
|
+ }
|
|
+
|
|
+ if (!debugfs_create_x32("vc_mem_phys_addr",
|
|
+ 0444,
|
|
+ vc_mem_debugfs_entry,
|
|
+ (u32 *)&mm_vc_mem_phys_addr)) {
|
|
+ dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
|
|
+ __func__);
|
|
+ goto fail;
|
|
+ }
|
|
+
|
|
+ if (!debugfs_create_x32("vc_mem_size",
|
|
+ 0444,
|
|
+ vc_mem_debugfs_entry,
|
|
+ (u32 *)&mm_vc_mem_size)) {
|
|
+ dev_warn(dev, "%s:could not create vc_mem_size entry\n",
|
|
+ __func__);
|
|
+ goto fail;
|
|
+ }
|
|
+
|
|
+ if (!debugfs_create_x32("vc_mem_base",
|
|
+ 0444,
|
|
+ vc_mem_debugfs_entry,
|
|
+ (u32 *)&mm_vc_mem_base)) {
|
|
+ dev_warn(dev, "%s:could not create vc_mem_base entry\n",
|
|
+ __func__);
|
|
+ goto fail;
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+
|
|
+fail:
|
|
+ vc_mem_debugfs_deinit();
|
|
+ return -EFAULT;
|
|
+}
|
|
+
|
|
+#endif /* CONFIG_DEBUG_FS */
|
|
+
|
|
+
|
|
+/****************************************************************************
|
|
+*
|
|
+* vc_mem_init
|
|
+*
|
|
+***************************************************************************/
|
|
+
|
|
+static int __init
|
|
+vc_mem_init(void)
|
|
+{
|
|
+ int rc = -EFAULT;
|
|
+ struct device *dev;
|
|
+
|
|
+ pr_debug("%s: called\n", __func__);
|
|
+
|
|
+ mm_vc_mem_phys_addr = phys_addr;
|
|
+ mm_vc_mem_size = mem_size;
|
|
+ mm_vc_mem_base = mem_base;
|
|
+
|
|
+ vc_mem_get_size();
|
|
+
|
|
+ pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
|
|
+ mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
|
|
+
|
|
+ if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
|
|
+ pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
|
|
+ __func__, rc);
|
|
+ goto out_err;
|
|
+ }
|
|
+
|
|
+ cdev_init(&vc_mem_cdev, &vc_mem_fops);
|
|
+ if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
|
|
+ pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
|
|
+ goto out_unregister;
|
|
+ }
|
|
+
|
|
+ vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
|
|
+ if (IS_ERR(vc_mem_class)) {
|
|
+ rc = PTR_ERR(vc_mem_class);
|
|
+ pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
|
|
+ goto out_cdev_del;
|
|
+ }
|
|
+
|
|
+ dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
|
|
+ DRIVER_NAME);
|
|
+ if (IS_ERR(dev)) {
|
|
+ rc = PTR_ERR(dev);
|
|
+ pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
|
|
+ goto out_class_destroy;
|
|
+ }
|
|
+
|
|
+#ifdef CONFIG_DEBUG_FS
|
|
+ /* don't fail if the debug entries cannot be created */
|
|
+ vc_mem_debugfs_init(dev);
|
|
+#endif
|
|
+
|
|
+ vc_mem_inited = 1;
|
|
+ return 0;
|
|
+
|
|
+ device_destroy(vc_mem_class, vc_mem_devnum);
|
|
+
|
|
+ out_class_destroy:
|
|
+ class_destroy(vc_mem_class);
|
|
+ vc_mem_class = NULL;
|
|
+
|
|
+ out_cdev_del:
|
|
+ cdev_del(&vc_mem_cdev);
|
|
+
|
|
+ out_unregister:
|
|
+ unregister_chrdev_region(vc_mem_devnum, 1);
|
|
+
|
|
+ out_err:
|
|
+ return -1;
|
|
+}
|
|
+
|
|
+/****************************************************************************
|
|
+*
|
|
+* vc_mem_exit
|
|
+*
|
|
+***************************************************************************/
|
|
+
|
|
+static void __exit
|
|
+vc_mem_exit(void)
|
|
+{
|
|
+ pr_debug("%s: called\n", __func__);
|
|
+
|
|
+ if (vc_mem_inited) {
|
|
+#if CONFIG_DEBUG_FS
|
|
+ vc_mem_debugfs_deinit();
|
|
+#endif
|
|
+ device_destroy(vc_mem_class, vc_mem_devnum);
|
|
+ class_destroy(vc_mem_class);
|
|
+ cdev_del(&vc_mem_cdev);
|
|
+ unregister_chrdev_region(vc_mem_devnum, 1);
|
|
+ }
|
|
+}
|
|
+
|
|
+module_init(vc_mem_init);
|
|
+module_exit(vc_mem_exit);
|
|
+MODULE_LICENSE("GPL");
|
|
+MODULE_AUTHOR("Broadcom Corporation");
|
|
+
|
|
+module_param(phys_addr, uint, 0644);
|
|
+module_param(mem_size, uint, 0644);
|
|
+module_param(mem_base, uint, 0644);
|
|
--- a/arch/arm/mm/Kconfig
|
|
+++ b/arch/arm/mm/Kconfig
|
|
@@ -358,7 +358,7 @@ config CPU_PJ4B
|
|
|
|
# ARMv6
|
|
config CPU_V6
|
|
- bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
|
|
+ bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708)
|
|
select CPU_32v6
|
|
select CPU_ABRT_EV6
|
|
select CPU_CACHE_V6
|
|
--- a/arch/arm/mm/proc-v6.S
|
|
+++ b/arch/arm/mm/proc-v6.S
|
|
@@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset)
|
|
*
|
|
* IRQs are already disabled.
|
|
*/
|
|
+
|
|
+/* See jira SW-5991 for details of this workaround */
|
|
ENTRY(cpu_v6_do_idle)
|
|
- mov r1, #0
|
|
- mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
|
|
- mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
|
|
+ .align 5
|
|
+ mov r1, #2
|
|
+1: subs r1, #1
|
|
+ nop
|
|
+ mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
|
|
+ mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt
|
|
+ nop
|
|
+ nop
|
|
+ nop
|
|
+ bne 1b
|
|
ret lr
|
|
|
|
ENTRY(cpu_v6_dcache_clean_area)
|
|
--- a/arch/arm/mm/proc-v7.S
|
|
+++ b/arch/arm/mm/proc-v7.S
|
|
@@ -480,6 +480,7 @@ __errata_finish:
|
|
orr r0, r0, r6 @ set them
|
|
THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
|
|
ret lr @ return to head.S:__ret
|
|
+ .space 256
|
|
ENDPROC(__v7_setup)
|
|
|
|
.align 2
|
|
--- a/arch/arm/tools/mach-types
|
|
+++ b/arch/arm/tools/mach-types
|
|
@@ -522,6 +522,8 @@ torbreck MACH_TORBRECK TORBRECK 3090
|
|
prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103
|
|
paz00 MACH_PAZ00 PAZ00 3128
|
|
acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
|
|
+bcm2708 MACH_BCM2708 BCM2708 3138
|
|
+bcm2709 MACH_BCM2709 BCM2709 3139
|
|
ag5evm MACH_AG5EVM AG5EVM 3189
|
|
ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
|
|
wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
|
|
--- a/drivers/clocksource/Makefile
|
|
+++ b/drivers/clocksource/Makefile
|
|
@@ -19,7 +19,7 @@ obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += noma
|
|
obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
|
|
obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
|
|
obj-$(CONFIG_ORION_TIMER) += time-orion.o
|
|
-obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
|
|
+obj-$(CONFIG_ARCH_BCM2835)$(CONFIG_ARCH_BCM2708) += bcm2835_timer.o
|
|
obj-$(CONFIG_ARCH_CLPS711X) += clps711x-timer.o
|
|
obj-$(CONFIG_ARCH_ATLAS7) += timer-atlas7.o
|
|
obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o
|
|
--- a/drivers/irqchip/Makefile
|
|
+++ b/drivers/irqchip/Makefile
|
|
@@ -2,6 +2,9 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o
|
|
|
|
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
|
|
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
|
|
+obj-$(CONFIG_ARCH_BCM2708) += irq-bcm2835.o
|
|
+obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2835.o
|
|
+obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2836.o
|
|
obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
|
|
obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
|
|
obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
|
|
--- a/include/linux/mmc/host.h
|
|
+++ b/include/linux/mmc/host.h
|
|
@@ -289,6 +289,7 @@ struct mmc_host {
|
|
#define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
|
|
#define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
|
|
#define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */
|
|
+#define MMC_CAP2_FORCE_MULTIBLOCK (1 << 31) /* Always use multiblock transfers */
|
|
|
|
mmc_pm_flag_t pm_caps; /* supported pm features */
|
|
|