mirror of https://github.com/hak5/openwrt.git
178 lines
5.9 KiB
Diff
178 lines
5.9 KiB
Diff
From fff3364a637796611c06f59a6f2be61685d99bfe Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Sun, 2 Apr 2017 18:55:22 +0200
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Subject: [PATCH] phy: bcm-ns-usb3: split all writes into reg & val pairs
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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So far all the PHY initialization was implemented using some totally
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magic values. There was some pattern there but it wasn't clear what is
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it about.
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Thanks to the patch submitted by Broadcom:
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[PATCH 5/6] phy: Add USB3 PHY support for Broadcom NSP SoC
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and the upstream "iproc-mdio" driver we now know there is a MDIO bus
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underneath with PHY(s) and their registers.
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It allows us to clean the driver a bit by making all these values less
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magical. The next step is switching to using a proper MDIO layer.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Acked-by: Jon Mason <jon.mason@broadcom.com>
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Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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---
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drivers/phy/phy-bcm-ns-usb3.c | 69 ++++++++++++++++++++++++++++++-------------
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1 file changed, 49 insertions(+), 20 deletions(-)
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--- a/drivers/phy/phy-bcm-ns-usb3.c
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+++ b/drivers/phy/phy-bcm-ns-usb3.c
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@@ -2,6 +2,7 @@
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* Broadcom Northstar USB 3.0 PHY Driver
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*
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* Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
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+ * Copyright (C) 2016 Broadcom
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*
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* All magic values used for initialization (and related comments) were obtained
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* from Broadcom's SDK:
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@@ -23,6 +24,23 @@
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#define BCM_NS_USB3_MII_MNG_TIMEOUT_US 1000 /* usecs */
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+#define BCM_NS_USB3_PHY_BASE_ADDR_REG 0x1f
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+#define BCM_NS_USB3_PHY_PLL30_BLOCK 0x8000
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+#define BCM_NS_USB3_PHY_TX_PMD_BLOCK 0x8040
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+#define BCM_NS_USB3_PHY_PIPE_BLOCK 0x8060
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+
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+/* Registers of PLL30 block */
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+#define BCM_NS_USB3_PLL_CONTROL 0x01
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+#define BCM_NS_USB3_PLLA_CONTROL0 0x0a
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+#define BCM_NS_USB3_PLLA_CONTROL1 0x0b
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+
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+/* Registers of TX PMD block */
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+#define BCM_NS_USB3_TX_PMD_CONTROL1 0x01
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+
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+/* Registers of PIPE block */
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+#define BCM_NS_USB3_LFPS_CMP 0x02
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+#define BCM_NS_USB3_LFPS_DEGLITCH 0x03
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+
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enum bcm_ns_family {
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BCM_NS_UNKNOWN,
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BCM_NS_AX,
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@@ -76,8 +94,10 @@ static inline int bcm_ns_usb3_mii_mng_wa
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usecs_to_jiffies(BCM_NS_USB3_MII_MNG_TIMEOUT_US));
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}
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-static int bcm_ns_usb3_mii_mng_write32(struct bcm_ns_usb3 *usb3, u32 value)
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+static int bcm_ns_usb3_mdio_phy_write(struct bcm_ns_usb3 *usb3, u16 reg,
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+ u16 value)
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{
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+ u32 tmp = 0;
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int err;
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err = bcm_ns_usb3_mii_mng_wait_idle(usb3);
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@@ -86,7 +106,11 @@ static int bcm_ns_usb3_mii_mng_write32(s
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return err;
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}
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- writel(value, usb3->ccb_mii + BCMA_CCB_MII_MNG_CMD_DATA);
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+ /* TODO: Use a proper MDIO bus layer */
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+ tmp |= 0x58020000; /* Magic value for MDIO PHY write */
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+ tmp |= reg << 18;
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+ tmp |= value;
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+ writel(tmp, usb3->ccb_mii + BCMA_CCB_MII_MNG_CMD_DATA);
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return 0;
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}
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@@ -102,21 +126,22 @@ static int bcm_ns_usb3_phy_init_ns_bx(st
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udelay(2);
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/* USB3 PLL Block */
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- err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000);
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+ err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
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+ BCM_NS_USB3_PHY_PLL30_BLOCK);
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if (err < 0)
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return err;
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/* Assert Ana_Pllseq start */
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x58061000);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLL_CONTROL, 0x1000);
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/* Assert CML Divider ratio to 26 */
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL0, 0x6400);
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/* Asserting PLL Reset */
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x582ec000);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL1, 0xc000);
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/* Deaaserting PLL Reset */
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x582e8000);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL1, 0x8000);
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/* Waiting MII Mgt interface idle */
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bcm_ns_usb3_mii_mng_wait_idle(usb3);
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@@ -125,22 +150,24 @@ static int bcm_ns_usb3_phy_init_ns_bx(st
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writel(0, usb3->dmp + BCMA_RESET_CTL);
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/* PLL frequency monitor enable */
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x58069000);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLL_CONTROL, 0x9000);
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/* PIPE Block */
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8060);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
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+ BCM_NS_USB3_PHY_PIPE_BLOCK);
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/* CMPMAX & CMPMINTH setting */
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x580af30d);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_LFPS_CMP, 0xf30d);
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/* DEGLITCH MIN & MAX setting */
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x580e6302);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_LFPS_DEGLITCH, 0x6302);
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/* TXPMD block */
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
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+ BCM_NS_USB3_PHY_TX_PMD_BLOCK);
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/* Enabling SSC */
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_TX_PMD_CONTROL1, 0x1003);
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/* Waiting MII Mgt interface idle */
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bcm_ns_usb3_mii_mng_wait_idle(usb3);
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@@ -159,22 +186,24 @@ static int bcm_ns_usb3_phy_init_ns_ax(st
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udelay(2);
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/* PLL30 block */
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- err = bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8000);
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+ err = bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
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+ BCM_NS_USB3_PHY_PLL30_BLOCK);
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if (err < 0)
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return err;
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x582a6400);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PLLA_CONTROL0, 0x6400);
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x587e80e0);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG, 0x80e0);
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x580a009c);
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+ bcm_ns_usb3_mdio_phy_write(usb3, 0x02, 0x009c);
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/* Enable SSC */
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x587e8040);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_PHY_BASE_ADDR_REG,
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+ BCM_NS_USB3_PHY_TX_PMD_BLOCK);
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x580a21d3);
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+ bcm_ns_usb3_mdio_phy_write(usb3, 0x02, 0x21d3);
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- bcm_ns_usb3_mii_mng_write32(usb3, 0x58061003);
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+ bcm_ns_usb3_mdio_phy_write(usb3, BCM_NS_USB3_TX_PMD_CONTROL1, 0x1003);
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/* Waiting MII Mgt interface idle */
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bcm_ns_usb3_mii_mng_wait_idle(usb3);
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