mirror of https://github.com/hak5/openwrt.git
175 lines
4.9 KiB
Diff
175 lines
4.9 KiB
Diff
From 7b8e7bc9806b61be2f07bf2bbb5e3ee6e0f333e9 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Sun, 21 Apr 2013 15:38:56 +0200
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Subject: [PATCH 10/13] MIPS: BCM63XX: protect irq register accesses with a
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spinlock
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Since IRQs can be handled on both CPUs, we need to ensure that we
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don't try to modify the IRQ registers at the same time.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/irq.c | 47 ++++++++++++++++++++++++++++++++++++++++++-----
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1 file changed, 42 insertions(+), 5 deletions(-)
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--- a/arch/mips/bcm63xx/irq.c
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+++ b/arch/mips/bcm63xx/irq.c
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@@ -12,6 +12,7 @@
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/irq.h>
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+#include <linux/spinlock.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <bcm63xx_cpu.h>
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@@ -26,6 +27,9 @@ static void __internal_irq_mask_64(unsig
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static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
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static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
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+static DEFINE_SPINLOCK(ipic_lock);
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+static DEFINE_SPINLOCK(epic_lock);
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+
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#ifndef BCMCPU_RUNTIME_DETECT
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#ifdef CONFIG_BCM63XX_CPU_6328
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#define irq_stat_reg0 PERF_IRQSTAT_6328_REG(0)
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@@ -290,7 +294,9 @@ void __dispatch_internal_##width(int cpu
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static int i; \
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u32 irq_stat_addr = get_irq_stat_addr(cpu); \
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u32 irq_mask_addr = get_irq_mask_addr(cpu); \
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+ unsigned long flags; \
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\
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+ spin_lock_irqsave(&ipic_lock, flags); \
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/* read registers in reverse order */ \
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for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
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u32 val; \
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@@ -302,6 +308,7 @@ void __dispatch_internal_##width(int cpu
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if (val) \
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irqs_pending = true; \
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} \
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+ spin_unlock_irqrestore(&ipic_lock, flags); \
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\
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if (!irqs_pending) \
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return; \
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@@ -381,12 +388,20 @@ asmlinkage void plat_irq_dispatch(void)
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*/
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static void bcm63xx_internal_irq_mask(struct irq_data *d)
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{
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&ipic_lock, flags);
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internal_irq_mask(d->irq - IRQ_INTERNAL_BASE);
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+ spin_unlock_irqrestore(&ipic_lock, flags);
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}
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static void bcm63xx_internal_irq_unmask(struct irq_data *d)
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{
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&ipic_lock, flags);
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internal_irq_unmask(d->irq - IRQ_INTERNAL_BASE);
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+ spin_unlock_irqrestore(&ipic_lock, flags);
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}
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/*
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@@ -397,8 +412,11 @@ static void bcm63xx_external_irq_mask(st
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg, regaddr;
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+ unsigned long flags;
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regaddr = get_ext_irq_perf_reg(irq);
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+
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+ spin_lock_irqsave(&epic_lock, flags);
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reg = bcm_perf_readl(regaddr);
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if (BCMCPU_IS_6348())
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@@ -407,16 +425,24 @@ static void bcm63xx_external_irq_mask(st
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reg &= ~EXTIRQ_CFG_MASK(irq % 4);
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bcm_perf_writel(reg, regaddr);
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- if (is_ext_irq_cascaded)
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- internal_irq_mask(irq + ext_irq_start);
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+ spin_unlock_irqrestore(&epic_lock, flags);
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+
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+ if (is_ext_irq_cascaded) {
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+ struct irq_data *cd = irq_get_irq_data(irq + ext_irq_start);
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+
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+ bcm63xx_internal_irq_mask(cd);
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+ }
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}
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static void bcm63xx_external_irq_unmask(struct irq_data *d)
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg, regaddr;
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+ unsigned long flags;
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regaddr = get_ext_irq_perf_reg(irq);
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+
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+ spin_lock_irqsave(&epic_lock, flags);
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reg = bcm_perf_readl(regaddr);
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if (BCMCPU_IS_6348())
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@@ -425,16 +451,22 @@ static void bcm63xx_external_irq_unmask(
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reg |= EXTIRQ_CFG_MASK(irq % 4);
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bcm_perf_writel(reg, regaddr);
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+ spin_unlock_irqrestore(&epic_lock, flags);
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+
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+ if (is_ext_irq_cascaded) {
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+ struct irq_data *cd = irq_get_irq_data(irq + ext_irq_start);
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- if (is_ext_irq_cascaded)
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- internal_irq_unmask(irq + ext_irq_start);
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+ bcm63xx_internal_irq_unmask(cd);
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+ }
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}
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static void bcm63xx_external_irq_clear(struct irq_data *d)
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{
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg, regaddr;
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+ unsigned long flags;
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+ spin_lock_irqsave(&epic_lock, flags);
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regaddr = get_ext_irq_perf_reg(irq);
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reg = bcm_perf_readl(regaddr);
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@@ -444,6 +476,7 @@ static void bcm63xx_external_irq_clear(s
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reg |= EXTIRQ_CFG_CLEAR(irq % 4);
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bcm_perf_writel(reg, regaddr);
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+ spin_unlock_irqrestore(&epic_lock, flags);
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}
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static int bcm63xx_external_irq_set_type(struct irq_data *d,
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@@ -452,6 +485,7 @@ static int bcm63xx_external_irq_set_type
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unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
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u32 reg, regaddr;
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int levelsense, sense, bothedge;
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+ unsigned long flags;
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flow_type &= IRQ_TYPE_SENSE_MASK;
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@@ -486,9 +520,11 @@ static int bcm63xx_external_irq_set_type
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}
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regaddr = get_ext_irq_perf_reg(irq);
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- reg = bcm_perf_readl(regaddr);
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irq %= 4;
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+ spin_lock_irqsave(&epic_lock, flags);
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+ reg = bcm_perf_readl(regaddr);
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+
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switch (bcm63xx_get_cpu_id()) {
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case BCM6348_CPU_ID:
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if (levelsense)
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@@ -529,6 +565,7 @@ static int bcm63xx_external_irq_set_type
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}
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bcm_perf_writel(reg, regaddr);
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+ spin_unlock_irqrestore(&epic_lock, flags);
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irqd_set_trigger_type(d, flow_type);
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if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
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