mirror of https://github.com/hak5/openwrt.git
471 lines
12 KiB
C
471 lines
12 KiB
C
/*
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* $Id$
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*
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* Copyright (C) 2007 OpenWrt.org
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <asm/ar7/ar7.h>
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#define BOOT_PLL_SOURCE_MASK 0x3
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#define CPU_PLL_SOURCE_SHIFT 16
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#define BUS_PLL_SOURCE_SHIFT 14
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#define USB_PLL_SOURCE_SHIFT 18
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#define DSP_PLL_SOURCE_SHIFT 22
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#define BOOT_PLL_SOURCE_AFE 0
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#define BOOT_PLL_SOURCE_BUS 0
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#define BOOT_PLL_SOURCE_REF 1
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#define BOOT_PLL_SOURCE_XTAL 2
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#define BOOT_PLL_SOURCE_CPU 3
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#define BOOT_PLL_BYPASS 0x00000020
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#define BOOT_PLL_ASYNC_MODE 0x02000000
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#define BOOT_PLL_2TO1_MODE 0x00008000
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#define TNETD7200_CLOCK_ID_CPU 0
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#define TNETD7200_CLOCK_ID_DSP 1
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#define TNETD7200_CLOCK_ID_USB 2
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#define TNETD7200_DEF_CPU_CLK 211000000
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#define TNETD7200_DEF_DSP_CLK 125000000
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#define TNETD7200_DEF_USB_CLK 48000000
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struct tnetd7300_clock {
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volatile u32 ctrl;
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#define PREDIV_MASK 0x001f0000
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#define PREDIV_SHIFT 16
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#define POSTDIV_MASK 0x0000001f
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u32 unused1[3];
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volatile u32 pll;
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#define MUL_MASK 0x0000f000
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#define MUL_SHIFT 12
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#define PLL_MODE_MASK 0x00000001
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#define PLL_NDIV 0x00000800
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#define PLL_DIV 0x00000002
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#define PLL_STATUS 0x00000001
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u32 unused2[3];
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} __attribute__ ((packed));
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struct tnetd7300_clocks {
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struct tnetd7300_clock bus;
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struct tnetd7300_clock cpu;
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struct tnetd7300_clock usb;
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struct tnetd7300_clock dsp;
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} __attribute__ ((packed));
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struct tnetd7200_clock {
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volatile u32 ctrl;
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u32 unused1[3];
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#define DIVISOR_ENABLE_MASK 0x00008000
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volatile u32 mul;
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volatile u32 prediv;
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volatile u32 postdiv;
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volatile u32 postdiv2;
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u32 unused2[6];
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volatile u32 cmd;
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volatile u32 status;
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volatile u32 cmden;
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u32 padding[15];
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} __attribute__ ((packed));
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struct tnetd7200_clocks {
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struct tnetd7200_clock cpu;
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struct tnetd7200_clock dsp;
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struct tnetd7200_clock usb;
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} __attribute__ ((packed));
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int ar7_afe_clock = 35328000;
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int ar7_ref_clock = 25000000;
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int ar7_xtal_clock = 24000000;
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int ar7_cpu_clock = 150000000;
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EXPORT_SYMBOL(ar7_cpu_clock);
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int ar7_bus_clock = 125000000;
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EXPORT_SYMBOL(ar7_bus_clock);
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int ar7_dsp_clock = 0;
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EXPORT_SYMBOL(ar7_dsp_clock);
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static int gcd(int x, int y)
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{
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if (x > y)
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return (x % y) ? gcd(y, x % y) : y;
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return (y % x) ? gcd(x, y % x) : x;
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}
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static inline int ABS(int x)
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{
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return (x >= 0) ? x : -x;
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}
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static void approximate(int base, int target, int *prediv,
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int *postdiv, int *mul)
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{
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int i, j, k, freq, res = target;
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for (i = 1; i <= 16; i++) {
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for (j = 1; j <= 32; j++) {
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for (k = 1; k <= 32; k++) {
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freq = ABS(base / j * i / k - target);
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if (freq < res) {
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res = freq;
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*mul = i;
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*prediv = j;
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*postdiv = k;
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}
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}
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}
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}
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}
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static void calculate(int base, int target, int *prediv, int *postdiv,
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int *mul)
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{
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int tmp_gcd, tmp_base, tmp_freq;
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for (*prediv = 1; *prediv <= 32; (*prediv)++) {
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tmp_base = base / *prediv;
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tmp_gcd = gcd(target, tmp_base);
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*mul = target / tmp_gcd;
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*postdiv = tmp_base / tmp_gcd;
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if ((*mul < 1) || (*mul >= 16))
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continue;
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if ((*postdiv > 0) & (*postdiv <= 32))
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break;
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}
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if (base / (*prediv) * (*mul) / (*postdiv) != target) {
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approximate(base, target, prediv, postdiv, mul);
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tmp_freq = base / (*prediv) * (*mul) / (*postdiv);
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printk(KERN_WARNING
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"Adjusted requested frequency %d to %d\n",
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target, tmp_freq);
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}
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printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
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*prediv, *postdiv, *mul);
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}
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static int tnetd7300_dsp_clock(void)
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{
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u32 didr1, didr2;
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u8 rev = ar7_chip_rev();
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didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
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didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
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if (didr2 & (1 << 23))
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return 0;
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if ((rev >= 0x23) && (rev != 0x57))
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return 250000000;
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if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
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> 4208000)
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return 250000000;
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return 0;
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}
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static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
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u32 *bootcr, u32 bus_clock)
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{
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int product;
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int base_clock = ar7_ref_clock;
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u32 ctrl = clock->ctrl;
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u32 pll = clock->pll;
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int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
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int postdiv = (ctrl & POSTDIV_MASK) + 1;
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int divisor = prediv * postdiv;
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int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
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switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
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case BOOT_PLL_SOURCE_BUS:
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base_clock = bus_clock;
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break;
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case BOOT_PLL_SOURCE_REF:
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base_clock = ar7_ref_clock;
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break;
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case BOOT_PLL_SOURCE_XTAL:
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base_clock = ar7_xtal_clock;
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break;
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case BOOT_PLL_SOURCE_CPU:
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base_clock = ar7_cpu_clock;
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break;
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}
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if (*bootcr & BOOT_PLL_BYPASS)
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return base_clock / divisor;
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if ((pll & PLL_MODE_MASK) == 0)
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return (base_clock >> (mul / 16 + 1)) / divisor;
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if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
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product = (mul & 1) ?
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(base_clock * mul) >> 1 :
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(base_clock * (mul - 1)) >> 2;
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return product / divisor;
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}
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if (mul == 16)
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return base_clock / divisor;
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return base_clock * mul / divisor;
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}
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static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
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u32 *bootcr, u32 frequency)
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{
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u32 status;
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int prediv, postdiv, mul;
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int base_clock = ar7_bus_clock;
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switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
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case BOOT_PLL_SOURCE_BUS:
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base_clock = ar7_bus_clock;
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break;
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case BOOT_PLL_SOURCE_REF:
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base_clock = ar7_ref_clock;
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break;
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case BOOT_PLL_SOURCE_XTAL:
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base_clock = ar7_xtal_clock;
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break;
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case BOOT_PLL_SOURCE_CPU:
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base_clock = ar7_cpu_clock;
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break;
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}
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calculate(base_clock, frequency, &prediv, &postdiv, &mul);
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clock->ctrl = ((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1);
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mdelay(1);
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clock->pll = 4;
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do {
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status = clock->pll;
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} while (status & PLL_STATUS);
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clock->pll = ((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e;
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mdelay(75);
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}
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static void __init tnetd7300_init_clocks(void)
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{
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u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
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struct tnetd7300_clocks *clocks = (struct tnetd7300_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x20, sizeof(struct tnetd7300_clocks));
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ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
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&clocks->bus, bootcr, ar7_afe_clock);
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if (*bootcr & BOOT_PLL_ASYNC_MODE) {
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ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
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&clocks->cpu, bootcr, ar7_afe_clock);
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} else {
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ar7_cpu_clock = ar7_bus_clock;
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}
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tnetd7300_set_clock(USB_PLL_SOURCE_SHIFT, &clocks->usb,
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bootcr, 48000000);
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if (ar7_dsp_clock == 250000000)
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tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
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bootcr, ar7_dsp_clock);
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iounmap(clocks);
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iounmap(bootcr);
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}
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static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
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u32 *bootcr, u32 bus_clock)
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{
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int divisor = ((clock->prediv & 0x1f) + 1) *
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((clock->postdiv & 0x1f) + 1);
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if (*bootcr & BOOT_PLL_BYPASS)
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return base / divisor;
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return base * ((clock->mul & 0xf) + 1) / divisor;
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}
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static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
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int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
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{
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printk("Clocks: base = %d, frequency = %u, prediv = %d, postdiv = %d, postdiv2 = %d, mul = %d\n",
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base, frequency, prediv, postdiv, postdiv2, mul);
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clock->ctrl = 0;
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clock->prediv = DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F);
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clock->mul = ((mul - 1) & 0xF);
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for(mul = 0; mul < 2000; mul++) /* nop */;
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while(clock->status & 0x1) /* nop */;
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clock->postdiv = DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F);
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clock->cmden |= 1;
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clock->cmd |= 1;
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while(clock->status & 0x1) /* nop */;
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clock->postdiv2 = DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F);
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clock->cmden |= 1;
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clock->cmd |= 1;
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while(clock->status & 0x1) /* nop */;
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clock->ctrl |= 1;
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}
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static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
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{
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if (*bootcr & BOOT_PLL_ASYNC_MODE) {
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// Async
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switch (clock_id) {
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case TNETD7200_CLOCK_ID_DSP:
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return ar7_ref_clock;
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default:
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return ar7_afe_clock;
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}
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} else {
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// Sync
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if (*bootcr & BOOT_PLL_2TO1_MODE) {
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// 2:1
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switch (clock_id) {
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case TNETD7200_CLOCK_ID_DSP:
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return ar7_ref_clock;
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default:
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return ar7_afe_clock;
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}
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} else {
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// 1:1
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return ar7_ref_clock;
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}
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}
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}
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static void __init tnetd7200_init_clocks(void)
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{
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u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
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struct tnetd7200_clocks *clocks = (struct tnetd7200_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x80, sizeof(struct tnetd7200_clocks));
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int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
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int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
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int usb_base, usb_mul, usb_prediv, usb_postdiv;
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/*
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Log from Fritz!Box 7170 Annex B:
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CPU revision is: 00018448
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Clocks: Async mode
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Clocks: Setting DSP clock
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Clocks: prediv: 1, postdiv: 1, mul: 5
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Clocks: base = 25000000, frequency = 125000000, prediv = 1, postdiv = 2, postdiv2 = 1, mul = 10
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Clocks: Setting CPU clock
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Adjusted requested frequency 211000000 to 211968000
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Clocks: prediv: 1, postdiv: 1, mul: 6
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Clocks: base = 35328000, frequency = 211968000, prediv = 1, postdiv = 1, postdiv2 = -1, mul = 6
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Clocks: Setting USB clock
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Adjusted requested frequency 48000000 to 48076920
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Clocks: prediv: 13, postdiv: 1, mul: 5
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Clocks: base = 125000000, frequency = 48000000, prediv = 13, postdiv = 1, postdiv2 = -1, mul = 5
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DSL didn't work if you didn't set the postdiv 2:1 postdiv2 combination, driver hung on startup.
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Haven't tested this on a synchronous board, neither do i know what to do with ar7_dsp_clock
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*/
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cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
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dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
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if (*bootcr & BOOT_PLL_ASYNC_MODE) {
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printk("Clocks: Async mode\n");
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printk("Clocks: Setting DSP clock\n");
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calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
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ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
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tnetd7200_set_clock(dsp_base, &clocks->dsp,
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dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
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ar7_bus_clock);
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printk("Clocks: Setting CPU clock\n");
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calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, &cpu_postdiv, &cpu_mul);
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ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
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tnetd7200_set_clock(cpu_base, &clocks->cpu,
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cpu_prediv, cpu_postdiv, -1, cpu_mul,
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ar7_cpu_clock);
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} else {
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if (*bootcr & BOOT_PLL_2TO1_MODE) {
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printk("Clocks: Sync 2:1 mode\n");
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printk("Clocks: Setting CPU clock\n");
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calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, &cpu_postdiv, &cpu_mul);
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ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
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tnetd7200_set_clock(cpu_base, &clocks->cpu,
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cpu_prediv, cpu_postdiv, -1, cpu_mul,
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ar7_cpu_clock);
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printk("Clocks: Setting DSP clock\n");
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calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
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ar7_bus_clock = ar7_cpu_clock / 2;
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tnetd7200_set_clock(dsp_base, &clocks->dsp,
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dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
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ar7_bus_clock);
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} else {
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printk("Clocks: Sync 1:1 mode\n");
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printk("Clocks: Setting DSP clock\n");
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calculate(dsp_base, TNETD7200_DEF_CPU_CLK, &dsp_prediv, &dsp_postdiv, &dsp_mul);
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ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
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tnetd7200_set_clock(dsp_base, &clocks->dsp,
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dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
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ar7_bus_clock);
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ar7_cpu_clock = ar7_bus_clock;
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}
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}
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printk("Clocks: Setting USB clock\n");
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usb_base = ar7_bus_clock;
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calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv, &usb_postdiv, &usb_mul);
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tnetd7200_set_clock(usb_base, &clocks->usb,
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usb_prediv, usb_postdiv, -1, usb_mul,
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TNETD7200_DEF_USB_CLK);
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#warning FIXME: ????! Hrmm
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ar7_dsp_clock = ar7_cpu_clock;
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iounmap(clocks);
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iounmap(bootcr);
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}
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void __init ar7_init_clocks(void)
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{
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switch (ar7_chip_id()) {
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case AR7_CHIP_7100:
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#warning FIXME: Check if the new 7200 clock init works for 7100
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tnetd7200_init_clocks();
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break;
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case AR7_CHIP_7200:
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tnetd7200_init_clocks();
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break;
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case AR7_CHIP_7300:
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ar7_dsp_clock = tnetd7300_dsp_clock();
|
|
tnetd7300_init_clocks();
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|