mirror of https://github.com/hak5/openwrt.git
406 lines
10 KiB
Diff
406 lines
10 KiB
Diff
From 61ac7d9b4228de8c332900902c2b93189b042eab Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sun, 27 Jul 2014 11:00:32 +0100
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Subject: [PATCH 28/53] GPIO: ralink: add mt7621 gpio controller
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/Kconfig | 3 +
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drivers/gpio/Kconfig | 6 +
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drivers/gpio/Makefile | 1 +
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drivers/gpio/gpio-mt7621.c | 354 ++++++++++++++++++++++++++++++++++++++++++++
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4 files changed, 364 insertions(+)
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create mode 100644 drivers/gpio/gpio-mt7621.c
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -559,6 +559,9 @@ config RALINK
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select RESET_CONTROLLER
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select PINCTRL
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select PINCTRL_RT2880
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+ select ARCH_HAS_RESET_CONTROLLER
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+ select RESET_CONTROLLER
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+ select ARCH_REQUIRE_GPIOLIB
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config SGI_IP22
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bool "SGI IP22 (Indy/Indigo2)"
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--- a/drivers/gpio/Kconfig
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+++ b/drivers/gpio/Kconfig
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@@ -269,6 +269,12 @@ config GPIO_MB86S7X
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help
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Say yes here to support the GPIO controller in Fujitsu MB86S70 SoCs.
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+config GPIO_MT7621
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+ bool "Mediatek GPIO Support"
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+ depends on SOC_MT7620 || SOC_MT7621
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+ help
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+ Say yes here to support the Mediatek SoC GPIO device
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+
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config GPIO_MM_LANTIQ
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bool "Lantiq Memory mapped GPIOs"
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depends on LANTIQ && SOC_XWAY
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--- a/drivers/gpio/Makefile
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+++ b/drivers/gpio/Makefile
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@@ -119,3 +119,4 @@ obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa
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obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
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obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o
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obj-$(CONFIG_GPIO_ZX) += gpio-zx.o
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+obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
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--- /dev/null
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+++ b/drivers/gpio/gpio-mt7621.c
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@@ -0,0 +1,354 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/io.h>
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+#include <linux/err.h>
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+#include <linux/gpio.h>
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+#include <linux/module.h>
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+#include <linux/of_irq.h>
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+#include <linux/spinlock.h>
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+#include <linux/irqdomain.h>
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+#include <linux/interrupt.h>
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+#include <linux/platform_device.h>
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+
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+#define MTK_MAX_BANK 3
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+#define MTK_BANK_WIDTH 32
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+
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+enum mediatek_gpio_reg {
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+ GPIO_REG_CTRL = 0,
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+ GPIO_REG_POL,
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+ GPIO_REG_DATA,
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+ GPIO_REG_DSET,
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+ GPIO_REG_DCLR,
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+ GPIO_REG_REDGE,
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+ GPIO_REG_FEDGE,
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+ GPIO_REG_HLVL,
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+ GPIO_REG_LLVL,
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+ GPIO_REG_STAT,
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+ GPIO_REG_EDGE,
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+};
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+
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+static void __iomem *mediatek_gpio_membase;
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+static int mediatek_gpio_irq;
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+static struct irq_domain *mediatek_gpio_irq_domain;
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+static atomic_t irq_refcount = ATOMIC_INIT(0);
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+
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+struct mtk_gc {
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+ struct gpio_chip chip;
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+ spinlock_t lock;
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+ int bank;
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+ u32 rising;
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+ u32 falling;
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+} *gc_map[MTK_MAX_BANK];
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+
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+static inline struct mtk_gc
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+*to_mediatek_gpio(struct gpio_chip *chip)
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+{
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+ struct mtk_gc *mgc;
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+
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+ mgc = container_of(chip, struct mtk_gc, chip);
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+
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+ return mgc;
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+}
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+
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+static inline void
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+mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
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+{
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+ iowrite32(val, mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
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+}
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+
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+static inline u32
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+mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
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+{
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+ return ioread32(mediatek_gpio_membase + (reg * 0x10) + (rg->bank * 0x4));
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+}
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+
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+static void
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+mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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+{
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+ struct mtk_gc *rg = to_mediatek_gpio(chip);
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+
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+ mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
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+}
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+
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+static int
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+mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
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+{
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+ struct mtk_gc *rg = to_mediatek_gpio(chip);
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+
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+ return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
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+}
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+
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+static int
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+mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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+{
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+ struct mtk_gc *rg = to_mediatek_gpio(chip);
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+ unsigned long flags;
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+ u32 t;
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+
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+ spin_lock_irqsave(&rg->lock, flags);
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+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
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+ t &= ~BIT(offset);
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+ mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
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+ spin_unlock_irqrestore(&rg->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int
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+mediatek_gpio_direction_output(struct gpio_chip *chip,
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+ unsigned offset, int value)
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+{
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+ struct mtk_gc *rg = to_mediatek_gpio(chip);
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+ unsigned long flags;
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+ u32 t;
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+
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+ spin_lock_irqsave(&rg->lock, flags);
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+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
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+ t |= BIT(offset);
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+ mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
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+ mediatek_gpio_set(chip, offset, value);
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+ spin_unlock_irqrestore(&rg->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int
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+mediatek_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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+{
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+ struct mtk_gc *rg = to_mediatek_gpio(chip);
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+ unsigned long flags;
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+ u32 t;
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+
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+ spin_lock_irqsave(&rg->lock, flags);
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+ t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
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+ spin_unlock_irqrestore(&rg->lock, flags);
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+
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+ if (t & BIT(offset))
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+ return 0;
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+
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+ return 1;
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+}
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+
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+static int
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+mediatek_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
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+{
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+ struct mtk_gc *rg = to_mediatek_gpio(chip);
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+
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+ return irq_create_mapping(mediatek_gpio_irq_domain, pin + (rg->bank * MTK_BANK_WIDTH));
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+}
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+
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+static int
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+mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
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+{
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+ const __be32 *id = of_get_property(bank, "reg", NULL);
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+ struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
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+ sizeof(struct mtk_gc), GFP_KERNEL);
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+
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+ if (!rg || !id || be32_to_cpu(*id) > MTK_MAX_BANK)
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+ return -ENOMEM;
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+
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+ gc_map[be32_to_cpu(*id)] = rg;
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+
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+ memset(rg, 0, sizeof(struct mtk_gc));
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+
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+ spin_lock_init(&rg->lock);
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+
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+ rg->chip.dev = &pdev->dev;
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+ rg->chip.label = dev_name(&pdev->dev);
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+ rg->chip.of_node = bank;
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+ rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
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+ rg->chip.ngpio = MTK_BANK_WIDTH;
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+ rg->chip.direction_input = mediatek_gpio_direction_input;
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+ rg->chip.direction_output = mediatek_gpio_direction_output;
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+ rg->chip.get_direction = mediatek_gpio_get_direction;
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+ rg->chip.get = mediatek_gpio_get;
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+ rg->chip.set = mediatek_gpio_set;
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+ if (mediatek_gpio_irq_domain)
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+ rg->chip.to_irq = mediatek_gpio_to_irq;
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+ rg->bank = be32_to_cpu(*id);
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+
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+ /* set polarity to low for all gpios */
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+ mtk_gpio_w32(rg, GPIO_REG_POL, 0);
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+
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+ dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
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+
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+ return gpiochip_add(&rg->chip);
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+}
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+
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+static void
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+mediatek_gpio_irq_handler(struct irq_desc *desc)
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+{
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+ int i;
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+
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+ for (i = 0; i < MTK_MAX_BANK; i++) {
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+ struct mtk_gc *rg = gc_map[i];
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+ unsigned long pending;
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+ int bit;
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+
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+ if (!rg)
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+ continue;
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+
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+ pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
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+
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+ for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
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+ u32 map = irq_find_mapping(mediatek_gpio_irq_domain, (MTK_BANK_WIDTH * i) + bit);
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+
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+ generic_handle_irq(map);
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+ mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
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+ }
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+ }
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+}
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+
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+static void
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+mediatek_gpio_irq_unmask(struct irq_data *d)
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+{
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+ int pin = d->hwirq;
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+ int bank = pin / 32;
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+ struct mtk_gc *rg = gc_map[bank];
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+ unsigned long flags;
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+ u32 rise, fall;
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+
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+ if (!rg)
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+ return;
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+
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+ rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
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+ fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
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+
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+ spin_lock_irqsave(&rg->lock, flags);
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+ mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(d->hwirq) & rg->rising));
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+ mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(d->hwirq) & rg->falling));
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+ spin_unlock_irqrestore(&rg->lock, flags);
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+}
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+
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+static void
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+mediatek_gpio_irq_mask(struct irq_data *d)
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+{
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+ int pin = d->hwirq;
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+ int bank = pin / 32;
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+ struct mtk_gc *rg = gc_map[bank];
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+ unsigned long flags;
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+ u32 rise, fall;
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+
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+ if (!rg)
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+ return;
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+
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+ rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
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+ fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
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+
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+ spin_lock_irqsave(&rg->lock, flags);
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+ mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(d->hwirq));
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+ mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(d->hwirq));
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+ spin_unlock_irqrestore(&rg->lock, flags);
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+}
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+
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+static int
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+mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
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+{
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+ int pin = d->hwirq;
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+ int bank = pin / 32;
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+ struct mtk_gc *rg = gc_map[bank];
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+ u32 mask = BIT(d->hwirq);
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+
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+ if (!rg)
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+ return -1;
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+
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+ if (type == IRQ_TYPE_PROBE) {
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+ if ((rg->rising | rg->falling) & mask)
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+ return 0;
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+
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+ type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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+ }
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+
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+ if (type & IRQ_TYPE_EDGE_RISING)
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+ rg->rising |= mask;
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+ else
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+ rg->rising &= ~mask;
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+
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+ if (type & IRQ_TYPE_EDGE_FALLING)
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+ rg->falling |= mask;
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+ else
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+ rg->falling &= ~mask;
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+
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+ return 0;
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+}
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+
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+static struct irq_chip mediatek_gpio_irq_chip = {
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+ .name = "GPIO",
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+ .irq_unmask = mediatek_gpio_irq_unmask,
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+ .irq_mask = mediatek_gpio_irq_mask,
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+ .irq_mask_ack = mediatek_gpio_irq_mask,
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+ .irq_set_type = mediatek_gpio_irq_type,
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+};
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+
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+static int
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+mediatek_gpio_gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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+{
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+ irq_set_chip_and_handler(irq, &mediatek_gpio_irq_chip, handle_level_irq);
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+ irq_set_handler_data(irq, d);
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+
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+ return 0;
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+}
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+
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+static const struct irq_domain_ops irq_domain_ops = {
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+ .xlate = irq_domain_xlate_onecell,
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+ .map = mediatek_gpio_gpio_map,
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+};
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+
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+static int
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+mediatek_gpio_probe(struct platform_device *pdev)
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+{
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+ struct device_node *bank, *np = pdev->dev.of_node;
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+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+
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+ mediatek_gpio_membase = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(mediatek_gpio_membase))
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+ return PTR_ERR(mediatek_gpio_membase);
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+
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+ mediatek_gpio_irq = irq_of_parse_and_map(np, 0);
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+ if (mediatek_gpio_irq) {
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+ mediatek_gpio_irq_domain = irq_domain_add_linear(np,
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+ MTK_MAX_BANK * MTK_BANK_WIDTH,
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+ &irq_domain_ops, NULL);
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+ if (!mediatek_gpio_irq_domain)
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+ dev_err(&pdev->dev, "irq_domain_add_linear failed\n");
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+ }
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+
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+ for_each_child_of_node(np, bank)
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+ if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
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+ mediatek_gpio_bank_probe(pdev, bank);
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+
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+ if (mediatek_gpio_irq_domain)
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+ irq_set_chained_handler(mediatek_gpio_irq, mediatek_gpio_irq_handler);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id mediatek_gpio_match[] = {
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+ { .compatible = "mtk,mt7621-gpio" },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
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+
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+static struct platform_driver mediatek_gpio_driver = {
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+ .probe = mediatek_gpio_probe,
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+ .driver = {
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+ .name = "mt7621_gpio",
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+ .owner = THIS_MODULE,
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+ .of_match_table = mediatek_gpio_match,
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+ },
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+};
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+
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+static int __init
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+mediatek_gpio_init(void)
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+{
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+ return platform_driver_register(&mediatek_gpio_driver);
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+}
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+
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+subsys_initcall(mediatek_gpio_init);
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