mirror of https://github.com/hak5/openwrt.git
298 lines
9.0 KiB
Diff
298 lines
9.0 KiB
Diff
From 92ce45fb875d7c3e021cc454482fe0687ff54f29 Mon Sep 17 00:00:00 2001
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From: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Date: Thu, 14 Dec 2017 16:00:05 +0100
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Subject: cpufreq: Add DVFS support for Armada 37xx
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This patch adds DVFS support for the Armada 37xx SoCs
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There are up to four CPU frequency loads for Armada 37xx controlled by
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the hardware.
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This driver associates the CPU load level to a frequency, then the
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hardware will switch while selecting a load level.
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The hardware also can associate a voltage for each level (AVS support)
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but it is not yet supported
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Tested-by: Andre Heider <a.heider@gmail.com>
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Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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---
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drivers/cpufreq/Kconfig.arm | 7 +
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drivers/cpufreq/Makefile | 1 +
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drivers/cpufreq/armada-37xx-cpufreq.c | 241 ++++++++++++++++++++++++++++++++++
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3 files changed, 249 insertions(+)
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create mode 100644 drivers/cpufreq/armada-37xx-cpufreq.c
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--- a/drivers/cpufreq/Kconfig.arm
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+++ b/drivers/cpufreq/Kconfig.arm
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@@ -2,6 +2,13 @@
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# ARM CPU Frequency scaling drivers
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#
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+config ARM_ARMADA_37XX_CPUFREQ
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+ tristate "Armada 37xx CPUFreq support"
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+ depends on ARCH_MVEBU
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+ help
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+ This adds the CPUFreq driver support for Marvell Armada 37xx SoCs.
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+ The Armada 37xx PMU supports 4 frequency and VDD levels.
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+
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# big LITTLE core layer and glue drivers
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config ARM_BIG_LITTLE_CPUFREQ
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tristate "Generic ARM big LITTLE CPUfreq driver"
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--- a/drivers/cpufreq/Makefile
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+++ b/drivers/cpufreq/Makefile
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@@ -52,6 +52,7 @@ obj-$(CONFIG_ARM_BIG_LITTLE_CPUFREQ) +=
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# LITTLE drivers, so that it is probed last.
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obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o
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+obj-$(CONFIG_ARM_ARMADA_37XX_CPUFREQ) += armada-37xx-cpufreq.o
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obj-$(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ) += brcmstb-avs-cpufreq.o
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obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o
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obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
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--- /dev/null
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+++ b/drivers/cpufreq/armada-37xx-cpufreq.c
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@@ -0,0 +1,241 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * CPU frequency scaling support for Armada 37xx platform.
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+ *
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+ * Copyright (C) 2017 Marvell
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+ *
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+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/cpu.h>
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+#include <linux/cpufreq.h>
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+#include <linux/err.h>
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+#include <linux/interrupt.h>
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+#include <linux/io.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/module.h>
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+#include <linux/of_address.h>
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+#include <linux/of_device.h>
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+#include <linux/of_irq.h>
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+#include <linux/platform_device.h>
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+#include <linux/pm_opp.h>
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+#include <linux/regmap.h>
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+#include <linux/slab.h>
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+
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+/* Power management in North Bridge register set */
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+#define ARMADA_37XX_NB_L0L1 0x18
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+#define ARMADA_37XX_NB_L2L3 0x1C
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+#define ARMADA_37XX_NB_TBG_DIV_OFF 13
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+#define ARMADA_37XX_NB_TBG_DIV_MASK 0x7
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+#define ARMADA_37XX_NB_CLK_SEL_OFF 11
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+#define ARMADA_37XX_NB_CLK_SEL_MASK 0x1
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+#define ARMADA_37XX_NB_CLK_SEL_TBG 0x1
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+#define ARMADA_37XX_NB_TBG_SEL_OFF 9
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+#define ARMADA_37XX_NB_TBG_SEL_MASK 0x3
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+#define ARMADA_37XX_NB_VDD_SEL_OFF 6
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+#define ARMADA_37XX_NB_VDD_SEL_MASK 0x3
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+#define ARMADA_37XX_NB_CONFIG_SHIFT 16
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+#define ARMADA_37XX_NB_DYN_MOD 0x24
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+#define ARMADA_37XX_NB_CLK_SEL_EN BIT(26)
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+#define ARMADA_37XX_NB_TBG_EN BIT(28)
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+#define ARMADA_37XX_NB_DIV_EN BIT(29)
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+#define ARMADA_37XX_NB_VDD_EN BIT(30)
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+#define ARMADA_37XX_NB_DFS_EN BIT(31)
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+#define ARMADA_37XX_NB_CPU_LOAD 0x30
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+#define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3
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+#define ARMADA_37XX_DVFS_LOAD_0 0
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+#define ARMADA_37XX_DVFS_LOAD_1 1
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+#define ARMADA_37XX_DVFS_LOAD_2 2
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+#define ARMADA_37XX_DVFS_LOAD_3 3
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+
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+/*
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+ * On Armada 37xx the Power management manages 4 level of CPU load,
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+ * each level can be associated with a CPU clock source, a CPU
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+ * divider, a VDD level, etc...
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+ */
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+#define LOAD_LEVEL_NR 4
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+
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+struct armada_37xx_dvfs {
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+ u32 cpu_freq_max;
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+ u8 divider[LOAD_LEVEL_NR];
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+};
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+
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+static struct armada_37xx_dvfs armada_37xx_dvfs[] = {
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+ {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
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+ {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
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+ {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
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+ {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
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+};
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+
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+static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq)
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+{
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(armada_37xx_dvfs); i++) {
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+ if (freq == armada_37xx_dvfs[i].cpu_freq_max)
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+ return &armada_37xx_dvfs[i];
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+ }
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+
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+ pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000);
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+ return NULL;
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+}
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+
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+/*
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+ * Setup the four level managed by the hardware. Once the four level
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+ * will be configured then the DVFS will be enabled.
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+ */
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+static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
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+ struct clk *clk, u8 *divider)
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+{
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+ int load_lvl;
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+ struct clk *parent;
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+
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+ for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
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+ unsigned int reg, mask, val, offset = 0;
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+
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+ if (load_lvl <= ARMADA_37XX_DVFS_LOAD_1)
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+ reg = ARMADA_37XX_NB_L0L1;
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+ else
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+ reg = ARMADA_37XX_NB_L2L3;
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+
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+ if (load_lvl == ARMADA_37XX_DVFS_LOAD_0 ||
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+ load_lvl == ARMADA_37XX_DVFS_LOAD_2)
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+ offset += ARMADA_37XX_NB_CONFIG_SHIFT;
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+
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+ /* Set cpu clock source, for all the level we use TBG */
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+ val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF;
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+ mask = (ARMADA_37XX_NB_CLK_SEL_MASK
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+ << ARMADA_37XX_NB_CLK_SEL_OFF);
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+
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+ /*
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+ * Set cpu divider based on the pre-computed array in
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+ * order to have balanced step.
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+ */
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+ val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
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+ mask |= (ARMADA_37XX_NB_TBG_DIV_MASK
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+ << ARMADA_37XX_NB_TBG_DIV_OFF);
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+
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+ /* Set VDD divider which is actually the load level. */
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+ val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF;
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+ mask |= (ARMADA_37XX_NB_VDD_SEL_MASK
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+ << ARMADA_37XX_NB_VDD_SEL_OFF);
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+
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+ val <<= offset;
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+ mask <<= offset;
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+
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+ regmap_update_bits(base, reg, mask, val);
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+ }
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+
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+ /*
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+ * Set cpu clock source, for all the level we keep the same
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+ * clock source that the one already configured. For this one
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+ * we need to use the clock framework
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+ */
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+ parent = clk_get_parent(clk);
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+ clk_set_parent(clk, parent);
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+}
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+
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+static void __init armada37xx_cpufreq_disable_dvfs(struct regmap *base)
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+{
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+ unsigned int reg = ARMADA_37XX_NB_DYN_MOD,
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+ mask = ARMADA_37XX_NB_DFS_EN;
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+
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+ regmap_update_bits(base, reg, mask, 0);
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+}
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+
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+static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base)
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+{
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+ unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD,
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+ mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
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+
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+ /* Start with the highest load (0) */
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+ val = ARMADA_37XX_DVFS_LOAD_0;
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+ regmap_update_bits(base, reg, mask, val);
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+
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+ /* Now enable DVFS for the CPUs */
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+ reg = ARMADA_37XX_NB_DYN_MOD;
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+ mask = ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN |
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+ ARMADA_37XX_NB_DIV_EN | ARMADA_37XX_NB_VDD_EN |
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+ ARMADA_37XX_NB_DFS_EN;
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+
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+ regmap_update_bits(base, reg, mask, mask);
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+}
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+
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+static int __init armada37xx_cpufreq_driver_init(void)
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+{
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+ struct armada_37xx_dvfs *dvfs;
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+ struct platform_device *pdev;
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+ unsigned int cur_frequency;
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+ struct regmap *nb_pm_base;
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+ struct device *cpu_dev;
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+ int load_lvl, ret;
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+ struct clk *clk;
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+
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+ nb_pm_base =
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+ syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
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+
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+ if (IS_ERR(nb_pm_base))
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+ return -ENODEV;
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+
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+ /* Before doing any configuration on the DVFS first, disable it */
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+ armada37xx_cpufreq_disable_dvfs(nb_pm_base);
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+
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+ /*
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+ * On CPU 0 register the operating points supported (which are
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+ * the nominal CPU frequency and full integer divisions of
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+ * it).
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+ */
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+ cpu_dev = get_cpu_device(0);
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+ if (!cpu_dev) {
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+ dev_err(cpu_dev, "Cannot get CPU\n");
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+ return -ENODEV;
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+ }
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+
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+ clk = clk_get(cpu_dev, 0);
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+ if (IS_ERR(clk)) {
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+ dev_err(cpu_dev, "Cannot get clock for CPU0\n");
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+ return PTR_ERR(clk);
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+ }
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+
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+ /* Get nominal (current) CPU frequency */
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+ cur_frequency = clk_get_rate(clk);
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+ if (!cur_frequency) {
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+ dev_err(cpu_dev, "Failed to get clock rate for CPU\n");
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+ return -EINVAL;
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+ }
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+
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+ dvfs = armada_37xx_cpu_freq_info_get(cur_frequency);
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+ if (!dvfs)
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+ return -EINVAL;
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+
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+ armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
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+
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+ for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
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+ load_lvl++) {
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+ unsigned long freq = cur_frequency / dvfs->divider[load_lvl];
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+
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+ ret = dev_pm_opp_add(cpu_dev, freq, 0);
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+ if (ret) {
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+ /* clean-up the already added opp before leaving */
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+ while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
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+ freq = cur_frequency / dvfs->divider[load_lvl];
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+ dev_pm_opp_remove(cpu_dev, freq);
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+ }
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+ return ret;
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+ }
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+ }
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+
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+ /* Now that everything is setup, enable the DVFS at hardware level */
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+ armada37xx_cpufreq_enable_dvfs(nb_pm_base);
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+
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+ pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
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+
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+ return PTR_ERR_OR_ZERO(pdev);
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+}
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+/* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
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+late_initcall(armada37xx_cpufreq_driver_init);
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+
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+MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
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+MODULE_DESCRIPTION("Armada 37xx cpufreq driver");
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+MODULE_LICENSE("GPL");
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