mirror of https://github.com/hak5/openwrt.git
214 lines
5.8 KiB
Diff
214 lines
5.8 KiB
Diff
From 4d7dc77babfef1d6cb8fd825e2f17dc3384c3272 Mon Sep 17 00:00:00 2001
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From: Stephen Boyd <sboyd@codeaurora.org>
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Date: Tue, 14 Aug 2018 17:42:26 +0530
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Subject: [PATCH 07/12] clk: qcom: Add support for Krait clocks
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The Krait clocks are made up of a series of muxes and a divider
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that choose between a fixed rate clock and dedicated HFPLLs for
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each CPU. Instead of using mmio accesses to remux parents, the
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Krait implementation exposes the remux control via cp15
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registers. Support these clocks.
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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Tested-by: Craig Tatlor <ctatlor97@gmail.com>
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[sboyd@kernel.org: Move hidden config to top outside of the visible qcom
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config zone so that menuconfig looks nice]
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/qcom/Kconfig | 4 ++
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drivers/clk/qcom/Makefile | 1 +
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drivers/clk/qcom/clk-krait.c | 124 +++++++++++++++++++++++++++++++++++
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drivers/clk/qcom/clk-krait.h | 37 +++++++++++
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4 files changed, 166 insertions(+)
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create mode 100644 drivers/clk/qcom/clk-krait.c
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create mode 100644 drivers/clk/qcom/clk-krait.h
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--- a/drivers/clk/qcom/Kconfig
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+++ b/drivers/clk/qcom/Kconfig
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@@ -1,3 +1,7 @@
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+config KRAIT_CLOCKS
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+ bool
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+ select KRAIT_L2_ACCESSORS
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+
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config QCOM_GDSC
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bool
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select PM_GENERIC_DOMAINS if PM
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--- a/drivers/clk/qcom/Makefile
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+++ b/drivers/clk/qcom/Makefile
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@@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
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clk-qcom-y += clk-regmap-divider.o
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clk-qcom-y += clk-regmap-mux.o
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clk-qcom-y += clk-regmap-mux-div.o
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+clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
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clk-qcom-y += clk-hfpll.o
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clk-qcom-y += reset.o
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clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
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--- /dev/null
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+++ b/drivers/clk/qcom/clk-krait.c
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@@ -0,0 +1,124 @@
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+// SPDX-License-Identifier: GPL-2.0
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+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/delay.h>
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+#include <linux/err.h>
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+#include <linux/clk-provider.h>
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+#include <linux/spinlock.h>
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+
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+#include <asm/krait-l2-accessors.h>
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+
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+#include "clk-krait.h"
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+
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+/* Secondary and primary muxes share the same cp15 register */
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+static DEFINE_SPINLOCK(krait_clock_reg_lock);
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+
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+#define LPL_SHIFT 8
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+static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
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+{
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+ unsigned long flags;
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+ u32 regval;
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+
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+ spin_lock_irqsave(&krait_clock_reg_lock, flags);
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+ regval = krait_get_l2_indirect_reg(mux->offset);
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+ regval &= ~(mux->mask << mux->shift);
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+ regval |= (sel & mux->mask) << mux->shift;
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+ if (mux->lpl) {
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+ regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
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+ regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
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+ }
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+ krait_set_l2_indirect_reg(mux->offset, regval);
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+ spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
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+
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+ /* Wait for switch to complete. */
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+ mb();
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+ udelay(1);
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+}
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+
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+static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
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+{
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+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
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+ u32 sel;
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+
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+ sel = clk_mux_reindex(index, mux->parent_map, 0);
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+ mux->en_mask = sel;
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+ /* Don't touch mux if CPU is off as it won't work */
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+ if (__clk_is_enabled(hw->clk))
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+ __krait_mux_set_sel(mux, sel);
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+
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+ return 0;
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+}
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+
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+static u8 krait_mux_get_parent(struct clk_hw *hw)
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+{
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+ struct krait_mux_clk *mux = to_krait_mux_clk(hw);
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+ u32 sel;
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+
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+ sel = krait_get_l2_indirect_reg(mux->offset);
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+ sel >>= mux->shift;
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+ sel &= mux->mask;
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+ mux->en_mask = sel;
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+
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+ return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
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+}
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+
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+const struct clk_ops krait_mux_clk_ops = {
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+ .set_parent = krait_mux_set_parent,
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+ .get_parent = krait_mux_get_parent,
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+ .determine_rate = __clk_mux_determine_rate_closest,
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+};
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+EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
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+
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+/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
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+static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long *parent_rate)
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+{
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+ *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
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+ return DIV_ROUND_UP(*parent_rate, 2);
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+}
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+
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+static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long parent_rate)
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+{
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+ struct krait_div2_clk *d = to_krait_div2_clk(hw);
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+ unsigned long flags;
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+ u32 val;
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+ u32 mask = BIT(d->width) - 1;
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+
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+ if (d->lpl)
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+ mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
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+
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+ spin_lock_irqsave(&krait_clock_reg_lock, flags);
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+ val = krait_get_l2_indirect_reg(d->offset);
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+ val &= ~mask;
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+ krait_set_l2_indirect_reg(d->offset, val);
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+ spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
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+
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+ return 0;
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+}
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+
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+static unsigned long
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+krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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+{
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+ struct krait_div2_clk *d = to_krait_div2_clk(hw);
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+ u32 mask = BIT(d->width) - 1;
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+ u32 div;
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+
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+ div = krait_get_l2_indirect_reg(d->offset);
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+ div >>= d->shift;
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+ div &= mask;
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+ div = (div + 1) * 2;
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+
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+ return DIV_ROUND_UP(parent_rate, div);
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+}
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+
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+const struct clk_ops krait_div2_clk_ops = {
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+ .round_rate = krait_div2_round_rate,
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+ .set_rate = krait_div2_set_rate,
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+ .recalc_rate = krait_div2_recalc_rate,
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+};
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+EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
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--- /dev/null
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+++ b/drivers/clk/qcom/clk-krait.h
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@@ -0,0 +1,37 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+
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+#ifndef __QCOM_CLK_KRAIT_H
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+#define __QCOM_CLK_KRAIT_H
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+
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+#include <linux/clk-provider.h>
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+
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+struct krait_mux_clk {
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+ unsigned int *parent_map;
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+ u32 offset;
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+ u32 mask;
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+ u32 shift;
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+ u32 en_mask;
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+ bool lpl;
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+
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+ struct clk_hw hw;
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+ struct notifier_block clk_nb;
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+};
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+
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+#define to_krait_mux_clk(_hw) container_of(_hw, struct krait_mux_clk, hw)
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+
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+extern const struct clk_ops krait_mux_clk_ops;
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+
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+struct krait_div2_clk {
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+ u32 offset;
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+ u8 width;
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+ u32 shift;
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+ bool lpl;
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+
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+ struct clk_hw hw;
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+};
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+
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+#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw)
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+
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+extern const struct clk_ops krait_div2_clk_ops;
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+
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+#endif
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