mirror of https://github.com/hak5/openwrt.git
144 lines
3.6 KiB
C
144 lines
3.6 KiB
C
/* CF-mips driver
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This is a block driver for the direct (mmaped) interface to the CF-slot,
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found in Routerboard.com's RB532 board
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See SDK provided from routerboard.com.
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Module adapted By P.Christeas <p_christeas@yahoo.com>, 2005-6.
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Cleaned up and adapted to platform_device by Felix Fietkau <nbd@openwrt.org>
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This work is redistributed under the terms of the GNU General Public License.
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*/
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#ifndef __CFMIPS_ATA_H__
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#define __CFMIPS_ATA_H__
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#include <linux/interrupt.h>
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#define CFG_DC_DEV1 (void*)0xb8010010
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#define CFG_DC_DEVBASE 0x0
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#define CFG_DC_DEVMASK 0x4
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#define CFG_DC_DEVC 0x8
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#define CFG_DC_DEVTC 0xC
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#define CFDEV_BUF_SIZE 0x1000
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#define ATA_CIS_OFFSET 0x200
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#define ATA_REG_OFFSET 0x800
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#define ATA_DBUF_OFFSET 0xC00
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#define ATA_REG_FEAT 0x1
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#define ATA_REG_SC 0x2
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#define ATA_REG_SN 0x3
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#define ATA_REG_CL 0x4
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#define ATA_REG_CH 0x5
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#define ATA_REG_DH 0x6
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#define ATA_REG_DH_BASE 0xa0
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#define ATA_REG_DH_LBA 0x40
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#define ATA_REG_DH_DRV 0x10
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#define ATA_REG_CMD 0x7
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#define ATA_REG_ST 0x7
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#define ATA_REG_ST_BUSY 0x80
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#define ATA_REG_ST_RDY 0x40
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#define ATA_REG_ST_DWF 0x20
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#define ATA_REG_ST_DSC 0x10
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#define ATA_REG_ST_DRQ 0x08
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#define ATA_REG_ST_CORR 0x04
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#define ATA_REG_ST_ERR 0x01
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#define ATA_REG_ERR 0xd
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#define ATA_REG_DC 0xe
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#define ATA_REG_DC_IEN 0x02
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#define ATA_REG_DC_SRST 0x04
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#define ATA_CMD_READ_SECTORS 0x20
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#define ATA_CMD_WRITE_SECTORS 0x30
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#define ATA_CMD_EXEC_DRIVE_DIAG 0x90
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#define ATA_CMD_READ_MULTIPLE 0xC4
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#define ATA_CMD_WRITE_MULTIPLE 0xC5
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#define ATA_CMD_SET_MULTIPLE 0xC6
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#define ATA_CMD_IDENTIFY_DRIVE 0xEC
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#define ATA_CMD_SET_FEATURES 0xEF
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#define ATA_FEATURE_ENABLE_APM 0x05
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#define ATA_FEATURE_DISABLE_APM 0x85
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#define ATA_APM_DISABLED 0x00
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#define ATA_APM_MIN_POWER 0x01
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#define ATA_APM_WITH_STANDBY 0x7f
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#define ATA_APM_WITHOUT_STANDBY 0x80
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#define ATA_APM_MAX_PERFORMANCE 0xfe
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#define CF_SECT_SIZE 0x200
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/* That is the ratio CF_SECT_SIZE/512 (the kernel sector size) */
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#define CF_KERNEL_MUL 1
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#define ATA_MAX_SECT_PER_CMD 0x100
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#define CF_TRANS_FAILED 0
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#define CF_TRANS_OK 1
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#define CF_TRANS_IN_PROGRESS 2
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enum trans_state {
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TS_IDLE = 0,
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TS_AFTER_RESET,
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TS_READY,
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TS_CMD,
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TS_TRANS
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};
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//
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// #if DEBUG
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// static unsigned long busy_time;
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// #endif
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/** Struct to hold the cfdev
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Actually, all the data here only has one instance. However, for
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reasons of programming conformity, it is passed around as a pointer
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*/
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struct cf_mips_dev {
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void *base; /* base address for I/O */
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void *baddr; /* remapped address */
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int pin; /* gpio pin */
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int irq; /* gpio irq */
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unsigned head;
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unsigned cyl;
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unsigned spt;
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unsigned sectors;
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unsigned short block_size;
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unsigned dtype ; // ATA or CF
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struct request_queue *queue;
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struct gendisk *gd;
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/* Transaction state */
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enum trans_state tstate;
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char *tbuf;
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unsigned long tbuf_size;
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sector_t tsect_start;
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unsigned tsector_count;
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unsigned tsectors_left;
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int tread;
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unsigned tcmd;
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int async_mode;
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unsigned long irq_enable_time;
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struct request *active_req; /* A request is being carried out. Is that different from tstate? */
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int users;
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struct timer_list to_timer;
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struct tasklet_struct tasklet;
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/** This lock ensures that the requests to this device are all done
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atomically. Transfers can run in parallel, requests are all queued
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one-by-one */
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spinlock_t lock;
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};
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int cf_do_transfer(struct cf_mips_dev* dev,sector_t sector, unsigned long nsect,
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char* buffer, int is_write);
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int cf_init(struct cf_mips_dev* dev);
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void cf_cleanup(struct cf_mips_dev* dev);
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void cf_async_trans_done(struct cf_mips_dev* dev, int result);
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// void *cf_get_next_buf(unsigned long *buf_size);
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#endif
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