mirror of https://github.com/hak5/openwrt.git
1339 lines
33 KiB
Diff
1339 lines
33 KiB
Diff
From 45ba5bb2bdc9462fe5998aeb75e2c7e33b56c9fb Mon Sep 17 00:00:00 2001
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From: Zhao Qiang <qiang.zhao@nxp.com>
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Date: Mon, 7 Nov 2016 10:23:52 +0800
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Subject: [PATCH 227/238] ls2088a/dts: add ls2088a dts
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Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
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---
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arch/arm64/boot/dts/freescale/Makefile | 2 +
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arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 241 ++++++
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arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 207 +++++
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arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 854 +++++++++++++++++++++
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4 files changed, 1304 insertions(+)
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
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--- a/arch/arm64/boot/dts/freescale/Makefile
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+++ b/arch/arm64/boot/dts/freescale/Makefile
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@@ -6,6 +6,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
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+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
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+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
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@@ -0,0 +1,241 @@
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+/*
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+ * Device Tree file for Freescale LS2080a QDS Board
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+ *
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+ * Copyright (C) 2016, Freescale Semiconductor
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+ *
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+ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+/dts-v1/;
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+
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+#include "fsl-ls2088a.dtsi"
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+
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+/ {
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+ model = "Freescale Layerscape 2088a QDS Board";
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+ compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
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+};
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+
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+&esdhc {
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+ status = "okay";
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+};
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+
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+&ifc {
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+ status = "okay";
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ ranges = <0x0 0x0 0x5 0x80000000 0x08000000
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+ 0x2 0x0 0x5 0x30000000 0x00010000
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+ 0x3 0x0 0x5 0x20000000 0x00010000>;
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+
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+ nor@0,0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "cfi-flash";
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+ reg = <0x0 0x0 0x8000000>;
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+ bank-width = <2>;
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+ device-width = <1>;
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+ };
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+
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+ nand@2,0 {
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+ compatible = "fsl,ifc-nand";
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+ reg = <0x2 0x0 0x10000>;
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+ };
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+
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+ cpld@3,0 {
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+ reg = <0x3 0x0 0x10000>;
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+ compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis",
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+ "fsl,fpga-qixis";
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+ };
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+};
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+
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+&ftm0 {
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+ pca9547@77 {
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+ compatible = "nxp,pca9547";
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+ reg = <0x77>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ i2c@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x00>;
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+ rtc@68 {
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+ compatible = "dallas,ds3232";
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+ reg = <0x68>;
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+ };
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+ };
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+
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+ i2c@2 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x02>;
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+
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+ ina220@40 {
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+ compatible = "ti,ina220";
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+ reg = <0x40>;
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+ shunt-resistor = <500>;
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+ };
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+ ina220@41 {
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+ compatible = "ti,ina220";
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+ reg = <0x41>;
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+ shunt-resistor = <1000>;
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+ };
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+ };
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+
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+ i2c@3 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x3>;
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+
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+ adt7481@4c {
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+ compatible = "adi,adt7461";
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+ reg = <0x4c>;
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+ };
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+ };
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+ };
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+};
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+
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+&i2c1 {
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+ status = "disabled";
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+};
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+
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+&i2c2 {
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+ status = "disabled";
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+};
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+
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+&i2c3 {
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+ status = "disabled";
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+};
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+
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+&dspi {
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+ status = "okay";
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+ dflash0: n25q128a {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "st,m25p80";
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+ spi-max-frequency = <3000000>;
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+ reg = <0>;
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+ };
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+ dflash1: sst25wf040b {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "st,m25p80";
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+ spi-max-frequency = <3000000>;
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+ reg = <1>;
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+ };
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+ dflash2: en25s64 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "st,m25p80";
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+ spi-max-frequency = <3000000>;
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+ reg = <2>;
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+ };
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+};
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+
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+&qspi {
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+ status = "okay";
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+ qflash0: s25fs256s1@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "st,m25p80";
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+ spi-max-frequency = <20000000>;
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+ m25p,fast-read;
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+ reg = <0>;
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+ };
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+
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+ qflash2: s25fs256s1@2 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "st,m25p80";
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+ spi-max-frequency = <20000000>;
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+ m25p,fast-read;
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+ reg = <2>;
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+ };
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+};
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+
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+&sata0 {
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+ status = "okay";
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+};
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+
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+&sata1 {
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+ status = "okay";
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+};
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+
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+&usb0 {
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+ status = "okay";
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+};
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+
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+&usb1 {
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+ status = "okay";
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+};
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+
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+&ifc {
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+ boardctrl: board-control@3,0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
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+ reg = <3 0 0x300>; /* TODO check address */
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+ ranges = <0 3 0 0x300>;
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+
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+ mdio_mux_emi1 {
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+ compatible = "mdio-mux-mmioreg", "mdio-mux";
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+ mdio-parent-bus = <&emdio1>;
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+ reg = <0x54 1>; /* BRDCFG4 */
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+ mux-mask = <0xe0>; /* EMI1_MDIO */
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+
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+ #address-cells=<1>;
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+ #size-cells = <0>;
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+
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+ /* Child MDIO buses, one for each riser card:
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+ reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
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+
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+ VSC8234 PHYs on the riser cards.
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+ */
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+
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+ mdio_mux3: mdio@60 {
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+ reg = <0x60>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mdio0_phy12: mdio_phy0@1c {
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+ reg = <0x1c>;
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+ phy-connection-type = "sgmii";
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+ };
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+ mdio0_phy13: mdio_phy1@1d {
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+ reg = <0x1d>;
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+ phy-connection-type = "sgmii";
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+ };
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+ mdio0_phy14: mdio_phy2@1e {
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+ reg = <0x1e>;
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+ phy-connection-type = "sgmii";
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+ };
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+ mdio0_phy15: mdio_phy3@1f {
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+ reg = <0x1f>;
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+ phy-connection-type = "sgmii";
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+ };
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+ };
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+ };
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+ };
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+};
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+
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+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
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+&dpmac9 {
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+ phy-handle = <&mdio0_phy12>;
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+};
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+&dpmac10 {
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+ phy-handle = <&mdio0_phy13>;
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+};
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+&dpmac11 {
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+ phy-handle = <&mdio0_phy14>;
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+};
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+&dpmac12 {
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+ phy-handle = <&mdio0_phy15>;
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+};
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
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@@ -0,0 +1,207 @@
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+/*
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+ * Device Tree file for Freescale LS2080a RDB board
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+ *
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+ * Copyright (C) 2015, Freescale Semiconductor
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+ *
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+ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
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+ *
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+ * This file is licensed under the terms of the GNU General Public
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+ * License version 2. This program is licensed "as is" without any
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+ * warranty of any kind, whether express or implied.
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+ */
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+
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+/dts-v1/;
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+
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+#include "fsl-ls2088a.dtsi"
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+
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+/ {
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+ model = "Freescale Layerscape 2088a RDB Board";
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+ compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
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+};
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+
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+&esdhc {
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+ status = "okay";
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+};
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+
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+&ifc {
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+ status = "okay";
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ ranges = <0x0 0x0 0x5 0x80000000 0x08000000
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+ 0x2 0x0 0x5 0x30000000 0x00010000
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+ 0x3 0x0 0x5 0x20000000 0x00010000>;
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+
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+ nor@0,0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "cfi-flash";
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+ reg = <0x0 0x0 0x8000000>;
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+ bank-width = <2>;
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+ device-width = <1>;
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+ };
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+
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+ nand@2,0 {
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+ compatible = "fsl,ifc-nand";
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+ reg = <0x2 0x0 0x10000>;
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+ };
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+
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+ cpld@3,0 {
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+ reg = <0x3 0x0 0x10000>;
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+ compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis",
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+ "fsl,fpga-qixis";
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+ };
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+};
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+
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+&ftm0 {
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+ status = "okay";
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+};
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+
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+&i2c0 {
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+ status = "okay";
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+ pca9547@75 {
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+ compatible = "nxp,pca9547";
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+ reg = <0x75>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ i2c-mux-never-disable;
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+ i2c@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x01>;
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+ rtc@68 {
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+ compatible = "dallas,ds3232";
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+ reg = <0x68>;
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+ };
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+ };
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+
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+ i2c@3 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x3>;
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+
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+ adt7481@4c {
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+ compatible = "adi,adt7461";
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+ reg = <0x4c>;
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+ };
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+ };
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+ };
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+};
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+
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+&i2c1 {
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+ status = "disabled";
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+};
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+
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+&i2c2 {
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+ status = "disabled";
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+};
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+
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+&i2c3 {
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+ status = "disabled";
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+};
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+
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+&dspi {
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+ status = "okay";
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+ dflash0: n25q512a {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "st,m25p80";
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+ spi-max-frequency = <3000000>;
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+ reg = <0>;
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+ };
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+};
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+
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+&qspi {
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+ status = "disabled";
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+};
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+
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+&sata0 {
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+ status = "okay";
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+};
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+
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+&sata1 {
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+ status = "okay";
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+};
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+
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+&usb0 {
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+ status = "okay";
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+};
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+
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+&usb1 {
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+ status = "okay";
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+};
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+
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+&emdio1 {
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+ /* CS4340 PHYs */
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+ mdio1_phy1: emdio1_phy@1 {
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+ reg = <0x10>;
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+ phy-connection-type = "xfi";
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+ };
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+ mdio1_phy2: emdio1_phy@2 {
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+ reg = <0x11>;
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+ phy-connection-type = "xfi";
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+ };
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+ mdio1_phy3: emdio1_phy@3 {
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+ reg = <0x12>;
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+ phy-connection-type = "xfi";
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+ };
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+ mdio1_phy4: emdio1_phy@4 {
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+ reg = <0x13>;
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+ phy-connection-type = "xfi";
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+ };
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+};
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+
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+&emdio2 {
|
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+ /* AQR405 PHYs */
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+ mdio2_phy1: emdio2_phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c45";
|
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+ interrupts = <0 1 0x4>; /* Level high type */
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+ reg = <0x0>;
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+ phy-connection-type = "xfi";
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+ };
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+ mdio2_phy2: emdio2_phy@2 {
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ interrupts = <0 2 0x4>; /* Level high type */
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+ reg = <0x1>;
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+ phy-connection-type = "xfi";
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+ };
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+ mdio2_phy3: emdio2_phy@3 {
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ interrupts = <0 4 0x4>; /* Level high type */
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+ reg = <0x2>;
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+ phy-connection-type = "xfi";
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+ };
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+ mdio2_phy4: emdio2_phy@4 {
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+ compatible = "ethernet-phy-ieee802.3-c45";
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+ interrupts = <0 5 0x4>; /* Level high type */
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+ reg = <0x3>;
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+ phy-connection-type = "xfi";
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+ };
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+};
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+
|
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+/* Update DPMAC connections to external PHYs, under the assumption of
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+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
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+ */
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+&dpmac1 {
|
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+ phy-handle = <&mdio1_phy1>;
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+};
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+&dpmac2 {
|
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+ phy-handle = <&mdio1_phy2>;
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+};
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+&dpmac3 {
|
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+ phy-handle = <&mdio1_phy3>;
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+};
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+&dpmac4 {
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+ phy-handle = <&mdio1_phy4>;
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+};
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+&dpmac5 {
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+ phy-handle = <&mdio2_phy1>;
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+};
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+&dpmac6 {
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+ phy-handle = <&mdio2_phy2>;
|
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+};
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+&dpmac7 {
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+ phy-handle = <&mdio2_phy3>;
|
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+};
|
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+&dpmac8 {
|
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+ phy-handle = <&mdio2_phy4>;
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+};
|
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--- /dev/null
|
|
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
|
|
@@ -0,0 +1,854 @@
|
|
+/*
|
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+ * Device Tree Include file for Freescale Layerscape-2088A family SoC.
|
|
+ *
|
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+ * Copyright (C) 2016, Freescale Semiconductor
|
|
+ *
|
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+ * Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
|
+ *
|
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+ * This file is dual-licensed: you can use it either under the terms
|
|
+ * of the GPLv2 or the X11 license, at your option. Note that this dual
|
|
+ * licensing only applies to this file, and not this project as a
|
|
+ * whole.
|
|
+ *
|
|
+ * a) This library is free software; you can redistribute it and/or
|
|
+ * modify it under the terms of the GNU General Public License as
|
|
+ * published by the Free Software Foundation; either version 2 of the
|
|
+ * License, or (at your option) any later version.
|
|
+ *
|
|
+ * This library is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * Or, alternatively,
|
|
+ *
|
|
+ * b) Permission is hereby granted, free of charge, to any person
|
|
+ * obtaining a copy of this software and associated documentation
|
|
+ * files (the "Software"), to deal in the Software without
|
|
+ * restriction, including without limitation the rights to use,
|
|
+ * copy, modify, merge, publish, distribute, sublicense, and/or
|
|
+ * sell copies of the Software, and to permit persons to whom the
|
|
+ * Software is furnished to do so, subject to the following
|
|
+ * conditions:
|
|
+ *
|
|
+ * The above copyright notice and this permission notice shall be
|
|
+ * included in all copies or substantial portions of the Software.
|
|
+ *
|
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
|
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
|
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
|
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
|
+ * OTHER DEALINGS IN THE SOFTWARE.
|
|
+ */
|
|
+
|
|
+#include <dt-bindings/thermal/thermal.h>
|
|
+
|
|
+/memreserve/ 0x80000000 0x00010000;
|
|
+
|
|
+/ {
|
|
+ compatible = "fsl,ls2088a";
|
|
+ interrupt-parent = <&gic>;
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+
|
|
+ cpus {
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ cpu0: cpu@0 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a72";
|
|
+ reg = <0x0 0x0>;
|
|
+ clocks = <&clockgen 1 0>;
|
|
+ #cooling-cells = <2>;
|
|
+ cpu-idle-states = <&CPU_PW20>;
|
|
+ };
|
|
+
|
|
+ cpu1: cpu@1 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a72";
|
|
+ reg = <0x0 0x1>;
|
|
+ clocks = <&clockgen 1 0>;
|
|
+ cpu-idle-states = <&CPU_PW20>;
|
|
+ };
|
|
+
|
|
+ cpu2: cpu@100 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a72";
|
|
+ reg = <0x0 0x100>;
|
|
+ clocks = <&clockgen 1 1>;
|
|
+ #cooling-cells = <2>;
|
|
+ cpu-idle-states = <&CPU_PW20>;
|
|
+ };
|
|
+
|
|
+ cpu3: cpu@101 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a72";
|
|
+ reg = <0x0 0x101>;
|
|
+ clocks = <&clockgen 1 1>;
|
|
+ cpu-idle-states = <&CPU_PW20>;
|
|
+ };
|
|
+
|
|
+ cpu4: cpu@200 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a72";
|
|
+ reg = <0x0 0x200>;
|
|
+ clocks = <&clockgen 1 2>;
|
|
+ #cooling-cells = <2>;
|
|
+ cpu-idle-states = <&CPU_PW20>;
|
|
+ };
|
|
+
|
|
+ cpu5: cpu@201 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a72";
|
|
+ reg = <0x0 0x201>;
|
|
+ clocks = <&clockgen 1 2>;
|
|
+ cpu-idle-states = <&CPU_PW20>;
|
|
+ };
|
|
+
|
|
+ cpu6: cpu@300 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a72";
|
|
+ reg = <0x0 0x300>;
|
|
+ clocks = <&clockgen 1 3>;
|
|
+ #cooling-cells = <2>;
|
|
+ cpu-idle-states = <&CPU_PW20>;
|
|
+ };
|
|
+
|
|
+ cpu7: cpu@301 {
|
|
+ device_type = "cpu";
|
|
+ compatible = "arm,cortex-a72";
|
|
+ reg = <0x0 0x301>;
|
|
+ clocks = <&clockgen 1 3>;
|
|
+ cpu-idle-states = <&CPU_PW20>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pmu {
|
|
+ compatible = "arm,armv8-pmuv3";
|
|
+ interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
|
|
+ };
|
|
+
|
|
+ idle-states {
|
|
+ entry-method = "arm,psci";
|
|
+
|
|
+ CPU_PW20: cpu-pw20 {
|
|
+ compatible = "arm,idle-state";
|
|
+ idle-state-name = "PW20";
|
|
+ arm,psci-suspend-param = <0x00010000>;
|
|
+ entry-latency-us = <2000>;
|
|
+ exit-latency-us = <2000>;
|
|
+ min-residency-us = <6000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ gic: interrupt-controller@6000000 {
|
|
+ compatible = "arm,gic-v3";
|
|
+ reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
|
|
+ <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
|
|
+ <0x0 0x0c0c0000 0 0x2000>, /* GICC */
|
|
+ <0x0 0x0c0d0000 0 0x1000>, /* GICH */
|
|
+ <0x0 0x0c0e0000 0 0x20000>; /* GICV */
|
|
+ #interrupt-cells = <3>;
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ ranges;
|
|
+ interrupt-controller;
|
|
+ interrupts = <1 9 0x4>;
|
|
+
|
|
+ its: gic-its@6020000 {
|
|
+ compatible = "arm,gic-v3-its";
|
|
+ msi-controller;
|
|
+ reg = <0x0 0x6020000 0 0x20000>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ sysclk: sysclk {
|
|
+ compatible = "fixed-clock";
|
|
+ #clock-cells = <0>;
|
|
+ clock-frequency = <100000000>;
|
|
+ clock-output-names = "sysclk";
|
|
+ };
|
|
+
|
|
+ clockgen: clocking@1300000 {
|
|
+ compatible = "fsl,ls2088a-clockgen";
|
|
+ reg = <0 0x1300000 0 0xa0000>;
|
|
+ #clock-cells = <2>;
|
|
+ clocks = <&sysclk>;
|
|
+ };
|
|
+
|
|
+ tmu: tmu@1f80000 {
|
|
+ compatible = "fsl,qoriq-tmu", "fsl,ls2080a-tmu", "fsl,ls2088a-tmu";
|
|
+ reg = <0x0 0x1f80000 0x0 0x10000>;
|
|
+ interrupts = <0 23 0x4>;
|
|
+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
|
|
+ fsl,tmu-calibration = <0x00000000 0x00000026
|
|
+ 0x00000001 0x0000002d
|
|
+ 0x00000002 0x00000032
|
|
+ 0x00000003 0x00000039
|
|
+ 0x00000004 0x0000003f
|
|
+ 0x00000005 0x00000046
|
|
+ 0x00000006 0x0000004d
|
|
+ 0x00000007 0x00000054
|
|
+ 0x00000008 0x0000005a
|
|
+ 0x00000009 0x00000061
|
|
+ 0x0000000a 0x0000006a
|
|
+ 0x0000000b 0x00000071
|
|
+
|
|
+ 0x00010000 0x00000025
|
|
+ 0x00010001 0x0000002c
|
|
+ 0x00010002 0x00000035
|
|
+ 0x00010003 0x0000003d
|
|
+ 0x00010004 0x00000045
|
|
+ 0x00010005 0x0000004e
|
|
+ 0x00010006 0x00000057
|
|
+ 0x00010007 0x00000061
|
|
+ 0x00010008 0x0000006b
|
|
+ 0x00010009 0x00000076
|
|
+
|
|
+ 0x00020000 0x00000029
|
|
+ 0x00020001 0x00000033
|
|
+ 0x00020002 0x0000003d
|
|
+ 0x00020003 0x00000049
|
|
+ 0x00020004 0x00000056
|
|
+ 0x00020005 0x00000061
|
|
+ 0x00020006 0x0000006d
|
|
+
|
|
+ 0x00030000 0x00000021
|
|
+ 0x00030001 0x0000002a
|
|
+ 0x00030002 0x0000003c
|
|
+ 0x00030003 0x0000004e>;
|
|
+ little-endian;
|
|
+ #thermal-sensor-cells = <1>;
|
|
+ };
|
|
+
|
|
+ thermal-zones {
|
|
+ cpu_thermal: cpu-thermal {
|
|
+ polling-delay-passive = <1000>;
|
|
+ polling-delay = <5000>;
|
|
+
|
|
+ thermal-sensors = <&tmu 4>;
|
|
+
|
|
+ trips {
|
|
+ cpu_alert: cpu-alert {
|
|
+ temperature = <75000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "passive";
|
|
+ };
|
|
+ cpu_crit: cpu-crit {
|
|
+ temperature = <85000>;
|
|
+ hysteresis = <2000>;
|
|
+ type = "critical";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ cooling-maps {
|
|
+ map0 {
|
|
+ trip = <&cpu_alert>;
|
|
+ cooling-device =
|
|
+ <&cpu0 THERMAL_NO_LIMIT
|
|
+ THERMAL_NO_LIMIT>;
|
|
+ };
|
|
+ map1 {
|
|
+ trip = <&cpu_alert>;
|
|
+ cooling-device =
|
|
+ <&cpu2 THERMAL_NO_LIMIT
|
|
+ THERMAL_NO_LIMIT>;
|
|
+ };
|
|
+ map2 {
|
|
+ trip = <&cpu_alert>;
|
|
+ cooling-device =
|
|
+ <&cpu4 THERMAL_NO_LIMIT
|
|
+ THERMAL_NO_LIMIT>;
|
|
+ };
|
|
+ map3 {
|
|
+ trip = <&cpu_alert>;
|
|
+ cooling-device =
|
|
+ <&cpu6 THERMAL_NO_LIMIT
|
|
+ THERMAL_NO_LIMIT>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ serial0: serial@21c0500 {
|
|
+ device_type = "serial";
|
|
+ compatible = "fsl,ns16550", "ns16550a";
|
|
+ reg = <0x0 0x21c0500 0x0 0x100>;
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ interrupts = <0 32 0x4>; /* Level high type */
|
|
+ };
|
|
+
|
|
+ serial1: serial@21c0600 {
|
|
+ device_type = "serial";
|
|
+ compatible = "fsl,ns16550", "ns16550a";
|
|
+ reg = <0x0 0x21c0600 0x0 0x100>;
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ interrupts = <0 32 0x4>; /* Level high type */
|
|
+ };
|
|
+ cluster1_core0_watchdog: wdt@c000000 {
|
|
+ compatible = "arm,sp805-wdt", "arm,primecell";
|
|
+ reg = <0x0 0xc000000 0x0 0x1000>;
|
|
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
|
+ clock-names = "apb_pclk", "wdog_clk";
|
|
+ };
|
|
+
|
|
+ cluster1_core1_watchdog: wdt@c010000 {
|
|
+ compatible = "arm,sp805-wdt", "arm,primecell";
|
|
+ reg = <0x0 0xc010000 0x0 0x1000>;
|
|
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
|
+ clock-names = "apb_pclk", "wdog_clk";
|
|
+ };
|
|
+
|
|
+ cluster2_core0_watchdog: wdt@c100000 {
|
|
+ compatible = "arm,sp805-wdt", "arm,primecell";
|
|
+ reg = <0x0 0xc100000 0x0 0x1000>;
|
|
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
|
+ clock-names = "apb_pclk", "wdog_clk";
|
|
+ };
|
|
+
|
|
+ cluster2_core1_watchdog: wdt@c110000 {
|
|
+ compatible = "arm,sp805-wdt", "arm,primecell";
|
|
+ reg = <0x0 0xc110000 0x0 0x1000>;
|
|
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
|
+ clock-names = "apb_pclk", "wdog_clk";
|
|
+ };
|
|
+
|
|
+ cluster3_core0_watchdog: wdt@c200000 {
|
|
+ compatible = "arm,sp805-wdt", "arm,primecell";
|
|
+ reg = <0x0 0xc200000 0x0 0x1000>;
|
|
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
|
+ clock-names = "apb_pclk", "wdog_clk";
|
|
+ };
|
|
+
|
|
+ cluster3_core1_watchdog: wdt@c210000 {
|
|
+ compatible = "arm,sp805-wdt", "arm,primecell";
|
|
+ reg = <0x0 0xc210000 0x0 0x1000>;
|
|
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
|
+ clock-names = "apb_pclk", "wdog_clk";
|
|
+ };
|
|
+
|
|
+ cluster4_core0_watchdog: wdt@c300000 {
|
|
+ compatible = "arm,sp805-wdt", "arm,primecell";
|
|
+ reg = <0x0 0xc300000 0x0 0x1000>;
|
|
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
|
+ clock-names = "apb_pclk", "wdog_clk";
|
|
+ };
|
|
+
|
|
+ cluster4_core1_watchdog: wdt@c310000 {
|
|
+ compatible = "arm,sp805-wdt", "arm,primecell";
|
|
+ reg = <0x0 0xc310000 0x0 0x1000>;
|
|
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
|
+ clock-names = "apb_pclk", "wdog_clk";
|
|
+ };
|
|
+
|
|
+ gpio0: gpio@2300000 {
|
|
+ compatible = "fsl,qoriq-gpio";
|
|
+ reg = <0x0 0x2300000 0x0 0x10000>;
|
|
+ interrupts = <0 36 0x4>; /* Level high type */
|
|
+ gpio-controller;
|
|
+ little-endian;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio1: gpio@2310000 {
|
|
+ compatible = "fsl,qoriq-gpio";
|
|
+ reg = <0x0 0x2310000 0x0 0x10000>;
|
|
+ interrupts = <0 36 0x4>; /* Level high type */
|
|
+ gpio-controller;
|
|
+ little-endian;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio2: gpio@2320000 {
|
|
+ compatible = "fsl,qoriq-gpio";
|
|
+ reg = <0x0 0x2320000 0x0 0x10000>;
|
|
+ interrupts = <0 37 0x4>; /* Level high type */
|
|
+ gpio-controller;
|
|
+ little-endian;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ gpio3: gpio@2330000 {
|
|
+ compatible = "fsl,qoriq-gpio";
|
|
+ reg = <0x0 0x2330000 0x0 0x10000>;
|
|
+ interrupts = <0 37 0x4>; /* Level high type */
|
|
+ gpio-controller;
|
|
+ little-endian;
|
|
+ #gpio-cells = <2>;
|
|
+ interrupt-controller;
|
|
+ #interrupt-cells = <2>;
|
|
+ };
|
|
+
|
|
+ /* TODO: WRIOP (CCSR?) */
|
|
+ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */
|
|
+ compatible = "fsl,fman-memac-mdio";
|
|
+ reg = <0x0 0x8B96000 0x0 0x1000>;
|
|
+ device_type = "mdio"; /* TODO: is this necessary? */
|
|
+ little-endian; /* force the driver in LE mode */
|
|
+
|
|
+ /* Not necessary on the QDS, but needed on the RDB */
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */
|
|
+ compatible = "fsl,fman-memac-mdio";
|
|
+ reg = <0x0 0x8B97000 0x0 0x1000>;
|
|
+ device_type = "mdio"; /* TODO: is this necessary? */
|
|
+ little-endian; /* force the driver in LE mode */
|
|
+
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ };
|
|
+
|
|
+ ifc: ifc@2240000 {
|
|
+ compatible = "fsl,ifc", "simple-bus";
|
|
+ reg = <0x0 0x2240000 0x0 0x20000>;
|
|
+ interrupts = <0 21 0x4>; /* Level high type */
|
|
+ little-endian;
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ ranges = <0 0 0x5 0x80000000 0x08000000
|
|
+ 2 0 0x5 0x30000000 0x00010000
|
|
+ 3 0 0x5 0x20000000 0x00010000>;
|
|
+ };
|
|
+
|
|
+ esdhc: esdhc@2140000 {
|
|
+ compatible = "fsl,ls2088a-esdhc", "fsl,ls2080a-esdhc",
|
|
+ "fsl,esdhc";
|
|
+ reg = <0x0 0x2140000 0x0 0x10000>;
|
|
+ interrupts = <0 28 0x4>; /* Level high type */
|
|
+ clock-frequency = <0>;
|
|
+ voltage-ranges = <1800 1800 3300 3300>;
|
|
+ sdhci,auto-cmd12;
|
|
+ little-endian;
|
|
+ bus-width = <4>;
|
|
+ };
|
|
+
|
|
+ ftm0: ftm0@2800000 {
|
|
+ compatible = "fsl,ftm-alarm";
|
|
+ reg = <0x0 0x2800000 0x0 0x10000>;
|
|
+ interrupts = <0 44 4>;
|
|
+ };
|
|
+
|
|
+ reset: reset@1E60000 {
|
|
+ compatible = "fsl,ls-reset";
|
|
+ reg = <0x0 0x1E60000 0x0 0x10000>;
|
|
+ };
|
|
+
|
|
+ dspi: dspi@2100000 {
|
|
+ compatible = "fsl,ls2088a-dspi", "fsl,ls2085a-dspi",
|
|
+ "fsl,ls2080a-dspi";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x2100000 0x0 0x10000>;
|
|
+ interrupts = <0 26 0x4>; /* Level high type */
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ clock-names = "dspi";
|
|
+ spi-num-chipselects = <5>;
|
|
+ bus-num = <0>;
|
|
+ };
|
|
+
|
|
+ i2c0: i2c@2000000 {
|
|
+ compatible = "fsl,vf610-i2c";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x2000000 0x0 0x10000>;
|
|
+ interrupts = <0 34 0x4>; /* Level high type */
|
|
+ clock-names = "i2c";
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ };
|
|
+
|
|
+ i2c1: i2c@2010000 {
|
|
+ compatible = "fsl,vf610-i2c";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x2010000 0x0 0x10000>;
|
|
+ interrupts = <0 34 0x4>; /* Level high type */
|
|
+ clock-names = "i2c";
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ };
|
|
+
|
|
+ i2c2: i2c@2020000 {
|
|
+ compatible = "fsl,vf610-i2c";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x2020000 0x0 0x10000>;
|
|
+ interrupts = <0 35 0x4>; /* Level high type */
|
|
+ clock-names = "i2c";
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ };
|
|
+
|
|
+ i2c3: i2c@2030000 {
|
|
+ compatible = "fsl,vf610-i2c";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x2030000 0x0 0x10000>;
|
|
+ interrupts = <0 35 0x4>; /* Level high type */
|
|
+ clock-names = "i2c";
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ };
|
|
+
|
|
+ qspi: quadspi@20c0000 {
|
|
+ compatible = "fsl,ls2088a-qspi", "fsl,ls2080a-qspi";
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ reg = <0x0 0x20c0000 0x0 0x10000>,
|
|
+ <0x0 0x20000000 0x0 0x10000000>;
|
|
+ reg-names = "QuadSPI", "QuadSPI-memory";
|
|
+ interrupts = <0 25 0x4>; /* Level high type */
|
|
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
|
|
+ clock-names = "qspi_en", "qspi";
|
|
+ };
|
|
+
|
|
+ pcie1: pcie@3400000 {
|
|
+ compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie",
|
|
+ "fsl,ls2085a-pcie", "snps,dw-pcie";
|
|
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
|
|
+ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
+ reg-names = "regs", "config";
|
|
+ interrupts = <0 108 0x4>; /* Level high type */
|
|
+ interrupt-names = "aer";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ dma-coherent;
|
|
+ fsl,lut_diff;
|
|
+ num-lanes = <4>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
+ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&its>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
|
|
+ <0000 0 0 2 &gic 0 0 0 110 4>,
|
|
+ <0000 0 0 3 &gic 0 0 0 111 4>,
|
|
+ <0000 0 0 4 &gic 0 0 0 112 4>;
|
|
+ };
|
|
+
|
|
+ pcie2: pcie@3500000 {
|
|
+ compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie",
|
|
+ "fsl,ls2085a-pcie", "snps,dw-pcie";
|
|
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
|
|
+ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
+ reg-names = "regs", "config";
|
|
+ interrupts = <0 113 0x4>; /* Level high type */
|
|
+ interrupt-names = "aer";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ dma-coherent;
|
|
+ fsl,lut_diff;
|
|
+ num-lanes = <4>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
+ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&its>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
|
|
+ <0000 0 0 2 &gic 0 0 0 115 4>,
|
|
+ <0000 0 0 3 &gic 0 0 0 116 4>,
|
|
+ <0000 0 0 4 &gic 0 0 0 117 4>;
|
|
+ };
|
|
+
|
|
+ pcie3: pcie@3600000 {
|
|
+ compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie",
|
|
+ "fsl,ls2085a-pcie", "snps,dw-pcie";
|
|
+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
|
|
+ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
+ reg-names = "regs", "config";
|
|
+ interrupts = <0 118 0x4>; /* Level high type */
|
|
+ interrupt-names = "aer";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ dma-coherent;
|
|
+ fsl,lut_diff;
|
|
+ num-lanes = <8>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
+ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&its>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
|
|
+ <0000 0 0 2 &gic 0 0 0 120 4>,
|
|
+ <0000 0 0 3 &gic 0 0 0 121 4>,
|
|
+ <0000 0 0 4 &gic 0 0 0 122 4>;
|
|
+ };
|
|
+
|
|
+ pcie4: pcie@3700000 {
|
|
+ compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie",
|
|
+ "fsl,ls2085a-pcie", "snps,dw-pcie";
|
|
+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
|
|
+ 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
|
|
+ reg-names = "regs", "config";
|
|
+ interrupts = <0 123 0x4>; /* Level high type */
|
|
+ interrupt-names = "aer";
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <2>;
|
|
+ device_type = "pci";
|
|
+ dma-coherent;
|
|
+ fsl,lut_diff;
|
|
+ num-lanes = <4>;
|
|
+ bus-range = <0x0 0xff>;
|
|
+ ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
+ 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
|
+ msi-parent = <&its>;
|
|
+ #interrupt-cells = <1>;
|
|
+ interrupt-map-mask = <0 0 0 7>;
|
|
+ interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
|
|
+ <0000 0 0 2 &gic 0 0 0 125 4>,
|
|
+ <0000 0 0 3 &gic 0 0 0 126 4>,
|
|
+ <0000 0 0 4 &gic 0 0 0 127 4>;
|
|
+ };
|
|
+
|
|
+ sata0: sata@3200000 {
|
|
+ status = "disabled";
|
|
+ compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci";
|
|
+ reg = <0x0 0x3200000 0x0 0x10000>;
|
|
+ interrupts = <0 133 0x4>; /* Level high type */
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ };
|
|
+
|
|
+ sata1: sata@3210000 {
|
|
+ status = "disabled";
|
|
+ compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci";
|
|
+ reg = <0x0 0x3210000 0x0 0x10000>;
|
|
+ interrupts = <0 136 0x4>; /* Level high type */
|
|
+ clocks = <&clockgen 4 3>;
|
|
+ };
|
|
+
|
|
+ usb0: usb3@3100000 {
|
|
+ status = "disabled";
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0x3100000 0x0 0x10000>;
|
|
+ interrupts = <0 80 0x4>; /* Level high type */
|
|
+ dr_mode = "host";
|
|
+ configure-gfladj;
|
|
+ snps,dis_rxdet_inp3_quirk;
|
|
+ };
|
|
+
|
|
+ usb1: usb3@3110000 {
|
|
+ status = "disabled";
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x0 0x3110000 0x0 0x10000>;
|
|
+ interrupts = <0 81 0x4>; /* Level high type */
|
|
+ dr_mode = "host";
|
|
+ configure-gfladj;
|
|
+ snps,dis_rxdet_inp3_quirk;
|
|
+ };
|
|
+
|
|
+ smmu: iommu@5000000 {
|
|
+ compatible = "arm,mmu-500";
|
|
+ reg = <0 0x5000000 0 0x800000>;
|
|
+ #global-interrupts = <12>;
|
|
+ interrupts = <0 13 4>, /* global secure fault */
|
|
+ <0 14 4>, /* combined secure interrupt */
|
|
+ <0 15 4>, /* global non-secure fault */
|
|
+ <0 16 4>, /* combined non-secure interrupt */
|
|
+ /* performance counter interrupts 0-7 */
|
|
+ <0 211 4>,
|
|
+ <0 212 4>,
|
|
+ <0 213 4>,
|
|
+ <0 214 4>,
|
|
+ <0 215 4>,
|
|
+ <0 216 4>,
|
|
+ <0 217 4>,
|
|
+ <0 218 4>,
|
|
+ /* per context interrupt, 64 interrupts */
|
|
+ <0 146 4>,
|
|
+ <0 147 4>,
|
|
+ <0 148 4>,
|
|
+ <0 149 4>,
|
|
+ <0 150 4>,
|
|
+ <0 151 4>,
|
|
+ <0 152 4>,
|
|
+ <0 153 4>,
|
|
+ <0 154 4>,
|
|
+ <0 155 4>,
|
|
+ <0 156 4>,
|
|
+ <0 157 4>,
|
|
+ <0 158 4>,
|
|
+ <0 159 4>,
|
|
+ <0 160 4>,
|
|
+ <0 161 4>,
|
|
+ <0 162 4>,
|
|
+ <0 163 4>,
|
|
+ <0 164 4>,
|
|
+ <0 165 4>,
|
|
+ <0 166 4>,
|
|
+ <0 167 4>,
|
|
+ <0 168 4>,
|
|
+ <0 169 4>,
|
|
+ <0 170 4>,
|
|
+ <0 171 4>,
|
|
+ <0 172 4>,
|
|
+ <0 173 4>,
|
|
+ <0 174 4>,
|
|
+ <0 175 4>,
|
|
+ <0 176 4>,
|
|
+ <0 177 4>,
|
|
+ <0 178 4>,
|
|
+ <0 179 4>,
|
|
+ <0 180 4>,
|
|
+ <0 181 4>,
|
|
+ <0 182 4>,
|
|
+ <0 183 4>,
|
|
+ <0 184 4>,
|
|
+ <0 185 4>,
|
|
+ <0 186 4>,
|
|
+ <0 187 4>,
|
|
+ <0 188 4>,
|
|
+ <0 189 4>,
|
|
+ <0 190 4>,
|
|
+ <0 191 4>,
|
|
+ <0 192 4>,
|
|
+ <0 193 4>,
|
|
+ <0 194 4>,
|
|
+ <0 195 4>,
|
|
+ <0 196 4>,
|
|
+ <0 197 4>,
|
|
+ <0 198 4>,
|
|
+ <0 199 4>,
|
|
+ <0 200 4>,
|
|
+ <0 201 4>,
|
|
+ <0 202 4>,
|
|
+ <0 203 4>,
|
|
+ <0 204 4>,
|
|
+ <0 205 4>,
|
|
+ <0 206 4>,
|
|
+ <0 207 4>,
|
|
+ <0 208 4>,
|
|
+ <0 209 4>;
|
|
+ mmu-masters = <&fsl_mc 0x300 0>;
|
|
+ };
|
|
+
|
|
+ timer {
|
|
+ compatible = "arm,armv8-timer";
|
|
+ interrupts = <1 13 0x1>, /* Physical Secure PPI, edge triggered */
|
|
+ <1 14 0x1>, /* Physical Non-Secure PPI, edge triggered */
|
|
+ <1 11 0x1>, /* Virtual PPI, edge triggered */
|
|
+ <1 10 0x1>; /* Hypervisor PPI, edge triggered */
|
|
+ arm,reread-timer;
|
|
+ fsl,erratum-a008585;
|
|
+ };
|
|
+
|
|
+ fsl_mc: fsl-mc@80c000000 {
|
|
+ compatible = "fsl,qoriq-mc";
|
|
+ #stream-id-cells = <2>;
|
|
+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
|
|
+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
|
|
+ msi-parent = <&its>;
|
|
+ #address-cells = <3>;
|
|
+ #size-cells = <1>;
|
|
+
|
|
+ /*
|
|
+ * Region type 0x0 - MC portals
|
|
+ * Region type 0x1 - QBMAN portals
|
|
+ */
|
|
+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
|
|
+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
|
|
+
|
|
+ /*
|
|
+ * Define the maximum number of MACs present on the SoC.
|
|
+ * They won't necessarily be all probed, since the
|
|
+ * Data Path Layout file and the MC firmware can put fewer
|
|
+ * actual DPMAC objects on the MC bus.
|
|
+ */
|
|
+ dpmacs {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ dpmac1: dpmac@1 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <1>;
|
|
+ };
|
|
+ dpmac2: dpmac@2 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <2>;
|
|
+ };
|
|
+ dpmac3: dpmac@3 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <3>;
|
|
+ };
|
|
+ dpmac4: dpmac@4 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <4>;
|
|
+ };
|
|
+ dpmac5: dpmac@5 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <5>;
|
|
+ };
|
|
+ dpmac6: dpmac@6 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <6>;
|
|
+ };
|
|
+ dpmac7: dpmac@7 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <7>;
|
|
+ };
|
|
+ dpmac8: dpmac@8 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <8>;
|
|
+ };
|
|
+ dpmac9: dpmac@9 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <9>;
|
|
+ };
|
|
+ dpmac10: dpmac@10 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <0xa>;
|
|
+ };
|
|
+ dpmac11: dpmac@11 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <0xb>;
|
|
+ };
|
|
+ dpmac12: dpmac@12 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <0xc>;
|
|
+ };
|
|
+ dpmac13: dpmac@13 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <0xd>;
|
|
+ };
|
|
+ dpmac14: dpmac@14 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <0xe>;
|
|
+ };
|
|
+ dpmac15: dpmac@15 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <0xf>;
|
|
+ };
|
|
+ dpmac16: dpmac@16 {
|
|
+ compatible = "fsl,qoriq-mc-dpmac";
|
|
+ reg = <0x10>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ ccn@4000000 {
|
|
+ compatible = "arm,ccn-504";
|
|
+ reg = <0x0 0x04000000 0x0 0x01000000>;
|
|
+ interrupts = <0 12 4>;
|
|
+ };
|
|
+
|
|
+ memory@80000000 {
|
|
+ device_type = "memory";
|
|
+ reg = <0x00000000 0x80000000 0 0x80000000>;
|
|
+ /* DRAM space 1 - 2 GB DRAM */
|
|
+ };
|
|
+};
|