mirror of https://github.com/hak5/openwrt.git
119 lines
3.2 KiB
Diff
119 lines
3.2 KiB
Diff
From 118d9f0abd69278cfdd7c5bde4743c0cab9b7618 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 8 Mar 2012 11:23:00 +0100
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Subject: [PATCH 29/70] NET: MIPS: lantiq: convert etop driver to clkdev api
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Update from old pmu_{dis,en}able() to ckldev api.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Cc: netdev@vger.kernel.org
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---
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drivers/net/ethernet/lantiq_etop.c | 49 ++++++++++++++++++++++++++++++-----
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1 files changed, 42 insertions(+), 7 deletions(-)
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--- a/drivers/net/ethernet/lantiq_etop.c
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+++ b/drivers/net/ethernet/lantiq_etop.c
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@@ -36,6 +36,7 @@
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/module.h>
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+#include <linux/clk.h>
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#include <asm/checksum.h>
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@@ -148,6 +149,11 @@ struct ltq_etop_priv {
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int tx_free[MAX_DMA_CHAN >> 1];
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spinlock_t lock;
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+
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+ struct clk *clk_ppe;
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+ struct clk *clk_switch;
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+ struct clk *clk_ephy;
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+ struct clk *clk_ephycgu;
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};
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static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
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@@ -281,16 +287,27 @@ ltq_etop_hw_exit(struct net_device *dev)
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struct ltq_etop_priv *priv = netdev_priv(dev);
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int i;
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- ltq_pmu_disable(PMU_PPE);
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+ clk_disable(priv->clk_ppe);
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+
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+ if (ltq_has_gbit())
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+ clk_disable(priv->clk_switch);
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+
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+ if (ltq_is_ase()) {
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+ clk_disable(priv->clk_ephy);
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+ clk_disable(priv->clk_ephycgu);
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+ }
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+
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for (i = 0; i < MAX_DMA_CHAN; i++)
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if (IS_TX(i) || IS_RX(i))
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ltq_etop_free_channel(dev, &priv->ch[i]);
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}
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static void
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-ltq_etop_gbit_init(void)
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+ltq_etop_gbit_init(struct net_device *dev)
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{
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- ltq_pmu_enable(PMU_SWITCH);
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+ struct ltq_etop_priv *priv = netdev_priv(dev);
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+
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+ clk_enable(priv->clk_switch);
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ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
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/** Disable MDIO auto polling mode */
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@@ -313,10 +330,10 @@ ltq_etop_hw_init(struct net_device *dev)
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int err = 0;
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int i;
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- ltq_pmu_enable(PMU_PPE);
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+ clk_enable(priv->clk_ppe);
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if (ltq_has_gbit()) {
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- ltq_etop_gbit_init();
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+ ltq_etop_gbit_init(dev);
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/* force the etops link to the gbit to MII */
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mii_mode = PHY_INTERFACE_MODE_MII;
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}
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@@ -334,11 +351,11 @@ ltq_etop_hw_init(struct net_device *dev)
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default:
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if (ltq_is_ase()) {
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- ltq_pmu_enable(PMU_EPHY);
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+ clk_enable(priv->clk_ephy);
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/* disable external MII */
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ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
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/* enable clock for internal PHY */
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- ltq_cgu_enable(CGU_EPHY);
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+ clk_enable(priv->clk_ephycgu);
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/* we need to write this magic to the internal phy to
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make it work */
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ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
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@@ -883,6 +900,24 @@ ltq_etop_probe(struct platform_device *p
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priv->pdev = pdev;
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priv->pldata = dev_get_platdata(&pdev->dev);
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priv->netdev = dev;
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+
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+ priv->clk_ppe = clk_get(&pdev->dev, NULL);
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+ if (IS_ERR(priv->clk_ppe))
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+ return PTR_ERR(priv->clk_ppe);
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+ if (ltq_has_gbit()) {
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+ priv->clk_switch = clk_get(&pdev->dev, "switch");
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+ if (IS_ERR(priv->clk_switch))
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+ return PTR_ERR(priv->clk_switch);
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+ }
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+ if (ltq_is_ase()) {
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+ priv->clk_ephy = clk_get(&pdev->dev, "ephy");
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+ if (IS_ERR(priv->clk_ephy))
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+ return PTR_ERR(priv->clk_ephy);
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+ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
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+ if (IS_ERR(priv->clk_ephycgu))
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+ return PTR_ERR(priv->clk_ephycgu);
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+ }
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+
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spin_lock_init(&priv->lock);
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for (i = 0; i < MAX_DMA_CHAN; i++) {
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