mirror of https://github.com/hak5/openwrt.git
426 lines
11 KiB
Diff
426 lines
11 KiB
Diff
From 29ceb2449cb3622ccfba9eb1c77bf2ac4162464b Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sat, 27 Jun 2015 13:15:29 +0200
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Subject: [PATCH 64/76] arm: mediatek: add mt7623 pcie support
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/arm/mach-mediatek/Makefile | 2 +-
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arch/arm/mach-mediatek/pcie.c | 383 +++++++++++++++++++++++++++++++++++++++
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arch/arm/mach-mediatek/pcie.h | 14 ++
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3 files changed, 398 insertions(+), 1 deletion(-)
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create mode 100644 arch/arm/mach-mediatek/pcie.c
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create mode 100644 arch/arm/mach-mediatek/pcie.h
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--- a/arch/arm/mach-mediatek/Makefile
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+++ b/arch/arm/mach-mediatek/Makefile
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@@ -1,4 +1,4 @@
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ifeq ($(CONFIG_SMP),y)
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obj-$(CONFIG_ARCH_MEDIATEK) += platsmp.o
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endif
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-obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o
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+obj-$(CONFIG_ARCH_MEDIATEK) += mediatek.o pcie.o
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--- /dev/null
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+++ b/arch/arm/mach-mediatek/pcie.c
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@@ -0,0 +1,383 @@
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+/*
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+ * Mediatek MT7623 SoC PCIE support
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+ *
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+ * Copyright (C) 2015 Mediatek
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+ * Copyright (C) 2015 John Crispin <blogic@openwrt.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/pci.h>
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+#include <linux/ioport.h>
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+#include <linux/interrupt.h>
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+#include <linux/spinlock.h>
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/delay.h>
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+#include <asm/irq.h>
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+#include <asm/mach/pci.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/of_irq.h>
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+#include <linux/of_pci.h>
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+#include <linux/reset.h>
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+#include <linux/platform_device.h>
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+
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+#include "pcie.h"
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+
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+#define PCICFG 0x00
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+#define PCIINT 0x08
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+#define PCIENA 0x0C
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+#define CFGADDR 0x20
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+#define CFGDATA 0x24
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+#define MEMBASE 0x28
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+#define IOBASE 0x2C
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+
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+#define BAR0SETUP 0x10
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+#define IMBASEBAR0 0x18
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+#define PCIE_CLASS 0x34
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+#define PCIE_SISTAT 0x50
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+
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+#define MTK_PCIE_HIGH_PERF BIT(14)
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+#define PCIEP0_BASE 0x2000
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+#define PCIEP1_BASE 0x3000
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+#define PCIEP2_BASE 0x4000
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+
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+#define PHY_P0_CTL 0x9000
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+#define PHY_P1_CTL 0xA000
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+#define PHY_P2_CTL 0x4000
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+
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+#define RSTCTL_PCIE0_RST BIT(24)
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+#define RSTCTL_PCIE1_RST BIT(25)
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+#define RSTCTL_PCIE2_RST BIT(26)
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+
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+static void __iomem *pcie_base;
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+static int pcie_card_link;
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+
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+static struct mtk_pcie_port {
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+ int id;
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+ int enable;
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+ u32 base;
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+ u32 phy_base;
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+ u32 perst_n;
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+ u32 reset;
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+ u32 interrupt;
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+ u32 link;
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+} mtk_pcie_port[] = {
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+ { 0, 1, PCIEP0_BASE, PHY_P0_CTL, BIT(1), RSTCTL_PCIE0_RST, BIT(20) },
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+ { 1, 1, PCIEP1_BASE, PHY_P1_CTL, BIT(2), RSTCTL_PCIE1_RST, BIT(21) },
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+ { 2, 0, PCIEP2_BASE, PHY_P2_CTL, BIT(3), RSTCTL_PCIE2_RST, BIT(22) },
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+};
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+
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+#define mtk_foreach_port(p) \
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+ for (p = mtk_pcie_port; p != &mtk_pcie_port[ARRAY_SIZE(mtk_pcie_port)]; p++)
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+
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+#define mtk_foreach_port_enabled(p) \
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+ mtk_foreach_port(p) \
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+ if (p->enable)
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+
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+#define mtk_foreach_port_link(p) \
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+ mtk_foreach_port(p) \
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+ if (p->link)
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+
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+static struct mtk_phy_init {
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+ uint32_t reg;
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+ uint32_t mask;
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+ uint32_t val;
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+} mtk_phy_init[] = {
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+ { 0xC00, 0x33000, 0x22000 },
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+ { 0xB04, 0xe0000000, 0x40000000 },
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+ { 0xB00, 0xe, 0x4 },
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+ { 0xC3C, 0xffff0000, 0x3c0000 },
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+ { 0xC48, 0xffff, 0x36 },
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+ { 0xC0C, 0x30000000, 0x10000000 },
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+ { 0xC08, 0x3800c0, 0xc0 },
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+ { 0xC10, 0xf0000, 0x20000 },
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+ { 0xC0C, 0xf000, 0x1000 },
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+ { 0xC14, 0xf0000, 0xa0000 },
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+};
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+
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+static inline void pcie_w32(u32 val, unsigned reg)
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+{
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+ iowrite32(val, pcie_base + reg);
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+}
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+
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+static inline u32 pcie_r32(unsigned reg)
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+{
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+ return ioread32(pcie_base + reg);
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+}
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+
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+static inline void pcie_m32(u32 mask, u32 val, unsigned reg)
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+{
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+ u32 v = pcie_r32(reg);
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+
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+ v &= mask;
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+ v |= val;
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+ pcie_w32(v, reg);
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+}
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+
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+static int pcie_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
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+{
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+ unsigned int slot = PCI_SLOT(devfn);
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+ u8 func = PCI_FUNC(devfn);
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+ u32 address;
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+ u32 data;
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+ u32 num = 0;
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+
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+ if (bus)
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+ num = bus->number;
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+
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+ address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc);
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+ pcie_m32(0xf0000000, address, CFGADDR);
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+ data = pcie_r32(CFGDATA);
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+
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+ switch (size) {
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+ case 1:
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+ *val = (data >> ((where & 3) << 3)) & 0xff;
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+ break;
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+ case 2:
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+ *val = (data >> ((where & 3) << 3)) & 0xffff;
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+ break;
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+ case 4:
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+ *val = data;
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+ break;
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+ }
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+static int pcie_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
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+{
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+ unsigned int slot = PCI_SLOT(devfn);
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+ u8 func = PCI_FUNC(devfn);
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+ u32 address;
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+ u32 data;
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+ u32 num = 0;
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+
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+ if (bus)
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+ num = bus->number;
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+
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+ address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc);
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+ pcie_m32(0xf0000000, address, CFGADDR);
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+ data = pcie_r32(CFGDATA);
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+
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+ switch (size) {
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+ case 1:
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+ data = (data & ~(0xff << ((where & 3) << 3))) |
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+ (val << ((where & 3) << 3));
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+ break;
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+ case 2:
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+ data = (data & ~(0xffff << ((where & 3) << 3))) |
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+ (val << ((where & 3) << 3));
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+ break;
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+ case 4:
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+ data = val;
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+ break;
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+ }
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+
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+ pcie_w32(data, CFGDATA);
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+static struct pci_ops mtk_pcie_ops = {
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+ .read = pcie_config_read,
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+ .write = pcie_config_write,
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+};
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+
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+static struct resource pci_mem = {
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+ .name = "PCIe Memory space",
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+ .start = MEM_DIRECT1,
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+ .end = (u32) (MEM_DIRECT1 + (unsigned char *) 0x0fffffff),
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+static struct resource pci_io = {
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+ .name = "PCIe IO space",
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+ .start = IO_WIN,
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+ .end = (u32) (IO_WIN + (unsigned char *) 0x0ffff),
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+ .flags = IORESOURCE_IO,
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+};
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+
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+static int __init mtk_pcie_setup(int nr, struct pci_sys_data *sys)
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+{
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+ sys->mem_offset = 0;
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+ sys->io_offset = 0;
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+
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+ request_resource(&ioport_resource, &pci_io);
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+ request_resource(&iomem_resource, &pci_mem);
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+
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+ pci_add_resource_offset(&sys->resources, &pci_io, sys->io_offset);
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+ pci_add_resource_offset(&sys->resources, &pci_mem, sys->mem_offset);
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+
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+ return 1;
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+}
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+
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+static struct pci_bus * __init mtk_pcie_scan_bus(int nr, struct pci_sys_data *sys)
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+{
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+ return pci_scan_root_bus(NULL, sys->busnr, &mtk_pcie_ops, sys,
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+ &sys->resources);
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+}
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+
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+static int __init mtk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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+{
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+ u16 cmd;
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+ u32 val;
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+
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+ if (dev->bus->number == 0) {
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+ pcie_config_write(NULL, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
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+ pcie_config_read(NULL, slot, 0, PCI_BASE_ADDRESS_0, &val);
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+ printk("BAR0 at bus %d, slot %d\n", dev->bus->number, slot);
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+ }
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+
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+ printk("bus=0x%x, slot = 0x%x, pin=0x%x, irq=0x%x\n", dev->bus->number, slot, pin, dev->irq);
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+
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+ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
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+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);
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+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
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+ cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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+ pci_write_config_word(dev, PCI_COMMAND, cmd);
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+ pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
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+
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+ return dev->irq;
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+}
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+
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+static void __init mtk_pcie_preinit(void)
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+{
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+ struct mtk_pcie_port *port;
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+ u32 val = 0;
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+ int i;
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+
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+ pcibios_min_io = 0;
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+ pcibios_min_mem = 0;
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+
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+#if defined (CONFIG_PCIE_PORT2)
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+ printk("%s: PCIe/USB3 combo PHY mode (%x) =%x\n", __func__, SYSCFG1, REGDATA(SYSCFG1));
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+ REGDATA(SYSCFG1) &= ~(0x300000);
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+ printk("%s: PCIe/USB3 combo PHY mode (%x) =%x\n", __func__, SYSCFG1, REGDATA(SYSCFG1));
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+#endif
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+
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+ /* PCIe RC Reset */
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+ val = 0;
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+ mtk_foreach_port_enabled(port)
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+ val |= port->reset;
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+ REGDATA(RSTCTL) |= val;
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+ mdelay(10);
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+ REGDATA(RSTCTL) &= ~val;
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+ mdelay(10);
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+
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+ /* Configure PCIe PHY */
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+ mtk_foreach_port_enabled(port) {
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+ for (i = 0; i < ARRAY_SIZE(mtk_phy_init); i++) {
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+ u32 val = pcie_r32(port->phy_base + mtk_phy_init[i].reg);
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+ val &= ~mtk_phy_init[i].mask;
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+ val |= mtk_phy_init[i].val;
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+ pcie_w32(val, port->phy_base + mtk_phy_init[i].reg);
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+ }
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+ mdelay(10);
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+ }
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+
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+ /* Enable RC */
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+ mtk_foreach_port_enabled(port) {
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+ val = 0;
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+ pcie_config_read(NULL, port->id, 0, 0x73c, &val);
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+ val &= ~(0x9fff)<<16;
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+ val |= 0x806c<<16;
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+ pcie_config_write(NULL, port->id, 0, 0x73c, val);
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+ }
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+
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+ /* PCIe EP reset */
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+ val = 0;
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+ mtk_foreach_port_enabled(port)
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+ val |= port->perst_n;
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+ val |= MTK_PCIE_HIGH_PERF;
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+ pcie_w32(pcie_r32(PCICFG) | val, PCICFG);
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+ mdelay(10);
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+ pcie_w32(pcie_r32(PCICFG) & ~val, PCICFG);
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+ mdelay(10);
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+
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+ /* check the link status */
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+ val = 0;
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+ mtk_foreach_port_enabled(port) {
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+ if ((pcie_r32(port->base + PCIE_SISTAT) & 0x1))
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+ port->link = 1;
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+ else
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+ val |= port->reset;
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+ }
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+ REGDATA(RSTCTL) |= val;
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+
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+ mtk_foreach_port_link(port)
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+ pcie_card_link++;
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+
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+ printk("PCIe Link count = %d\n", pcie_card_link);
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+ if (!pcie_card_link)
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+ return;
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+
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+ pcie_w32(MEM_WIN, MEMBASE);
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+ pcie_w32(IO_WIN, IOBASE);
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+
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+ mtk_foreach_port_link(port) {
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+ pcie_m32(0, port->interrupt, PCIENA);
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+ pcie_w32(0x7FFF0001, port->base + BAR0SETUP);
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+ pcie_w32(MEMORY_BASE, port->base + IMBASEBAR0);
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+ pcie_w32(0x06040001, port->base + PCIE_CLASS);
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+ printk("PCIE%d Setup OK\n", port->id);
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+ }
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+ val = 0;
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+
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+ pcie_config_read(NULL, pcie_card_link - 1, 0, 0x4, &val);
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+ pcie_config_write(NULL, pcie_card_link - 1, 0, 0x4, val|0x4);
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+ pcie_config_read(NULL, pcie_card_link - 1, 0, 0x70c, &val);
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+ val &= ~(0xff3) << 8;
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+ val |= 0x50 << 8;
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+ pcie_config_write(NULL, pcie_card_link - 1, 0, 0x70c, val);
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+ pcie_config_read(NULL, pcie_card_link - 1, 0, 0x70c, &val);
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+}
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+
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+static struct hw_pci mtk_pci __initdata = {
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+ .nr_controllers = 1,
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+ .map_irq = mtk_pcie_map_irq,
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+ .setup = mtk_pcie_setup,
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+ .scan = mtk_pcie_scan_bus,
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+ .preinit = mtk_pcie_preinit,
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+};
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+
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+extern void mt7623_ethifsys_init(void);
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+static int mtk_pcie_probe(struct platform_device *pdev)
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+{
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+ struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+
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+ pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
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+ if (!pcie_base)
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+ return -ENOMEM;
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+
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+ mt7623_ethifsys_init();
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+ pci_common_init_dev(&pdev->dev, &mtk_pci);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id mtk_pcie_ids[] = {
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+ { .compatible = "mediatek,mt7623-pcie" },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, mtk_pcie_ids);
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+
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+static struct platform_driver mtk_pcie_driver = {
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+ .probe = mtk_pcie_probe,
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+ .driver = {
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+ .name = "mt7623-pcie",
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+ .owner = THIS_MODULE,
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+ .of_match_table = of_match_ptr(mtk_pcie_ids),
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+ },
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+};
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+
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+static int __init mtk_pcie_init(void)
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+{
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+ return platform_driver_register(&mtk_pcie_driver);
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+}
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+
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+late_initcall(mtk_pcie_init);
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--- /dev/null
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+++ b/arch/arm/mach-mediatek/pcie.h
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@@ -0,0 +1,14 @@
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+#define SYSCTL_BASE 0xFA000000
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+#define MEM_WIN 0x1A150000
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+#define IO_WIN 0x1A160000
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+#define MEM_DIRECT1 0x60000000
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+#define MEMORY_BASE 0x80000000
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+
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+#define REGADDR(x, y) (x##_BASE + y)
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+#define REGDATA(x) *((volatile unsigned int *)(x))
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+
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+#define SYSCFG1 REGADDR(SYSCTL, 0x14)
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+#define RSTCTL REGADDR(SYSCTL, 0x34)
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+
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+
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+
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