mirror of https://github.com/hak5/openwrt.git
261 lines
7.0 KiB
Diff
261 lines
7.0 KiB
Diff
From f22c157f44c93d61058d2e2aa5626ee2899fde5a Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Tue, 22 Jan 2013 18:24:34 +0100
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Subject: [PATCH 114/121] GPIO: MIPS: ralink: adds ralink gpio support
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Add gpio driver for Ralink SoC. This driver makes the gpio core on
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RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/Kconfig | 1 +
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arch/mips/include/asm/mach-ralink/gpio.h | 24 ++++
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drivers/gpio/Kconfig | 6 +
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drivers/gpio/Makefile | 1 +
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drivers/gpio/gpio-ralink.c | 176 ++++++++++++++++++++++++++++++
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5 files changed, 208 insertions(+)
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create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
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create mode 100644 drivers/gpio/gpio-ralink.c
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -449,6 +449,7 @@ config RALINK
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select SYS_HAS_EARLY_PRINTK
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select HAVE_MACH_CLKDEV
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select CLKDEV_LOOKUP
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+ select ARCH_REQUIRE_GPIOLIB
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config SGI_IP22
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bool "SGI IP22 (Indy/Indigo2)"
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-ralink/gpio.h
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@@ -0,0 +1,24 @@
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+/*
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+ * Ralink SoC GPIO API support
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+ *
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+ * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ */
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+
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+#ifndef __ASM_MACH_RALINK_GPIO_H
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+#define __ASM_MACH_RALINK_GPIO_H
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+
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+#define ARCH_NR_GPIOS 128
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+#include <asm-generic/gpio.h>
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+
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+#define gpio_get_value __gpio_get_value
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+#define gpio_set_value __gpio_set_value
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+#define gpio_cansleep __gpio_cansleep
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+#define gpio_to_irq __gpio_to_irq
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+
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+#endif /* __ASM_MACH_RALINK_GPIO_H */
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--- a/drivers/gpio/Kconfig
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+++ b/drivers/gpio/Kconfig
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@@ -201,6 +201,12 @@ config GPIO_PXA
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help
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Say yes here to support the PXA GPIO device
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+config GPIO_RALINK
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+ bool "Ralink GPIO Support"
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+ depends on RALINK
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+ help
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+ Say yes here to support the Ralink SoC GPIO device
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+
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config GPIO_SPEAR_SPICS
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bool "ST SPEAr13xx SPI Chip Select as GPIO support"
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depends on PLAT_SPEAR
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--- a/drivers/gpio/Makefile
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+++ b/drivers/gpio/Makefile
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@@ -54,6 +54,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf85
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obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
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obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
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obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
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+obj-$(CONFIG_GPIO_RALINK) += gpio-ralink.o
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obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
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obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
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obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
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--- /dev/null
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+++ b/drivers/gpio/gpio-ralink.c
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@@ -0,0 +1,176 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/io.h>
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+#include <linux/gpio.h>
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+#include <linux/spinlock.h>
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+#include <linux/platform_device.h>
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+
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+enum ralink_gpio_reg {
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+ GPIO_REG_INT = 0,
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+ GPIO_REG_EDGE,
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+ GPIO_REG_RENA,
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+ GPIO_REG_FENA,
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+ GPIO_REG_DATA,
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+ GPIO_REG_DIR,
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+ GPIO_REG_POL,
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+ GPIO_REG_SET,
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+ GPIO_REG_RESET,
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+ GPIO_REG_TOGGLE,
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+ GPIO_REG_MAX
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+};
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+
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+struct ralink_gpio_chip {
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+ struct gpio_chip chip;
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+ u8 regs[GPIO_REG_MAX];
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+
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+ spinlock_t lock;
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+ void __iomem *membase;
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+};
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+
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+static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
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+{
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+ struct ralink_gpio_chip *rg;
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+
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+ rg = container_of(chip, struct ralink_gpio_chip, chip);
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+ return rg;
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+}
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+
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+static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
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+{
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+ iowrite32(val, rg->membase + rg->regs[reg]);
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+}
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+
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+static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
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+{
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+ return ioread32(rg->membase + rg->regs[reg]);
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+}
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+
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+static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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+{
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+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
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+
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+ rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
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+}
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+
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+static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
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+{
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+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
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+
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+ return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
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+}
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+
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+static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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+{
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+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
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+ unsigned long flags;
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+ u32 t;
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+
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+ spin_lock_irqsave(&rg->lock, flags);
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+ t = rt_gpio_r32(rg, GPIO_REG_DIR);
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+ t &= ~BIT(offset);
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+ rt_gpio_w32(rg, GPIO_REG_DIR, t);
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+ spin_unlock_irqrestore(&rg->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int ralink_gpio_direction_output(struct gpio_chip *chip,
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+ unsigned offset, int value)
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+{
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+ struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
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+ unsigned long flags;
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+ u32 t;
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+
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+ spin_lock_irqsave(&rg->lock, flags);
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+ ralink_gpio_set(chip, offset, value);
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+ t = rt_gpio_r32(rg, GPIO_REG_DIR);
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+ t |= BIT(offset);
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+ rt_gpio_w32(rg, GPIO_REG_DIR, t);
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+ spin_unlock_irqrestore(&rg->lock, flags);
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+
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+ return 0;
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+}
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+
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+static int ralink_gpio_probe(struct platform_device *pdev)
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+{
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+ struct device_node *np = pdev->dev.of_node;
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+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ struct ralink_gpio_chip *gc;
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+ const __be32 *ngpio;
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+
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+ if (!res) {
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+ dev_err(&pdev->dev, "failed to find resource\n");
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+ return -ENOMEM;
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+ }
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+
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+ gc = devm_kzalloc(&pdev->dev,
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+ sizeof(struct ralink_gpio_chip), GFP_KERNEL);
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+ if (!gc)
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+ return -ENOMEM;
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+
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+ gc->membase = devm_request_and_ioremap(&pdev->dev, res);
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+ if (!gc->membase) {
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+ dev_err(&pdev->dev, "cannot remap I/O memory region\n");
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+ return -ENOMEM;
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+ }
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+
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+ if (of_property_read_u8_array(np, "ralink,register-map",
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+ gc->regs, GPIO_REG_MAX)) {
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+ dev_err(&pdev->dev, "failed to read register definition\n");
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+ return -EINVAL;
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+ }
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+
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+ ngpio = of_get_property(np, "ralink,num-gpios", NULL);
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+ if (!ngpio) {
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+ dev_err(&pdev->dev, "failed to read number of pins\n");
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+ return -EINVAL;
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+ }
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+
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+ spin_lock_init(&gc->lock);
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+
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+ gc->chip.label = dev_name(&pdev->dev);
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+ gc->chip.of_node = np;
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+ gc->chip.base = -1;
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+ gc->chip.ngpio = be32_to_cpu(*ngpio);
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+ gc->chip.direction_input = ralink_gpio_direction_input;
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+ gc->chip.direction_output = ralink_gpio_direction_output;
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+ gc->chip.get = ralink_gpio_get;
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+ gc->chip.set = ralink_gpio_set;
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+
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+ /* set polarity to low for all lines */
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+ rt_gpio_w32(gc, GPIO_REG_POL, 0);
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+
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+ dev_info(&pdev->dev, "registering %d gpios\n", gc->chip.ngpio);
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+
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+ return gpiochip_add(&gc->chip);
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+}
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+
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+static const struct of_device_id ralink_gpio_match[] = {
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+ { .compatible = "ralink,rt2880-gpio" },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, ralink_gpio_match);
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+
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+static struct platform_driver ralink_gpio_driver = {
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+ .probe = ralink_gpio_probe,
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+ .driver = {
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+ .name = "rt2880_gpio",
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+ .owner = THIS_MODULE,
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+ .of_match_table = ralink_gpio_match,
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+ },
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+};
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+
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+static int __init ralink_gpio_init(void)
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+{
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+ return platform_driver_register(&ralink_gpio_driver);
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+}
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+
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+subsys_initcall(ralink_gpio_init);
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