mirror of https://github.com/hak5/openwrt.git
179 lines
5.4 KiB
Diff
179 lines
5.4 KiB
Diff
From 9818a7a4fd10f72537cdf2a5ec3402f2c245ea24 Mon Sep 17 00:00:00 2001
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From: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Date: Thu, 30 Nov 2017 14:40:28 +0100
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Subject: clk: mvebu: armada-37xx-periph: prepare cpu clk to be
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used with DVFS
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When DVFS will be enabled then the cpu clk will use a different set of
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register at run time. That means that we won't be able to use the common
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callback and need to use our own ones.
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This patch prepares this change by switching on our own set of callbacks
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without modifying the behavior of the clocks.
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Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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---
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drivers/clk/mvebu/armada-37xx-periph.c | 82 ++++++++++++++++++++++++++++++----
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1 file changed, 73 insertions(+), 9 deletions(-)
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--- a/drivers/clk/mvebu/armada-37xx-periph.c
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+++ b/drivers/clk/mvebu/armada-37xx-periph.c
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@@ -46,7 +46,17 @@ struct clk_double_div {
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u8 shift2;
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};
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+struct clk_pm_cpu {
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+ struct clk_hw hw;
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+ void __iomem *reg_mux;
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+ u8 shift_mux;
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+ u32 mask_mux;
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+ void __iomem *reg_div;
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+ u8 shift_div;
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+};
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+
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#define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw)
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+#define to_clk_pm_cpu(_hw) container_of(_hw, struct clk_pm_cpu, hw)
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struct clk_periph_data {
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const char *name;
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@@ -55,6 +65,7 @@ struct clk_periph_data {
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struct clk_hw *mux_hw;
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struct clk_hw *rate_hw;
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struct clk_hw *gate_hw;
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+ struct clk_hw *muxrate_hw;
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bool is_double_div;
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};
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@@ -81,6 +92,7 @@ static const struct clk_div_table clk_ta
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};
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static const struct clk_ops clk_double_div_ops;
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+static const struct clk_ops clk_pm_cpu_ops;
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#define PERIPH_GATE(_name, _bit) \
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struct clk_gate gate_##_name = { \
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@@ -122,6 +134,18 @@ struct clk_divider rate_##_name = { \
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} \
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};
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+#define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \
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+struct clk_pm_cpu muxrate_##_name = { \
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+ .reg_mux = (void *)TBG_SEL, \
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+ .mask_mux = 3, \
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+ .shift_mux = _shift1, \
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+ .reg_div = (void *)_reg, \
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+ .shift_div = _shift2, \
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+ .hw.init = &(struct clk_init_data){ \
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+ .ops = &clk_pm_cpu_ops, \
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+ } \
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+};
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+
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#define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\
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static PERIPH_GATE(_name, _bit); \
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static PERIPH_MUX(_name, _shift); \
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@@ -136,10 +160,6 @@ static PERIPH_DIV(_name, _reg, _shift1,
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static PERIPH_GATE(_name, _bit); \
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static PERIPH_DIV(_name, _reg, _shift, _table);
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-#define PERIPH_CLK_MUX_DIV(_name, _shift, _reg, _shift_div, _table) \
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-static PERIPH_MUX(_name, _shift); \
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-static PERIPH_DIV(_name, _reg, _shift_div, _table);
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-
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#define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\
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static PERIPH_MUX(_name, _shift); \
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static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
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@@ -180,13 +200,12 @@ static PERIPH_DOUBLEDIV(_name, _reg1, _r
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.rate_hw = &rate_##_name.hw, \
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}
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-#define REF_CLK_MUX_DIV(_name) \
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+#define REF_CLK_PM_CPU(_name) \
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{ .name = #_name, \
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.parent_names = (const char *[]){ "TBG-A-P", \
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"TBG-B-P", "TBG-A-S", "TBG-B-S"}, \
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.num_parents = 4, \
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- .mux_hw = &mux_##_name.hw, \
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- .rate_hw = &rate_##_name.hw, \
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+ .muxrate_hw = &muxrate_##_name.hw, \
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}
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#define REF_CLK_MUX_DD(_name) \
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@@ -216,7 +235,7 @@ PERIPH_CLK_FULL_DD(ddr_fclk, 21, 16, DIV
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PERIPH_CLK_FULL(trace, 22, 18, DIV_SEL0, 20, clk_table6);
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PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL0, 23, clk_table6);
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PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19);
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-PERIPH_CLK_MUX_DIV(cpu, 22, DIV_SEL0, 28, clk_table6);
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+static PERIPH_PM_CPU(cpu, 22, DIV_SEL0, 28);
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static struct clk_periph_data data_nb[] = {
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REF_CLK_FULL_DD(mmc),
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@@ -235,7 +254,7 @@ static struct clk_periph_data data_nb[]
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REF_CLK_FULL(trace),
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REF_CLK_FULL(counter),
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REF_CLK_FULL_DD(eip97),
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- REF_CLK_MUX_DIV(cpu),
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+ REF_CLK_PM_CPU(cpu),
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{ },
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};
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@@ -297,6 +316,37 @@ static const struct clk_ops clk_double_d
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.recalc_rate = clk_double_div_recalc_rate,
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};
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+static u8 clk_pm_cpu_get_parent(struct clk_hw *hw)
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+{
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+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
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+ int num_parents = clk_hw_get_num_parents(hw);
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+ u32 val;
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+
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+ val = readl(pm_cpu->reg_mux) >> pm_cpu->shift_mux;
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+ val &= pm_cpu->mask_mux;
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+
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+ if (val >= num_parents)
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+ return -EINVAL;
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+
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+ return val;
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+}
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+
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+static unsigned long clk_pm_cpu_recalc_rate(struct clk_hw *hw,
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+ unsigned long parent_rate)
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+{
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+ struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
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+ unsigned int div;
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+
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+ div = get_div(pm_cpu->reg_div, pm_cpu->shift_div);
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+
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+ return DIV_ROUND_UP_ULL((u64)parent_rate, div);
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+}
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+
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+static const struct clk_ops clk_pm_cpu_ops = {
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+ .get_parent = clk_pm_cpu_get_parent,
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+ .recalc_rate = clk_pm_cpu_recalc_rate,
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+};
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+
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static const struct of_device_id armada_3700_periph_clock_of_match[] = {
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{ .compatible = "marvell,armada-3700-periph-clock-nb",
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.data = data_nb, },
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@@ -356,6 +406,20 @@ static int armada_3700_add_composite_clk
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}
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}
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+ if (data->muxrate_hw) {
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+ struct clk_pm_cpu *pmcpu_clk;
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+ struct clk_hw *muxrate_hw = data->muxrate_hw;
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+
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+ pmcpu_clk = to_clk_pm_cpu(muxrate_hw);
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+ pmcpu_clk->reg_mux = reg + (u64)pmcpu_clk->reg_mux;
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+ pmcpu_clk->reg_div = reg + (u64)pmcpu_clk->reg_div;
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+
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+ mux_hw = muxrate_hw;
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+ rate_hw = muxrate_hw;
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+ mux_ops = muxrate_hw->init->ops;
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+ rate_ops = muxrate_hw->init->ops;
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+ }
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+
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*hw = clk_hw_register_composite(dev, data->name, data->parent_names,
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data->num_parents, mux_hw,
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mux_ops, rate_hw, rate_ops,
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