mirror of https://github.com/hak5/openwrt.git
525 lines
14 KiB
Diff
525 lines
14 KiB
Diff
From 7723e59d483a883578115a73eb87eb7fff0ff724 Mon Sep 17 00:00:00 2001
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From: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
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Date: Tue, 28 Feb 2017 10:37:24 +0000
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Subject: mtd: spi-nand: Support Gigadevice GD5F
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This commit uses the recently introduced SPI NAND framework to support
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the Gigadevice GD5F serial NAND device.
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The current support includes:
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* Page read and page program operations (using on-die ECC)
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* Page out-of-band read
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* Erase
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* Reset
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* Device status retrieval
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* Device ID retrieval
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(based on http://lists.infradead.org/pipermail/linux-mtd/2014-December/056769.html)
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Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
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Signed-off-by: Ian Pozella <Ian.Pozella@imgtec.com>
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---
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drivers/mtd/spi-nand/Kconfig | 10 +
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drivers/mtd/spi-nand/Makefile | 1 +
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drivers/mtd/spi-nand/spi-nand-device.c | 472 +++++++++++++++++++++++++++++++++
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3 files changed, 483 insertions(+)
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create mode 100644 drivers/mtd/spi-nand/spi-nand-device.c
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--- a/drivers/mtd/spi-nand/Kconfig
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+++ b/drivers/mtd/spi-nand/Kconfig
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@@ -5,3 +5,13 @@ menuconfig MTD_SPI_NAND
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help
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This is the framework for the SPI NAND.
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+if MTD_SPI_NAND
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+
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+config MTD_SPI_NAND_DEVICES
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+ tristate "Support for SPI NAND devices"
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+ default y
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+ depends on MTD_SPI_NAND
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+ help
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+ Select this option if you require support for SPI NAND devices.
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+
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+endif # MTD_SPI_NAND
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--- a/drivers/mtd/spi-nand/Makefile
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+++ b/drivers/mtd/spi-nand/Makefile
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@@ -1 +1,2 @@
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obj-$(CONFIG_MTD_SPI_NAND) += spi-nand-base.o
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+obj-$(CONFIG_MTD_SPI_NAND_DEVICES) += spi-nand-device.o
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--- /dev/null
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+++ b/drivers/mtd/spi-nand/spi-nand-device.c
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@@ -0,0 +1,472 @@
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+/*
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+ * Copyright (C) 2014 Imagination Technologies Ltd.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; version 2 of the License.
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+ *
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+ * Notes:
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+ * 1. We avoid using a stack-allocated buffer for SPI messages. Using
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+ * a kmalloced buffer is probably better, given we shouldn't assume
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+ * any particular usage by SPI core.
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+ */
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+
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+#include <linux/device.h>
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+#include <linux/err.h>
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+#include <linux/errno.h>
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+#include <linux/module.h>
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/partitions.h>
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+#include <linux/mtd/spi-nand.h>
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+#include <linux/sizes.h>
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+#include <linux/spi/spi.h>
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+
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+/* SPI NAND commands */
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+#define SPI_NAND_WRITE_ENABLE 0x06
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+#define SPI_NAND_WRITE_DISABLE 0x04
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+#define SPI_NAND_GET_FEATURE 0x0f
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+#define SPI_NAND_SET_FEATURE 0x1f
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+#define SPI_NAND_PAGE_READ 0x13
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+#define SPI_NAND_READ_CACHE 0x03
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+#define SPI_NAND_FAST_READ_CACHE 0x0b
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+#define SPI_NAND_READ_CACHE_X2 0x3b
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+#define SPI_NAND_READ_CACHE_X4 0x6b
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+#define SPI_NAND_READ_CACHE_DUAL_IO 0xbb
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+#define SPI_NAND_READ_CACHE_QUAD_IO 0xeb
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+#define SPI_NAND_READ_ID 0x9f
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+#define SPI_NAND_PROGRAM_LOAD 0x02
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+#define SPI_NAND_PROGRAM_LOAD4 0x32
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+#define SPI_NAND_PROGRAM_EXEC 0x10
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+#define SPI_NAND_PROGRAM_LOAD_RANDOM 0x84
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+#define SPI_NAND_PROGRAM_LOAD_RANDOM4 0xc4
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+#define SPI_NAND_BLOCK_ERASE 0xd8
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+#define SPI_NAND_RESET 0xff
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+
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+#define SPI_NAND_GD5F_READID_LEN 2
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+
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+#define SPI_NAND_GD5F_ECC_MASK (BIT(0) | BIT(1) | BIT(2))
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+#define SPI_NAND_GD5F_ECC_UNCORR (BIT(0) | BIT(1) | BIT(2))
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+#define SPI_NAND_GD5F_ECC_SHIFT 4
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+
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+static int spi_nand_gd5f_ooblayout_256_ecc(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *oobregion)
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+{
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+ if (section)
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+ return -ERANGE;
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+
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+ oobregion->offset = 128;
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+ oobregion->length = 128;
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+
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+ return 0;
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+}
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+
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+static int spi_nand_gd5f_ooblayout_256_free(struct mtd_info *mtd, int section,
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+ struct mtd_oob_region *oobregion)
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+{
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+ if (section)
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+ return -ERANGE;
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+
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+ oobregion->offset = 1;
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+ oobregion->length = 127;
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+
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+ return 0;
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+}
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+
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+static const struct mtd_ooblayout_ops spi_nand_gd5f_oob_256_ops = {
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+ .ecc = spi_nand_gd5f_ooblayout_256_ecc,
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+ .free = spi_nand_gd5f_ooblayout_256_free,
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+};
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+
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+static struct nand_flash_dev spi_nand_flash_ids[] = {
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+ {
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+ .name = "SPI NAND 512MiB 3,3V",
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+ .id = { NAND_MFR_GIGADEVICE, 0xb4 },
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+ .chipsize = 512,
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+ .pagesize = SZ_4K,
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+ .erasesize = SZ_256K,
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+ .id_len = 2,
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+ .oobsize = 256,
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+ .ecc.strength_ds = 8,
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+ .ecc.step_ds = 512,
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+ },
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+ {
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+ .name = "SPI NAND 512MiB 1,8V",
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+ .id = { NAND_MFR_GIGADEVICE, 0xa4 },
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+ .chipsize = 512,
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+ .pagesize = SZ_4K,
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+ .erasesize = SZ_256K,
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+ .id_len = 2,
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+ .oobsize = 256,
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+ .ecc.strength_ds = 8,
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+ .ecc.step_ds = 512,
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+ },
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+};
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+
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+enum spi_nand_device_variant {
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+ SPI_NAND_GENERIC,
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+ SPI_NAND_GD5F,
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+};
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+
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+struct spi_nand_device_cmd {
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+
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+ /*
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+ * Command and address. I/O errors have been observed if a
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+ * separate spi_transfer is used for command and address,
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+ * so keep them together.
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+ */
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+ u32 n_cmd;
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+ u8 cmd[5];
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+
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+ /* Tx data */
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+ u32 n_tx;
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+ u8 *tx_buf;
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+
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+ /* Rx data */
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+ u32 n_rx;
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+ u8 *rx_buf;
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+ u8 rx_nbits;
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+ u8 tx_nbits;
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+};
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+
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+struct spi_nand_device {
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+ struct spi_nand spi_nand;
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+ struct spi_device *spi;
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+
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+ struct spi_nand_device_cmd cmd;
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+};
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+
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+static int spi_nand_send_command(struct spi_device *spi,
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+ struct spi_nand_device_cmd *cmd)
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+{
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+ struct spi_message message;
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+ struct spi_transfer x[2];
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+
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+ if (!cmd->n_cmd) {
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+ dev_err(&spi->dev, "cannot send an empty command\n");
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+ return -EINVAL;
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+ }
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+
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+ if (cmd->n_tx && cmd->n_rx) {
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+ dev_err(&spi->dev, "cannot send and receive data at the same time\n");
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+ return -EINVAL;
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+ }
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+
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+ spi_message_init(&message);
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+ memset(x, 0, sizeof(x));
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+
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+ /* Command and address */
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+ x[0].len = cmd->n_cmd;
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+ x[0].tx_buf = cmd->cmd;
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+ x[0].tx_nbits = cmd->tx_nbits;
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+ spi_message_add_tail(&x[0], &message);
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+
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+ /* Data to be transmitted */
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+ if (cmd->n_tx) {
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+ x[1].len = cmd->n_tx;
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+ x[1].tx_buf = cmd->tx_buf;
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+ x[1].tx_nbits = cmd->tx_nbits;
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+ spi_message_add_tail(&x[1], &message);
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+ }
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+
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+ /* Data to be received */
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+ if (cmd->n_rx) {
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+ x[1].len = cmd->n_rx;
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+ x[1].rx_buf = cmd->rx_buf;
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+ x[1].rx_nbits = cmd->rx_nbits;
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+ spi_message_add_tail(&x[1], &message);
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+ }
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+
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+ return spi_sync(spi, &message);
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+}
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+
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+static int spi_nand_device_reset(struct spi_nand *snand)
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+{
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+ struct spi_nand_device *snand_dev = snand->priv;
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+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
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+
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+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
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+ cmd->n_cmd = 1;
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+ cmd->cmd[0] = SPI_NAND_RESET;
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+
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+ dev_dbg(snand->dev, "%s\n", __func__);
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+
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+ return spi_nand_send_command(snand_dev->spi, cmd);
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+}
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+
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+static int spi_nand_device_read_reg(struct spi_nand *snand, u8 opcode, u8 *buf)
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+{
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+ struct spi_nand_device *snand_dev = snand->priv;
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+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
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+
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+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
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+ cmd->n_cmd = 2;
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+ cmd->cmd[0] = SPI_NAND_GET_FEATURE;
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+ cmd->cmd[1] = opcode;
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+ cmd->n_rx = 1;
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+ cmd->rx_buf = buf;
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+
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+ dev_dbg(snand->dev, "%s: reg 0%x\n", __func__, opcode);
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+
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+ return spi_nand_send_command(snand_dev->spi, cmd);
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+}
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+
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+static int spi_nand_device_write_reg(struct spi_nand *snand, u8 opcode, u8 *buf)
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+{
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+ struct spi_nand_device *snand_dev = snand->priv;
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+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
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+
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+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
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+ cmd->n_cmd = 2;
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+ cmd->cmd[0] = SPI_NAND_SET_FEATURE;
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+ cmd->cmd[1] = opcode;
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+ cmd->n_tx = 1;
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+ cmd->tx_buf = buf;
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+
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+ dev_dbg(snand->dev, "%s: reg 0%x\n", __func__, opcode);
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+
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+ return spi_nand_send_command(snand_dev->spi, cmd);
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+}
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+
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+static int spi_nand_device_write_enable(struct spi_nand *snand)
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+{
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+ struct spi_nand_device *snand_dev = snand->priv;
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+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
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+
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+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
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+ cmd->n_cmd = 1;
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+ cmd->cmd[0] = SPI_NAND_WRITE_ENABLE;
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+
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+ dev_dbg(snand->dev, "%s\n", __func__);
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+
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+ return spi_nand_send_command(snand_dev->spi, cmd);
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+}
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+
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+static int spi_nand_device_write_disable(struct spi_nand *snand)
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+{
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+ struct spi_nand_device *snand_dev = snand->priv;
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+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
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+
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+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
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+ cmd->n_cmd = 1;
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+ cmd->cmd[0] = SPI_NAND_WRITE_DISABLE;
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+
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+ dev_dbg(snand->dev, "%s\n", __func__);
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+
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+ return spi_nand_send_command(snand_dev->spi, cmd);
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+}
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+
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+static int spi_nand_device_write_page(struct spi_nand *snand,
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+ unsigned int page_addr)
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+{
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+ struct spi_nand_device *snand_dev = snand->priv;
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+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
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+
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+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
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+ cmd->n_cmd = 4;
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+ cmd->cmd[0] = SPI_NAND_PROGRAM_EXEC;
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+ cmd->cmd[1] = (u8)((page_addr & 0xff0000) >> 16);
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+ cmd->cmd[2] = (u8)((page_addr & 0xff00) >> 8);
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+ cmd->cmd[3] = (u8)(page_addr & 0xff);
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+
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+ dev_dbg(snand->dev, "%s: page 0x%x\n", __func__, page_addr);
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+
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+ return spi_nand_send_command(snand_dev->spi, cmd);
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+}
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+
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+static int spi_nand_device_store_cache(struct spi_nand *snand,
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+ unsigned int page_offset, size_t length,
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+ u8 *write_buf)
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+{
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+ struct spi_nand_device *snand_dev = snand->priv;
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+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
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+ struct spi_device *spi = snand_dev->spi;
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+
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+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
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+ cmd->n_cmd = 3;
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+ cmd->cmd[0] = spi->mode & SPI_TX_QUAD ? SPI_NAND_PROGRAM_LOAD4 :
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+ SPI_NAND_PROGRAM_LOAD;
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+ cmd->cmd[1] = (u8)((page_offset & 0xff00) >> 8);
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+ cmd->cmd[2] = (u8)(page_offset & 0xff);
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+ cmd->n_tx = length;
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+ cmd->tx_buf = write_buf;
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+ cmd->tx_nbits = spi->mode & SPI_TX_QUAD ? 4 : 1;
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+
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+ dev_dbg(snand->dev, "%s: offset 0x%x\n", __func__, page_offset);
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+
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+ return spi_nand_send_command(snand_dev->spi, cmd);
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+}
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+
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+static int spi_nand_device_load_page(struct spi_nand *snand,
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+ unsigned int page_addr)
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+{
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+ struct spi_nand_device *snand_dev = snand->priv;
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+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
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+
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+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
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+ cmd->n_cmd = 4;
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+ cmd->cmd[0] = SPI_NAND_PAGE_READ;
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+ cmd->cmd[1] = (u8)((page_addr & 0xff0000) >> 16);
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+ cmd->cmd[2] = (u8)((page_addr & 0xff00) >> 8);
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+ cmd->cmd[3] = (u8)(page_addr & 0xff);
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+
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+ dev_dbg(snand->dev, "%s: page 0x%x\n", __func__, page_addr);
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+
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+ return spi_nand_send_command(snand_dev->spi, cmd);
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+}
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+
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+static int spi_nand_device_read_cache(struct spi_nand *snand,
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+ unsigned int page_offset, size_t length,
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+ u8 *read_buf)
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+{
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+ struct spi_nand_device *snand_dev = snand->priv;
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+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
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+ struct spi_device *spi = snand_dev->spi;
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+
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+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
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+ if ((spi->mode & SPI_RX_DUAL) || (spi->mode & SPI_RX_QUAD))
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+ cmd->n_cmd = 5;
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+ else
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+ cmd->n_cmd = 4;
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+ cmd->cmd[0] = (spi->mode & SPI_RX_QUAD) ? SPI_NAND_READ_CACHE_X4 :
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+ ((spi->mode & SPI_RX_DUAL) ? SPI_NAND_READ_CACHE_X2 :
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+ SPI_NAND_READ_CACHE);
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+ cmd->cmd[1] = 0; /* dummy byte */
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+ cmd->cmd[2] = (u8)((page_offset & 0xff00) >> 8);
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+ cmd->cmd[3] = (u8)(page_offset & 0xff);
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+ cmd->cmd[4] = 0; /* dummy byte */
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+ cmd->n_rx = length;
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+ cmd->rx_buf = read_buf;
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+ cmd->rx_nbits = (spi->mode & SPI_RX_QUAD) ? 4 :
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+ ((spi->mode & SPI_RX_DUAL) ? 2 : 1);
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+
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+ dev_dbg(snand->dev, "%s: offset 0x%x\n", __func__, page_offset);
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+
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+ return spi_nand_send_command(snand_dev->spi, cmd);
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+}
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+
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+static int spi_nand_device_block_erase(struct spi_nand *snand,
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+ unsigned int page_addr)
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+{
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+ struct spi_nand_device *snand_dev = snand->priv;
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+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
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+
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+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
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+ cmd->n_cmd = 4;
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+ cmd->cmd[0] = SPI_NAND_BLOCK_ERASE;
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+ cmd->cmd[1] = (u8)((page_addr & 0xff0000) >> 16);
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+ cmd->cmd[2] = (u8)((page_addr & 0xff00) >> 8);
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+ cmd->cmd[3] = (u8)(page_addr & 0xff);
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+
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+ dev_dbg(snand->dev, "%s: block 0x%x\n", __func__, page_addr);
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+
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+ return spi_nand_send_command(snand_dev->spi, cmd);
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+}
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+
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+static int spi_nand_gd5f_read_id(struct spi_nand *snand, u8 *buf)
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+{
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+ struct spi_nand_device *snand_dev = snand->priv;
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+ struct spi_nand_device_cmd *cmd = &snand_dev->cmd;
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+
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+ memset(cmd, 0, sizeof(struct spi_nand_device_cmd));
|
|
+ cmd->n_cmd = 1;
|
|
+ cmd->cmd[0] = SPI_NAND_READ_ID;
|
|
+ cmd->n_rx = SPI_NAND_GD5F_READID_LEN;
|
|
+ cmd->rx_buf = buf;
|
|
+
|
|
+ dev_dbg(snand->dev, "%s\n", __func__);
|
|
+
|
|
+ return spi_nand_send_command(snand_dev->spi, cmd);
|
|
+}
|
|
+
|
|
+static void spi_nand_gd5f_ecc_status(unsigned int status,
|
|
+ unsigned int *corrected,
|
|
+ unsigned int *ecc_error)
|
|
+{
|
|
+ unsigned int ecc_status = (status >> SPI_NAND_GD5F_ECC_SHIFT) &
|
|
+ SPI_NAND_GD5F_ECC_MASK;
|
|
+
|
|
+ *ecc_error = (ecc_status == SPI_NAND_GD5F_ECC_UNCORR) ? 1 : 0;
|
|
+ if (*ecc_error == 0)
|
|
+ *corrected = (ecc_status > 1) ? (2 + ecc_status) : 0;
|
|
+}
|
|
+
|
|
+static int spi_nand_device_probe(struct spi_device *spi)
|
|
+{
|
|
+ enum spi_nand_device_variant variant;
|
|
+ struct spi_nand_device *priv;
|
|
+ struct spi_nand *snand;
|
|
+ int ret;
|
|
+
|
|
+ priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
|
|
+ if (!priv)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ snand = &priv->spi_nand;
|
|
+
|
|
+ snand->read_cache = spi_nand_device_read_cache;
|
|
+ snand->load_page = spi_nand_device_load_page;
|
|
+ snand->store_cache = spi_nand_device_store_cache;
|
|
+ snand->write_page = spi_nand_device_write_page;
|
|
+ snand->write_reg = spi_nand_device_write_reg;
|
|
+ snand->read_reg = spi_nand_device_read_reg;
|
|
+ snand->block_erase = spi_nand_device_block_erase;
|
|
+ snand->reset = spi_nand_device_reset;
|
|
+ snand->write_enable = spi_nand_device_write_enable;
|
|
+ snand->write_disable = spi_nand_device_write_disable;
|
|
+ snand->dev = &spi->dev;
|
|
+ snand->priv = priv;
|
|
+
|
|
+ /* This'll mean we won't need to specify any specific compatible string
|
|
+ * for a given device, and instead just support spi-nand.
|
|
+ */
|
|
+ variant = spi_get_device_id(spi)->driver_data;
|
|
+ switch (variant) {
|
|
+ case SPI_NAND_GD5F:
|
|
+ snand->read_id = spi_nand_gd5f_read_id;
|
|
+ snand->get_ecc_status = spi_nand_gd5f_ecc_status;
|
|
+ snand->ooblayout = &spi_nand_gd5f_oob_256_ops;
|
|
+ break;
|
|
+ default:
|
|
+ dev_err(snand->dev, "unknown device\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+
|
|
+ spi_set_drvdata(spi, snand);
|
|
+ priv->spi = spi;
|
|
+
|
|
+ ret = spi_nand_register(snand, spi_nand_flash_ids);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int spi_nand_device_remove(struct spi_device *spi)
|
|
+{
|
|
+ struct spi_nand *snand = spi_get_drvdata(spi);
|
|
+
|
|
+ spi_nand_unregister(snand);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+const struct spi_device_id spi_nand_id_table[] = {
|
|
+ { "spi-nand", SPI_NAND_GENERIC },
|
|
+ { "gd5f", SPI_NAND_GD5F },
|
|
+ { },
|
|
+};
|
|
+MODULE_DEVICE_TABLE(spi, spi_nand_id_table);
|
|
+
|
|
+static struct spi_driver spi_nand_device_driver = {
|
|
+ .driver = {
|
|
+ .name = "spi_nand_device",
|
|
+ .owner = THIS_MODULE,
|
|
+ },
|
|
+ .id_table = spi_nand_id_table,
|
|
+ .probe = spi_nand_device_probe,
|
|
+ .remove = spi_nand_device_remove,
|
|
+};
|
|
+module_spi_driver(spi_nand_device_driver);
|
|
+
|
|
+MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@imgtec.com>");
|
|
+MODULE_DESCRIPTION("SPI NAND device support");
|
|
+MODULE_LICENSE("GPL v2");
|