Tomasz Maciej Nowak 43d1d88510 tegra: correct cpu subtype ... Tegra 2 processors have only 16 double-precision registers. The change introduced by 8dcc108760 ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") switched accidentally the toolchain for tegra target to cpu type with 32 double-precision registers. This stems from gcc defaults which assume "vfpv3-d32" if only "vfpv3" as mfpu is specified. That change resulted in unusable image, in which kernel will kill userspace as soon as it causing "Illegal instruction". Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272 Fixes: 8dcc108760 ("toolchain: ARM: Fix toolchain compilation for gcc 8.x") Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>		2020-03-28 22:58:36 +01:00
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base-files	treewide: use new procd sysupgrade $UPGRADE_BACKUP variable	2019-09-05 23:33:19 +02:00
image	treewide: gather DEVICE_VARS into one place	2020-03-21 19:55:12 +01:00
patches-4.19	tegra: add kernel 4.19 support	2019-04-06 14:48:46 +02:00
patches-5.4	tegra: refresh patches and kernel config for 5.4	2020-03-17 00:51:48 +01:00
Makefile	tegra: correct cpu subtype	2020-03-28 22:58:36 +01:00
config-4.19	tegra: add missing kernel symbol to 4.19 config	2019-06-17 09:42:36 +02:00
config-5.4	tegra: refresh patches and kernel config for 5.4	2020-03-17 00:51:48 +01:00