mirror of https://github.com/hak5/openwrt.git
202 lines
6.3 KiB
Diff
202 lines
6.3 KiB
Diff
From 8d6b6d7e135e9bbfc923d34a45cb0e72695e63ed Mon Sep 17 00:00:00 2001
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From: Abhishek Sahu <absahu@codeaurora.org>
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Date: Mon, 25 Sep 2017 13:21:26 +0530
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Subject: [PATCH 3/7] mtd: nand: qcom: support for command descriptor formation
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1. Add the function for command descriptor preparation which will
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be used only by BAM DMA and it will form the DMA descriptors
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containing command elements
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2. DMA_PREP_CMD flag should be used for forming command DMA
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descriptors
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Reviewed-by: Archit Taneja <architt@codeaurora.org>
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Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
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Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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---
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drivers/mtd/nand/qcom_nandc.c | 108 +++++++++++++++++++++++++++++++++++-------
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1 file changed, 92 insertions(+), 16 deletions(-)
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--- a/drivers/mtd/nand/qcom_nandc.c
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+++ b/drivers/mtd/nand/qcom_nandc.c
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@@ -200,6 +200,14 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_
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*/
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#define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
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+/* Returns the NAND register physical address */
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+#define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
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+
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+/* Returns the dma address for reg read buffer */
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+#define reg_buf_dma_addr(chip, vaddr) \
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+ ((chip)->reg_read_dma + \
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+ ((uint8_t *)(vaddr) - (uint8_t *)(chip)->reg_read_buf))
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+
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#define QPIC_PER_CW_CMD_ELEMENTS 32
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#define QPIC_PER_CW_CMD_SGL 32
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#define QPIC_PER_CW_DATA_SGL 8
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@@ -317,7 +325,8 @@ struct nandc_regs {
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* controller
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* @dev: parent device
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* @base: MMIO base
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- * @base_dma: physical base address of controller registers
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+ * @base_phys: physical base address of controller registers
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+ * @base_dma: dma base address of controller registers
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* @core_clk: controller clock
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* @aon_clk: another controller clock
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*
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@@ -350,6 +359,7 @@ struct qcom_nand_controller {
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struct device *dev;
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void __iomem *base;
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+ phys_addr_t base_phys;
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dma_addr_t base_dma;
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struct clk *core_clk;
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@@ -751,6 +761,66 @@ static int prepare_bam_async_desc(struct
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}
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/*
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+ * Prepares the command descriptor for BAM DMA which will be used for NAND
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+ * register reads and writes. The command descriptor requires the command
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+ * to be formed in command element type so this function uses the command
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+ * element from bam transaction ce array and fills the same with required
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+ * data. A single SGL can contain multiple command elements so
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+ * NAND_BAM_NEXT_SGL will be used for starting the separate SGL
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+ * after the current command element.
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+ */
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+static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read,
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+ int reg_off, const void *vaddr,
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+ int size, unsigned int flags)
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+{
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+ int bam_ce_size;
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+ int i, ret;
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+ struct bam_cmd_element *bam_ce_buffer;
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+ struct bam_transaction *bam_txn = nandc->bam_txn;
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+
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+ bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_pos];
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+
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+ /* fill the command desc */
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+ for (i = 0; i < size; i++) {
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+ if (read)
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+ bam_prep_ce(&bam_ce_buffer[i],
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+ nandc_reg_phys(nandc, reg_off + 4 * i),
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+ BAM_READ_COMMAND,
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+ reg_buf_dma_addr(nandc,
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+ (__le32 *)vaddr + i));
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+ else
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+ bam_prep_ce_le32(&bam_ce_buffer[i],
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+ nandc_reg_phys(nandc, reg_off + 4 * i),
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+ BAM_WRITE_COMMAND,
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+ *((__le32 *)vaddr + i));
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+ }
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+
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+ bam_txn->bam_ce_pos += size;
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+
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+ /* use the separate sgl after this command */
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+ if (flags & NAND_BAM_NEXT_SGL) {
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+ bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
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+ bam_ce_size = (bam_txn->bam_ce_pos -
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+ bam_txn->bam_ce_start) *
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+ sizeof(struct bam_cmd_element);
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+ sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
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+ bam_ce_buffer, bam_ce_size);
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+ bam_txn->cmd_sgl_pos++;
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+ bam_txn->bam_ce_start = bam_txn->bam_ce_pos;
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+
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+ if (flags & NAND_BAM_NWD) {
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+ ret = prepare_bam_async_desc(nandc, nandc->cmd_chan,
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+ DMA_PREP_FENCE |
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+ DMA_PREP_CMD);
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+ if (ret)
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+ return ret;
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+ }
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+ }
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+
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+ return 0;
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+}
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+
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+/*
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* Prepares the data descriptor for BAM DMA which will be used for NAND
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* data reads and writes.
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*/
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@@ -868,19 +938,22 @@ static int read_reg_dma(struct qcom_nand
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{
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bool flow_control = false;
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void *vaddr;
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- int size;
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- if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
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- flow_control = true;
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+ vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
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+ nandc->reg_read_pos += num_regs;
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if (first == NAND_DEV_CMD_VLD || first == NAND_DEV_CMD1)
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first = dev_cmd_reg_addr(nandc, first);
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- size = num_regs * sizeof(u32);
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- vaddr = nandc->reg_read_buf + nandc->reg_read_pos;
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- nandc->reg_read_pos += num_regs;
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+ if (nandc->props->is_bam)
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+ return prep_bam_dma_desc_cmd(nandc, true, first, vaddr,
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+ num_regs, flags);
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+
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+ if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
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+ flow_control = true;
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- return prep_adm_dma_desc(nandc, true, first, vaddr, size, flow_control);
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+ return prep_adm_dma_desc(nandc, true, first, vaddr,
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+ num_regs * sizeof(u32), flow_control);
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}
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/*
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@@ -897,13 +970,9 @@ static int write_reg_dma(struct qcom_nan
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bool flow_control = false;
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struct nandc_regs *regs = nandc->regs;
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void *vaddr;
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- int size;
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vaddr = offset_to_nandc_reg(regs, first);
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- if (first == NAND_FLASH_CMD)
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- flow_control = true;
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-
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if (first == NAND_ERASED_CW_DETECT_CFG) {
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if (flags & NAND_ERASED_CW_SET)
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vaddr = ®s->erased_cw_detect_cfg_set;
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@@ -920,10 +989,15 @@ static int write_reg_dma(struct qcom_nan
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if (first == NAND_DEV_CMD_VLD_RESTORE || first == NAND_DEV_CMD_VLD)
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first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD);
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- size = num_regs * sizeof(u32);
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+ if (nandc->props->is_bam)
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+ return prep_bam_dma_desc_cmd(nandc, false, first, vaddr,
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+ num_regs, flags);
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+
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+ if (first == NAND_FLASH_CMD)
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+ flow_control = true;
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- return prep_adm_dma_desc(nandc, false, first, vaddr, size,
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- flow_control);
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+ return prep_adm_dma_desc(nandc, false, first, vaddr,
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+ num_regs * sizeof(u32), flow_control);
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}
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/*
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@@ -1187,7 +1261,8 @@ static int submit_descs(struct qcom_nand
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}
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if (bam_txn->cmd_sgl_pos > bam_txn->cmd_sgl_start) {
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- r = prepare_bam_async_desc(nandc, nandc->cmd_chan, 0);
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+ r = prepare_bam_async_desc(nandc, nandc->cmd_chan,
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+ DMA_PREP_CMD);
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if (r)
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return r;
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}
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@@ -2722,6 +2797,7 @@ static int qcom_nandc_probe(struct platf
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if (IS_ERR(nandc->base))
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return PTR_ERR(nandc->base);
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+ nandc->base_phys = res->start;
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nandc->base_dma = phys_to_dma(dev, (phys_addr_t)res->start);
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nandc->core_clk = devm_clk_get(dev, "core");
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