mirror of https://github.com/hak5/openwrt.git
229 lines
6.5 KiB
Diff
229 lines
6.5 KiB
Diff
From 6a114526af4689938863bf34976c83bfd279f517 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Mon, 15 Jun 2020 23:06:02 +0200
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Subject: PCI: qcom: Use bulk clk api and assert on error
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Rework 2.1.0 revision to use bulk clk api and fix missing assert on
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reset_control_deassert error.
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Link: https://lore.kernel.org/r/20200615210608.21469-7-ansuelsmth@gmail.com
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
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---
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drivers/pci/controller/dwc/pcie-qcom.c | 131 ++++++++++++---------------------
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1 file changed, 46 insertions(+), 85 deletions(-)
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--- a/drivers/pci/controller/dwc/pcie-qcom.c
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+++ b/drivers/pci/controller/dwc/pcie-qcom.c
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@@ -99,12 +99,9 @@
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#define SLV_ADDR_SPACE_SZ 0x10000000
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#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
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+#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
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struct qcom_pcie_resources_2_1_0 {
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- struct clk *iface_clk;
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- struct clk *core_clk;
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- struct clk *phy_clk;
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- struct clk *aux_clk;
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- struct clk *ref_clk;
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+ struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
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struct reset_control *pci_reset;
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struct reset_control *axi_reset;
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struct reset_control *ahb_reset;
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@@ -244,25 +241,21 @@ static int qcom_pcie_get_resources_2_1_0
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if (ret)
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return ret;
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- res->iface_clk = devm_clk_get(dev, "iface");
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- if (IS_ERR(res->iface_clk))
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- return PTR_ERR(res->iface_clk);
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-
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- res->core_clk = devm_clk_get(dev, "core");
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- if (IS_ERR(res->core_clk))
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- return PTR_ERR(res->core_clk);
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-
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- res->phy_clk = devm_clk_get(dev, "phy");
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- if (IS_ERR(res->phy_clk))
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- return PTR_ERR(res->phy_clk);
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-
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- res->aux_clk = devm_clk_get_optional(dev, "aux");
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- if (IS_ERR(res->aux_clk))
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- return PTR_ERR(res->aux_clk);
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-
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- res->ref_clk = devm_clk_get_optional(dev, "ref");
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- if (IS_ERR(res->ref_clk))
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- return PTR_ERR(res->ref_clk);
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+ res->clks[0].id = "iface";
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+ res->clks[1].id = "core";
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+ res->clks[2].id = "phy";
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+ res->clks[3].id = "aux";
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+ res->clks[4].id = "ref";
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+
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+ /* iface, core, phy are required */
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+ ret = devm_clk_bulk_get(dev, 3, res->clks);
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+ if (ret < 0)
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+ return ret;
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+
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+ /* aux, ref are optional */
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+ ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
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+ if (ret < 0)
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+ return ret;
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res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
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if (IS_ERR(res->pci_reset))
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@@ -292,17 +285,13 @@ static void qcom_pcie_deinit_2_1_0(struc
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{
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struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
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- clk_disable_unprepare(res->phy_clk);
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+ clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
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reset_control_assert(res->pci_reset);
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reset_control_assert(res->axi_reset);
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reset_control_assert(res->ahb_reset);
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reset_control_assert(res->por_reset);
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reset_control_assert(res->ext_reset);
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reset_control_assert(res->phy_reset);
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- clk_disable_unprepare(res->iface_clk);
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- clk_disable_unprepare(res->core_clk);
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- clk_disable_unprepare(res->aux_clk);
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- clk_disable_unprepare(res->ref_clk);
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regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
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}
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@@ -321,47 +310,45 @@ static int qcom_pcie_init_2_1_0(struct q
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return ret;
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}
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- ret = reset_control_assert(res->ahb_reset);
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+ ret = reset_control_deassert(res->ahb_reset);
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if (ret) {
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- dev_err(dev, "cannot assert ahb reset\n");
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- goto err_assert_ahb;
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+ dev_err(dev, "cannot deassert ahb reset\n");
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+ goto err_deassert_ahb;
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}
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- ret = clk_prepare_enable(res->iface_clk);
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+ ret = reset_control_deassert(res->ext_reset);
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if (ret) {
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- dev_err(dev, "cannot prepare/enable iface clock\n");
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- goto err_assert_ahb;
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+ dev_err(dev, "cannot deassert ext reset\n");
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+ goto err_deassert_ext;
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}
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- ret = clk_prepare_enable(res->core_clk);
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+ ret = reset_control_deassert(res->phy_reset);
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if (ret) {
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- dev_err(dev, "cannot prepare/enable core clock\n");
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- goto err_clk_core;
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+ dev_err(dev, "cannot deassert phy reset\n");
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+ goto err_deassert_phy;
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}
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- ret = clk_prepare_enable(res->aux_clk);
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+ ret = reset_control_deassert(res->pci_reset);
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if (ret) {
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- dev_err(dev, "cannot prepare/enable aux clock\n");
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- goto err_clk_aux;
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+ dev_err(dev, "cannot deassert pci reset\n");
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+ goto err_deassert_pci;
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}
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- ret = clk_prepare_enable(res->ref_clk);
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+ ret = reset_control_deassert(res->por_reset);
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if (ret) {
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- dev_err(dev, "cannot prepare/enable ref clock\n");
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- goto err_clk_ref;
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+ dev_err(dev, "cannot deassert por reset\n");
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+ goto err_deassert_por;
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}
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- ret = reset_control_deassert(res->ahb_reset);
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+ ret = reset_control_deassert(res->axi_reset);
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if (ret) {
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- dev_err(dev, "cannot deassert ahb reset\n");
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- goto err_deassert_ahb;
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+ dev_err(dev, "cannot deassert axi reset\n");
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+ goto err_deassert_axi;
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}
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- ret = reset_control_deassert(res->ext_reset);
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- if (ret) {
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- dev_err(dev, "cannot deassert ext reset\n");
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- goto err_deassert_ahb;
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- }
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+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
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+ if (ret)
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+ goto err_clks;
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/* enable PCIe clocks and resets */
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val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
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@@ -393,36 +380,6 @@ static int qcom_pcie_init_2_1_0(struct q
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val |= PHY_REFCLK_SSP_EN;
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writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
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- ret = reset_control_deassert(res->phy_reset);
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- if (ret) {
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- dev_err(dev, "cannot deassert phy reset\n");
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- return ret;
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- }
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-
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- ret = reset_control_deassert(res->pci_reset);
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- if (ret) {
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- dev_err(dev, "cannot deassert pci reset\n");
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- return ret;
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- }
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-
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- ret = reset_control_deassert(res->por_reset);
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- if (ret) {
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- dev_err(dev, "cannot deassert por reset\n");
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- return ret;
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- }
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-
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- ret = reset_control_deassert(res->axi_reset);
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- if (ret) {
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- dev_err(dev, "cannot deassert axi reset\n");
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- return ret;
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- }
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-
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- ret = clk_prepare_enable(res->phy_clk);
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- if (ret) {
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- dev_err(dev, "cannot prepare/enable phy clock\n");
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- goto err_deassert_ahb;
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- }
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-
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/* wait for clock acquisition */
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usleep_range(1000, 1500);
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@@ -435,15 +392,19 @@ static int qcom_pcie_init_2_1_0(struct q
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return 0;
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+err_clks:
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+ reset_control_assert(res->axi_reset);
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+err_deassert_axi:
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+ reset_control_assert(res->por_reset);
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+err_deassert_por:
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+ reset_control_assert(res->pci_reset);
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+err_deassert_pci:
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+ reset_control_assert(res->phy_reset);
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+err_deassert_phy:
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+ reset_control_assert(res->ext_reset);
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+err_deassert_ext:
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+ reset_control_assert(res->ahb_reset);
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err_deassert_ahb:
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- clk_disable_unprepare(res->ref_clk);
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-err_clk_ref:
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- clk_disable_unprepare(res->aux_clk);
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-err_clk_aux:
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- clk_disable_unprepare(res->core_clk);
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-err_clk_core:
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- clk_disable_unprepare(res->iface_clk);
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-err_assert_ahb:
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regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
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return ret;
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