9 Commits (7da001d068c90581bd8104a184d9aa45fbc4cf48)

Author	SHA1	Message	Date
Gabor Juhos	40a5f5c16e	ar71xx: define NAND controller base address and register size for AR934X/QCA955x ... SVN-Revision: 33382	2012-09-12 19:06:38 +00:00
Gabor Juhos	2e0e38ad69	ar71xx: fix QCA955X_EHCI_SIZE ... SVN-Revision: 33360	2012-09-10 14:32:54 +00:00
Gabor Juhos	94bac7366c	ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934x ... SVN-Revision: 33343	2012-09-09 14:05:20 +00:00
Gabor Juhos	f4be8a76de	ar71xx: fix CPU/DDR frequency calculation for SRIF PLLs on AR934x ... SVN-Revision: 33335	2012-09-08 13:39:09 +00:00
Gabor Juhos	d1b237b335	ar71xx: add initial support for the QCA955X SoCs ... SVN-Revision: 32606	2012-07-05 08:26:47 +00:00
Gabor Juhos	7284cf73d6	ar71xx: refactor PCI code to allow registering multiple PCI controllers ... SVN-Revision: 32605	2012-07-05 08:26:45 +00:00
Gabor Juhos	56f2e08537	ar71xx: update 3.3 patches ... SVN-Revision: 31602	2012-05-05 13:56:35 +00:00
Gabor Juhos	e9b45ebaba	ar71xx: add AR934x specific interface speed setup for ge0 ... SVN-Revision: 31017	2012-03-19 11:11:20 +00:00
Gabor Juhos	32a18a05f8	ar71xx: add preliminary support for 3.3 ... SVN-Revision: 30410	2012-02-10 11:53:56 +00:00