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2 Commits (783fc8e55354cc2f6a5891c2c5647a6179ddd86f)

Author SHA1 Message Date
Tomasz Maciej Nowak 2d61f8821c mvebu: cortexa9: correct cpu subtype 
Armada 370  processors have only 16 double-precision registers. The
change introduced by 8dcc108760 ("toolchain: ARM: Fix toolchain
compilation for gcc 8.x") switched accidentally the toolchain for mvebu
cortexa9 subtarget to cpu type with 32 double-precision registers. This
stems from gcc defaults which assume "vfpv3-d32" if only "vfpv3" as mfpu
is specified. That change resulted in unusable image, in which kernel
will kill userspace as soon as it causing "Illegal instruction".

Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272
Fixes: 8dcc108760 ("toolchain: ARM: Fix toolchain compilation for
gcc 8.x")
Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
 2020-03-28 22:58:36 +01:00
Hauke Mehrtens be3da900cd mvebu: Add subtarget for Cortex A9 build 
This is in preparation for adding a subtarget for the Cortex A53 later.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
 2018-03-10 01:15:21 +01:00