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7 Commits (31469aebd4c737ba891ceffc58db59c6b039445c)

Author SHA1 Message Date
John Crispin 231d9d5327 Revert "intel-microcode: create early load microcode image" 
This reverts commit 022ffb56b2.

Signed-off-by: John Crispin <john@phrozen.org>
 2018-11-27 18:58:37 +01:00
Tomasz Maciej Nowak 022ffb56b2 intel-microcode: create early load microcode image 
Create initrd image with packed microcode. This'll allow to load it at
early boot stage.

Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
 2018-11-26 12:05:44 +01:00
Tomasz Maciej Nowak ad83fde30d intel-microcode: remove dependency on iucode-tool 
It is not necessary to have iucode-tool present on target system to have
functional intel-microcode package. The build time dependency is kept.

Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
 2018-11-26 12:05:44 +01:00
Hauke Mehrtens 90bb790fbf intel-microcode: update to version 20180807a 
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
 2018-10-07 02:12:06 +02:00
Zoltan HERPAI f4d3047671 firmware: intel-microcode: bump to 20180703 
* New upstream microcode data file 20180703
    + Updated Microcodes:
      sig 0x000206d6, pf_mask 0x6d, 2018-05-08, rev 0x061d, size 18432
      sig 0x000206d7, pf_mask 0x6d, 2018-05-08, rev 0x0714, size 19456
      sig 0x000306e4, pf_mask 0xed, 2018-04-25, rev 0x042d, size 15360
      sig 0x000306e7, pf_mask 0xed, 2018-04-25, rev 0x0714, size 17408
      sig 0x000306f2, pf_mask 0x6f, 2018-04-20, rev 0x003d, size 33792
      sig 0x000306f4, pf_mask 0x80, 2018-04-20, rev 0x0012, size 17408
      sig 0x000406f1, pf_mask 0xef, 2018-04-19, rev 0xb00002e, size 28672
      sig 0x00050654, pf_mask 0xb7, 2018-05-15, rev 0x200004d, size 31744
      sig 0x00050665, pf_mask 0x10, 2018-04-20, rev 0xe00000a, size 18432
      sig 0x000706a1, pf_mask 0x01, 2017-12-26, rev 0x0022, size 73728
    + First batch of fixes for: Intel SA-00115, CVE-2018-3639, CVE-2018-3640
    + Implements IBRS/IBPB/STIPB support, Spectre-v2 mitigation
    + SSBD support (Spectre-v4 mitigation) and fix Spectre-v3a for:
      Sandybridge server, Ivy Bridge server, Haswell server, Skylake server,
      Broadwell server, a few HEDT Core i7/i9 models that are actually gimped
      server dies.

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
 2018-08-09 01:00:06 +02:00
Zoltan HERPAI 3db9d6e57d intel-microcode: update to 20180312 
- Update microcode for 24 CPU types
- Implements IBRS/IBPB/STIPB support, Spectre-v2 mitigation for:
  Sandybridge, Ivy Bridge, Haswell, Broadwell, Skylake, Kaby Lake,
  Coffee Lake
- Missing production updates:
   - Broadwell-E/EX Xeons (sig 0x406f1)
   - Anniedale/Morefield, Apollo Lake, Avoton, Cherry Trail, Braswell,
     Gemini Lake, Denverton
- New Microcodes:
   - sig 0x00050653, pf_mask 0x97, 2018-01-29, rev 0x1000140
   - sig 0x00050665, pf_mask 0x10, 2018-01-22, rev 0xe000009

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
 2018-03-21 23:24:09 +01:00
Zoltan HERPAI 01020bc74d firmware: add microcode package for Intel 
Compiling the Intel microcode package results in a
microcode.bin and a microcode-64.bin. As we can
decide based on the subtarget which should be used,
we'll only split the required .bin file with
iucode-tool.

x64 will get the intel-microcode-64.bin
All other variants will get intel-microcode.bin

The microcodes will be updated from preinit via a common
script - that's the earliest place where we can do it.

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
 2018-02-11 14:39:21 +01:00