mirror of https://github.com/hak5/openwrt.git
ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344
Some AR9344 boards do very poorly with the default settings and need custom rxdv-delay, rxd-delay, txd-delay, txen-delay flags to perform reasonably. In this case the WD My Net Wi-Fi Range Extender can not even manage 10Mbps on a 1Gbit link: root@AR9344:~# iperf3 -s ----------------------------------------------------------- Server listening on 5201 ----------------------------------------------------------- Accepted connection from client [...] [ 5] local [...] connected to client [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 1.09 MBytes 9.16 Mbits/sec [ 5] 1.00-2.00 sec 895 KBytes 7.33 Mbits/sec [ 5] 2.00-3.00 sec 762 KBytes 6.25 Mbits/sec [...] [ 5] 10.00-10.03 sec 17.0 KBytes 4.74 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.03 sec 9.00 MBytes 7.52 Mbits/sec with but with the correct settings in place, it does much better: root@AR9344:~# iperf3 -s ----------------------------------------------------------- Server listening on 5201 ----------------------------------------------------------- Accepted connection from client [...] [ 5] local [...] connected to client [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 23.1 MBytes 193 Mbits/sec [ 5] 1.00-2.00 sec 23.1 MBytes 194 Mbits/sec [ 5] 2.00-3.00 sec 23.2 MBytes 195 Mbits/sec [...] [ 5] 10.00-10.04 sec 710 KBytes 180 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.04 sec 237 MBytes 198 Mbits/sec The tx data and enable delay bits definitions are taken from Atheros' AR9344 Data Sheet Section "8.6.1 Ethernet Configuration (ETH_CFG)" on page 153. Signed-off-by: Christian Lamparter <chunkeey@gmail.com>openwrt-19.07
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7b1b49bd32
commit
f3ffac90bc
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@ -57,6 +57,14 @@ static void ag71xx_setup_gmac_934x(struct device_node *np, void __iomem *base)
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ag71xx_of_bit(np, "switch-phy-swap", &val, AR934X_ETH_CFG_SW_PHY_SWAP);
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ag71xx_of_bit(np, "switch-phy-swap", &val, AR934X_ETH_CFG_SW_PHY_SWAP);
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ag71xx_of_bit(np, "switch-only-mode", &val,
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ag71xx_of_bit(np, "switch-only-mode", &val,
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AR934X_ETH_CFG_SW_ONLY_MODE);
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AR934X_ETH_CFG_SW_ONLY_MODE);
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ag71xx_of_set(np, "rxdv-delay", &val,
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AR934X_ETH_CFG_RDV_DELAY_SHIFT, 0x3);
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ag71xx_of_set(np, "rxd-delay", &val,
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AR934X_ETH_CFG_RXD_DELAY_SHIFT, 0x3);
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ag71xx_of_set(np, "txd-delay", &val,
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AR934X_ETH_CFG_TXD_DELAY_SHIFT, 0x3);
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ag71xx_of_set(np, "txen-delay", &val,
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AR934X_ETH_CFG_TXE_DELAY_SHIFT, 0x3);
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__raw_writel(val, base + AR934X_GMAC_REG_ETH_CFG);
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__raw_writel(val, base + AR934X_GMAC_REG_ETH_CFG);
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}
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}
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@ -650,7 +650,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
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/*
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/*
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* SRIF block
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* SRIF block
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@@ -552,4 +1007,318 @@
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@@ -552,4 +1007,322 @@
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#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
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#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
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#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
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#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
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@ -876,6 +876,10 @@ Signed-off-by: John Crispin <john@phrozen.org>
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+#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
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+#define AR934X_ETH_CFG_RDV_DELAY BIT(16)
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+#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
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+#define AR934X_ETH_CFG_RDV_DELAY_MASK 0x3
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+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
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+#define AR934X_ETH_CFG_RDV_DELAY_SHIFT 16
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+#define AR934X_ETH_CFG_TXD_DELAY_MASK 0x3
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+#define AR934X_ETH_CFG_TXD_DELAY_SHIFT 18
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+#define AR934X_ETH_CFG_TXE_DELAY_MASK 0x3
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+#define AR934X_ETH_CFG_TXE_DELAY_SHIFT 20
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+
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+
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+/*
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+/*
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+ * QCA953X GMAC Interface
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+ * QCA953X GMAC Interface
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