hak5
/
openwrt
mirror of https://github.com/hak5/openwrt.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

lantiq: kernel 4.14: update patches and config 

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Mathias Kresin <dev@kresin.me>
openwrt-18.06
Hauke Mehrtens 2017-11-12 23:06:30 +01:00 committed by Mathias Kresin
parent 5eeaba31b8
commit f1d84023cb
35 changed files with 333 additions and 3208 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target/linux/lantiq/ase/config-4.14
View File

@ -3,6 +3,7 @@ CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
CONFIG_CPU_MIPSR1=y
CONFIG_CRC16=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_FIRMWARE_MEMMAP=y

35
target/linux/lantiq/config-4.14
View File

@ -5,12 +5,21 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
# CONFIG_ARCH_HAS_GCOV_PROFILE_ALL is not set
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
# CONFIG_ARCH_HAS_SG_CHAIN is not set
# CONFIG_ARCH_HAS_STRICT_KERNEL_RWX is not set
# CONFIG_ARCH_HAS_STRICT_MODULE_RWX is not set
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
CONFIG_ARCH_MMAP_RND_BITS_MAX=15
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX is not set
# CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
CONFIG_ARCH_SUPPORTS_UPROBES=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARCH_USE_BUILTIN_BSWAP=y
CONFIG_ARCH_USE_QUEUED_RWLOCKS=y
CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y
# CONFIG_ARCH_WANTS_THP_SWAP is not set
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
CONFIG_CEVT_R4K=y
CONFIG_CLKDEV_LOOKUP=y
@ -36,18 +45,27 @@ CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_WORKQUEUE=y
CONFIG_CSRC_R4K=y
CONFIG_DMA_NONCOHERENT=y
# CONFIG_DMA_NOOP_OPS is not set
# CONFIG_DMA_VIRT_OPS is not set
# CONFIG_DRM_LIB_RANDOM is not set
CONFIG_DTC=y
# CONFIG_DT_EASY50712 is not set
CONFIG_EARLY_PRINTK=y
CONFIG_ETHERNET_PACKET_MANGLE=y
CONFIG_EXPORTFS=y
CONFIG_FIXED_PHY=y
CONFIG_FUTEX_PI=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_IO=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_IPI=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_TIME_VSYSCALL=y
@ -55,6 +73,7 @@ CONFIG_GPIOLIB=y
CONFIG_GPIO_MM_LANTIQ=y
CONFIG_GPIO_STP_XWAY=y
CONFIG_GPIO_SYSFS=y
# CONFIG_GRO_CELLS is not set
CONFIG_HANDLE_DOMAIN_IRQ=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
@ -71,6 +90,7 @@ CONFIG_HAVE_CBPF_JIT=y
CONFIG_HAVE_CC_STACKPROTECTOR=y
CONFIG_HAVE_CLK=y
CONFIG_HAVE_CONTEXT_TRACKING=y
CONFIG_HAVE_COPY_THREAD_TLS=y
CONFIG_HAVE_C_RECORDMCOUNT=y
CONFIG_HAVE_DEBUG_KMEMLEAK=y
CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
@ -104,6 +124,7 @@ CONFIG_HZ_PERIODIC=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MIPS_CPU=y
CONFIG_IRQ_WORK=y
@ -114,7 +135,10 @@ CONFIG_LANTIQ_WDT=y
# CONFIG_LANTIQ_XRX200 is not set
CONFIG_LEDS_GPIO=y
CONFIG_LIBFDT=y
CONFIG_MDIO_BOARDINFO=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MFD_CORE=y
CONFIG_MFD_SYSCON=y
CONFIG_MIPS=y
CONFIG_MIPS_ASID_BITS=8
CONFIG_MIPS_ASID_SHIFT=0
@ -160,13 +184,20 @@ CONFIG_PCI_DRIVERS_LEGACY=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHY_LANTIQ_RCU_USB2=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_LANTIQ=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PINCTRL_XWAY=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_SYSCON=y
CONFIG_PSB6970_PHY=y
# CONFIG_RCU_NEED_SEGCBLIST is not set
# CONFIG_RCU_STALL_COMMON is not set
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RESET_LANTIQ=y
CONFIG_RTL8366RB_PHY=y
CONFIG_RTL8366_SMI=y
# CONFIG_SCHED_INFO is not set
@ -194,6 +225,8 @@ CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_SYS_SUPPORTS_MULTITHREADING=y
CONFIG_THIN_ARCHIVES=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TINY_SRCU=y
CONFIG_USE_OF=y
# CONFIG_XRX200_PHY_FW is not set

2
target/linux/lantiq/falcon/config-4.14
View File

@ -1,8 +1,10 @@
# CONFIG_MFD_CORE is not set
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
CONFIG_PINCTRL_FALCON=y
# CONFIG_PSB6970_PHY is not set
# CONFIG_RESET_LANTIQ is not set
# CONFIG_RTL8366_SMI is not set
CONFIG_SOC_FALCON=y
# CONFIG_SOC_TYPE_XWAY is not set

18
target/linux/lantiq/patches-4.14/0001-MIPS-lantiq-add-pcie-driver.patch
View File

@ -41,15 +41,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -17,6 +17,7 @@ config SOC_XWAY
@@ -18,6 +18,7 @@ config SOC_XWAY
bool "XWAY"
select SOC_TYPE_XWAY
select HW_HAS_PCI
+ select ARCH_SUPPORTS_MSI
select MFD_SYSCON
select MFD_CORE
config SOC_FALCON
bool "FALCON"
@@ -47,6 +48,15 @@ config PCI_LANTIQ
@@ -50,6 +51,15 @@ config PCI_LANTIQ
bool "PCI Support"
depends on SOC_XWAY && PCI
@ -67,7 +67,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
depends on SOC_XWAY
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -48,6 +48,8 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o
@@ -49,6 +49,8 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o
obj-$(CONFIG_SOC_MT7620) += pci-mt7620.o
obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o
obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
@ -176,7 +176,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
@@ -25,5 +31,10 @@ int pcibios_plat_dev_init(struct pci_dev
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
+#ifdef CONFIG_PCIE_LANTIQ
+ if (pci_find_capability(dev, PCI_CAP_ID_EXP))
@ -4143,7 +4143,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+
--- a/arch/mips/pci/pci-legacy.c
+++ b/arch/mips/pci/pci-legacy.c
@@ -300,3 +300,30 @@ char *__init pcibios_setup(char *str)
@@ -309,3 +309,30 @@ char *__init pcibios_setup(char *str)
return pcibios_plat_setup(str);
return str;
}
@ -5494,7 +5494,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
(transaction layer end-to-end CRC checking).
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -1250,6 +1250,8 @@ void pci_walk_bus(struct pci_bus *top, i
@@ -1300,6 +1300,8 @@ void pci_walk_bus(struct pci_bus *top, i
void *userdata);
int pci_cfg_space_size(struct pci_dev *dev);
unsigned char pci_bus_max_busnr(struct pci_bus *bus);
@ -5505,7 +5505,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
unsigned long type);
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1056,6 +1056,12 @@
@@ -1061,6 +1061,12 @@
#define PCI_DEVICE_ID_SGI_LITHIUM 0x1002
#define PCI_DEVICE_ID_SGI_IOC4 0x100a

13
target/linux/lantiq/patches-4.14/0004-MIPS-lantiq-add-atm-hack.patch
View File

@ -431,7 +431,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
#include <asm/bootinfo.h>
#include <asm/irq_cpu.h>
@@ -100,6 +101,7 @@ void ltq_mask_and_ack_irq(struct irq_dat
@@ -96,6 +97,7 @@ void ltq_mask_and_ack_irq(struct irq_dat
ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
ltq_icu_w32(im, BIT(offset), isr);
}
@ -441,7 +441,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
{
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -63,6 +63,8 @@ void (*_dma_cache_wback)(unsigned long s
@@ -64,6 +64,8 @@ void (*_dma_cache_wback)(unsigned long s
void (*_dma_cache_inv)(unsigned long start, unsigned long size);
EXPORT_SYMBOL(_dma_cache_wback_inv);
@ -452,7 +452,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/include/uapi/linux/atm.h
+++ b/include/uapi/linux/atm.h
@@ -130,8 +130,14 @@
@@ -131,8 +131,14 @@
#define ATM_ABR 4
#define ATM_ANYCLASS 5 /* compatible with everything */
@ -469,16 +469,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
int max_pcr; /* maximum PCR in cells per second */
--- a/net/atm/common.c
+++ b/net/atm/common.c
@@ -62,11 +62,17 @@ static void vcc_remove_socket(struct soc
@@ -62,10 +62,16 @@ static void vcc_remove_socket(struct soc
write_unlock_irq(&vcc_sklist_lock);
}
+struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
+EXPORT_SYMBOL(ifx_atm_alloc_tx);
+
static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
static bool vcc_tx_ready(struct atm_vcc *vcc, unsigned int size)
{
struct sk_buff *skb;
struct sock *sk = sk_atm(vcc);
+ if (ifx_atm_alloc_tx != NULL)
@ -489,7 +488,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
--- a/net/atm/proc.c
+++ b/net/atm/proc.c
@@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_fil
@@ -155,7 +155,7 @@ static void *vcc_seq_next(struct seq_fil
static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
{
static const char *const class_name[] = {

16
target/linux/lantiq/patches-4.14/0008-MIPS-lantiq-backport-old-timer-code.patch
View File

@ -172,9 +172,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,4 +1,10 @@
-obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
+obj-y := prom.o sysctrl.o clk.o reset.o dma.o dcdc.o
@@ -1,3 +1,9 @@
-obj-y := prom.o sysctrl.o clk.o dma.o gptu.o dcdc.o
+obj-y := prom.o sysctrl.o clk.o dma.o dcdc.o
+
+ifdef CONFIG_SOC_AMAZON_SE
+obj-y += gptu.o
@ -183,10 +183,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+endif
obj-y += vmmc.o
--- /dev/null
+++ b/arch/mips/lantiq/xway/timer.c
@@ -0,0 +1,845 @@
@@ -0,0 +1,846 @@
+#ifndef CONFIG_SOC_AMAZON_SE
+
+#include <linux/kernel.h>
@ -201,6 +200,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+#include <linux/sched/signal.h>
+
+#include <asm/irq.h>
+#include <asm/div64.h>
@ -880,14 +880,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ int ret;
+ struct gptu_ioctl_param param;
+
+ if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
+ if (!access_ok(VERIFY_READ, (void __user *)arg, sizeof(struct gptu_ioctl_param)))
+ return -EFAULT;
+ copy_from_user(&param, (void *) arg, sizeof(param));
+ copy_from_user(&param, (void __user *)arg, sizeof(param));
+
+ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
+ || GPTU_SET_COUNTER) && param.timer < 2)
+ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
+ && !access_ok(VERIFY_WRITE, arg,
+ && !access_ok(VERIFY_WRITE, (void __user *)arg,
+ sizeof(struct gptu_ioctl_param)))
+ return -EFAULT;
+

2
target/linux/lantiq/patches-4.14/0020-MTD-lantiq-handle-NO_XIP-on-cfi0001-flash.patch
View File

@ -10,7 +10,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/drivers/mtd/maps/lantiq-flash.c
+++ b/drivers/mtd/maps/lantiq-flash.c
@@ -137,7 +137,11 @@ ltq_mtd_probe(struct platform_device *pd
@@ -131,7 +131,11 @@ ltq_mtd_probe(struct platform_device *pd
if (!ltq_mtd->map)
return -ENOMEM;

6
target/linux/lantiq/patches-4.14/0022-MTD-m25p80-allow-loading-mtd-name-from-OF.patch
View File

@ -22,8 +22,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
@@ -198,6 +199,10 @@ static int m25p_probe(struct spi_device
enum read_mode mode = SPI_NOR_NORMAL;
@@ -243,6 +244,10 @@ static int m25p_probe(struct spi_device
};
char *flash_name;
int ret;
+ const char __maybe_unused *of_mtd_name = NULL;
@ -33,7 +33,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
data = dev_get_platdata(&spi->dev);
@@ -227,6 +232,8 @@ static int m25p_probe(struct spi_device
@@ -281,6 +286,8 @@ static int m25p_probe(struct spi_device
if (data && data->name)
nor->mtd.name = data->name;

24
target/linux/lantiq/patches-4.14/0023-NET-PHY-adds-driver-for-lantiq-PHY11G.patch → target/linux/lantiq/patches-4.14/0023-NET-PHY-add-led-support-for-intel-xway.patch
View File

@ -24,34 +24,34 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+
+ /* store the led values if one was passed by the devicetree */
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp))
+ phy_write_mmd_indirect(phydev, XWAY_MMD_LEDCH, MDIO_MMD_VEND2, tmp);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp);
+
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp))
+ phy_write_mmd_indirect(phydev, XWAY_MMD_LEDCL, MDIO_MMD_VEND2, tmp);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp);
+
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp))
+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED0H, MDIO_MMD_VEND2, tmp);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp);
+
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp))
+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED0L, MDIO_MMD_VEND2, tmp);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp);
+
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp))
+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED1H, MDIO_MMD_VEND2, tmp);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp);
+
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp))
+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED1L, MDIO_MMD_VEND2, tmp);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp);
+
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp))
+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED3H, MDIO_MMD_VEND2, tmp);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp);
+
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp))
+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED3L, MDIO_MMD_VEND2, tmp);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp);
+
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp))
+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED3H, MDIO_MMD_VEND2, tmp);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp);
+
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp))
+ phy_write_mmd_indirect(phydev, XWAY_MMD_LED3L, MDIO_MMD_VEND2, tmp);
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp);
+
+ return 0;
+}
@ -66,8 +66,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
{
int err;
@@ -190,6 +235,7 @@ static int xway_gphy_config_init(struct
phy_write_mmd_indirect(phydev, XWAY_MMD_LED2H, MDIO_MMD_VEND2, ledxh);
phy_write_mmd_indirect(phydev, XWAY_MMD_LED2L, MDIO_MMD_VEND2, ledxl);
phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh);
phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl);
+ vr9_gphy_of_reg_init(phydev);
return 0;

364
target/linux/lantiq/patches-4.14/0024-NET-lantiq-adds-PHY11G-firmware-blobs.patch
View File

@ -1,364 +0,0 @@
From 77e89d5a28be35058041c79e9874ab26f222c603 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 22 Oct 2012 09:26:24 +0200
Subject: [PATCH 24/36] NET: lantiq: adds PHY11G firmware blobs
Signed-off-by: John Crispin <blogic@openwrt.org>
---
firmware/Makefile | 4 +
firmware/lantiq/COPYING | 286 +++++++++++++++++++++++++++++++++++++++++++++++
firmware/lantiq/README | 45 ++++++++
3 files changed, 335 insertions(+)
create mode 100644 firmware/lantiq/COPYING
create mode 100644 firmware/lantiq/README
--- a/firmware/Makefile
+++ b/firmware/Makefile
@@ -134,6 +134,10 @@ fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_P
fw-shipped-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda/xircom_pgs.fw
fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw
fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin
+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/xrx200_phy11g_a14.bin
+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/xrx200_phy11g_a22.bin
+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/xrx200_phy22f_a14.bin
+fw-shipped-$(CONFIG_LANTIQ_XRX200) += lantiq/xrx200_phy22f_a22.bin
fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin
fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-)
--- /dev/null
+++ b/firmware/lantiq/COPYING
@@ -0,0 +1,286 @@
+All firmware files are copyrighted by Lantiq Deutschland GmbH.
+The files have been extracted from header files found in Lantiq BSPs.
+If not stated otherwise all files are licensed under GPL.
+
+=======================================================================
+
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.) You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+ To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+ For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have. You must make sure that they, too, receive or can get the
+source code. And you must show them these terms so they know their
+rights.
+
+ We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+ Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software. If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+ Finally, any free program is threatened constantly by software
+patents. We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary. To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+ The precise terms and conditions for copying, distribution and
+modification follow.
+
+ GNU GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License. The "Program", below,
+refers to any such program or work, and a "work based on the Program"
+means either the Program or any derivative work under copyright law:
+that is to say, a work containing the Program or a portion of it,
+either verbatim or with modifications and/or translated into another
+language. (Hereinafter, translation is included without limitation in
+the term "modification".) Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope. The act of
+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+ 1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
+conspicuously and appropriately publish on each copy an appropriate
+copyright notice and disclaimer of warranty; keep intact all the
+notices that refer to this License and to the absence of any warranty;
+and give any other recipients of the Program a copy of this License
+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+ 2. You may modify your copy or copies of the Program or any portion
+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) You must cause the modified files to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ b) You must cause any work that you distribute or publish, that in
+ whole or in part contains or is derived from the Program or any
+ part thereof, to be licensed as a whole at no charge to all third
+ parties under the terms of this License.
+
+ c) If the modified program normally reads commands interactively
+ when run, you must cause it, when started running for such
+ interactive use in the most ordinary way, to print or display an
+ announcement including an appropriate copyright notice and a
+ notice that there is no warranty (or else, saying that you provide
+ a warranty) and that users may redistribute the program under
+ these conditions, and telling the user how to view a copy of this
+ License. (Exception: if the Program itself is interactive but
+ does not normally print such an announcement, your work based on
+ the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+ a) Accompany it with the complete corresponding machine-readable
+ source code, which must be distributed under the terms of Sections
+ 1 and 2 above on a medium customarily used for software interchange; or,
+
+ b) Accompany it with a written offer, valid for at least three
+ years, to give any third party, for a charge no more than your
+ cost of physically performing source distribution, a complete
+ machine-readable copy of the corresponding source code, to be
+ distributed under the terms of Sections 1 and 2 above on a medium
+ customarily used for software interchange; or,
+
+ c) Accompany it with the information you received as to the offer
+ to distribute corresponding source code. (This alternative is
+ allowed only for noncommercial distribution and only if you
+ received the program in object code or executable form with such
+ an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it. For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable. However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License. Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+ 5. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Program or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+ 6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+ 7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all. For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded. In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+ 9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation. If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+ 10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission. For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this. Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+ NO WARRANTY
+
+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+ END OF TERMS AND CONDITIONS
--- /dev/null
+++ b/firmware/lantiq/README
@@ -0,0 +1,45 @@
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# (C) Copyright 2007 - 2012
+# Lantiq Deutschland GmbH
+#
+# (C) Copyright 2012
+# Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
+#
+
+#
+# How to use
+#
+Configure kernel with:
+CONFIG_FW_LOADER=y
+CONFIG_EXTRA_FIRMWARE_DIR="FIRMWARE_DIR"
+CONFIG_EXTRA_FIRMWARE="FIRMWARE_FILES"
+
+where FIRMWARE_DIR should point to this git tree and FIRMWARE_FILES is a list
+of space separated files from list below.
+
+#
+# Firmware files
+#
+
+# GPHY core on Lantiq XWAY VR9 v1.1
+lantiq/xrx200_phy11g_a14.bin
+lantiq/xrx200_phy22f_a14.bin
+
+# GPHY core on Lantiq XWAY VR9 v1.2
+lantiq/xrx200_phy11g_a22.bin
+lantiq/xrx200_phy22f_a22.bin

60
target/linux/lantiq/patches-4.14/0025-NET-MIPS-lantiq-adds-xrx200-net.patch
View File

@ -16,7 +16,7 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -104,7 +104,13 @@ config LANTIQ_ETOP
@@ -107,7 +107,13 @@ config LANTIQ_ETOP
tristate "Lantiq SoC ETOP driver"
depends on SOC_TYPE_XWAY
---help---
@ -33,7 +33,7 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net
source "drivers/net/ethernet/mediatek/Kconfig"
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_NET_VENDOR_XSCALE) += xscal
@@ -50,6 +50,7 @@ obj-$(CONFIG_NET_VENDOR_XSCALE) += xscal
obj-$(CONFIG_JME) += jme.o
obj-$(CONFIG_KORINA) += korina.o
obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
@ -209,7 +209,7 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net
+};
--- /dev/null
+++ b/drivers/net/ethernet/lantiq_xrx200.c
@@ -0,0 +1,1851 @@
@@ -0,0 +1,1887 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
@ -240,6 +240,7 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net
+#include <linux/of_net.h>
+#include <linux/of_mdio.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+
+#include <xway_dma.h>
+#include <lantiq_soc.h>
@ -1460,16 +1461,12 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net
+static void xrx200_mdio_link(struct net_device *dev)
+{
+ struct xrx200_priv *priv = netdev_priv(dev);
+ bool link = false;
+ int i;
+
+ for (i = 0; i < priv->num_port; i++) {
+ if (!priv->port[i].phydev)
+ continue;
+
+ if (priv->port[i].phydev->link)
+ link = true;
+
+ if (priv->port[i].link != priv->port[i].phydev->link) {
+ xrx200_gmac_update(&priv->port[i]);
+ priv->port[i].link = priv->port[i].phydev->link;
@ -1478,8 +1475,6 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net
+ (priv->port[i].link)?("got"):("lost"));
+ }
+ }
+ if (netif_carrier_ok(dev) && !link)
+ netif_carrier_off(dev);
+}
+
+static inline int xrx200_mdio_poll(struct mii_bus *bus)
@ -1525,6 +1520,35 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net
+ return ltq_mdio_r32(MDIO_READ);
+}
+
+static int xrx200_phy_has_link(struct net_device *dev)
+{
+ struct xrx200_priv *priv = netdev_priv(dev);
+ int i;
+
+ for (i = 0; i < priv->num_port; i++) {
+ if (!priv->port[i].phydev)
+ continue;
+
+ if (priv->port[i].phydev->link)
+ return 1;
+ }
+
+ return 0;
+}
+
+static void xrx200_phy_link_change(struct phy_device *phydev, bool up, bool do_carrier)
+{
+ struct net_device *netdev = phydev->attached_dev;
+
+ if (do_carrier)
+ if (up)
+ netif_carrier_on(netdev);
+ else if (!xrx200_phy_has_link(netdev))
+ netif_carrier_off(netdev);
+
+ phydev->adjust_link(netdev);
+}
+
+static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port)
+{
+ struct xrx200_priv *priv = netdev_priv(dev);
@ -1557,7 +1581,7 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net
+ | SUPPORTED_TP);
+ phydev->advertising = phydev->supported;
+ port->phydev = phydev;
+ phydev->no_auto_carrier_off = true;
+ phydev->phy_link_change = xrx200_phy_link_change;
+
+ phy_attached_info(phydev);
+
@ -1880,7 +1904,6 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net
+ .ndo_start_xmit = xrx200_start_xmit,
+ .ndo_set_mac_address = eth_mac_addr,
+ .ndo_validate_addr = eth_validate_addr,
+ .ndo_change_mtu = eth_change_mtu,
+ .ndo_get_stats = xrx200_get_stats,
+ .ndo_tx_timeout = xrx200_tx_timeout,
+};
@ -1937,7 +1960,9 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net
+static int xrx200_probe(struct platform_device *pdev)
+{
+ struct resource *res[4];
+ struct device_node *mdio_np, *iface_np;
+ struct device_node *mdio_np, *iface_np, *phy_np;
+ struct of_phandle_iterator it;
+ int err;
+ int i;
+
+ /* load the memory ranges */
@ -1958,6 +1983,17 @@ Subject: [PATCH 25/36] NET: MIPS: lantiq: adds xrx200-net
+ return -ENOMEM;
+ }
+
+ of_for_each_phandle(&it, err, pdev->dev.of_node, "lantiq,phys", NULL, 0) {
+ phy_np = it.node;
+ if (phy_np) {
+ struct platform_device *phy = of_find_device_by_node(phy_np);
+
+ of_node_put(phy_np);
+ if (!platform_get_drvdata(phy))
+ return -EPROBE_DEFER;
+ }
+ }
+
+ /* get the clock */
+ xrx200_hw.clk = clk_get(&pdev->dev, NULL);
+ if (IS_ERR(xrx200_hw.clk)) {

53
target/linux/lantiq/patches-4.14/0026-NET-multi-phy-support.patch
View File

@ -1,53 +0,0 @@
From c6feeeb407a3b8a6597ae377ba4dd138e185e3dd Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 27 Jul 2014 09:38:50 +0100
Subject: [PATCH 26/36] NET: multi phy support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/net/phy/phy.c | 9 ++++++---
include/linux/phy.h | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -1032,7 +1032,8 @@ void phy_state_machine(struct work_struc
/* If the link is down, give up on negotiation for now */
if (!phydev->link) {
phydev->state = PHY_NOLINK;
- netif_carrier_off(phydev->attached_dev);
+ if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(phydev->attached_dev);
phydev->adjust_link(phydev->attached_dev);
break;
}
@@ -1124,7 +1125,8 @@ void phy_state_machine(struct work_struc
netif_carrier_on(phydev->attached_dev);
} else {
phydev->state = PHY_NOLINK;
- netif_carrier_off(phydev->attached_dev);
+ if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(phydev->attached_dev);
}
phydev->adjust_link(phydev->attached_dev);
@@ -1136,7 +1138,8 @@ void phy_state_machine(struct work_struc
case PHY_HALTED:
if (phydev->link) {
phydev->link = 0;
- netif_carrier_off(phydev->attached_dev);
+ if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(phydev->attached_dev);
phydev->adjust_link(phydev->attached_dev);
do_suspend = true;
}
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -369,6 +369,7 @@ struct phy_device {
bool is_pseudo_fixed_link;
bool has_fixups;
bool suspended;
+ bool no_auto_carrier_off;
enum phy_state state;

74
target/linux/lantiq/patches-4.14/0028-NET-lantiq-various-etop-fixes.patch
View File

@ -328,10 +328,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
struct ltq_etop_priv *priv = netdev_priv(dev);
- int i;
+ int mii_mode = priv->mii_mode;
+
+ clk_enable(priv->clk_ppe);
- ltq_pmu_enable(PMU_PPE);
+ clk_enable(priv->clk_ppe);
- switch (priv->pldata->mii_mode) {
+ if (of_machine_is_compatible("lantiq,ar9")) {
+ ltq_etop_gbit_init(dev);
+ /* force the etops link to the gbit to MII */
@ -340,8 +341,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
+ ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
+ MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
- switch (priv->pldata->mii_mode) {
+
+ switch (mii_mode) {
case PHY_INTERFACE_MODE_RMII:
- ltq_etop_w32_mask(ETOP_MII_MASK,
@ -440,19 +440,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
}
static void
@@ -303,7 +448,10 @@ ltq_etop_get_drvinfo(struct net_device *
static int
ltq_etop_nway_reset(struct net_device *dev)
{
- return phy_start_aneg(dev->phydev);
+ if (dev->phydev)
+ return phy_start_aneg(dev->phydev);
+ else
+ return 0;
}
static const struct ethtool_ops ltq_etop_ethtool_ops = {
@@ -314,6 +462,39 @@ static const struct ethtool_ops ltq_etop
@@ -308,6 +453,39 @@ static const struct ethtool_ops ltq_etop
};
static int
@ -492,7 +480,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
{
u32 val = MDIO_REQUEST |
@@ -321,9 +502,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
@@ -315,9 +493,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, in
((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
phy_data;
@ -504,7 +492,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
return 0;
}
@@ -334,12 +515,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
@@ -328,12 +506,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, in
((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
@ -521,7 +509,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
return val;
}
@@ -354,8 +535,18 @@ ltq_etop_mdio_probe(struct net_device *d
@@ -348,8 +526,18 @@ ltq_etop_mdio_probe(struct net_device *d
{
struct ltq_etop_priv *priv = netdev_priv(dev);
struct phy_device *phydev;
@ -541,7 +529,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
if (!phydev) {
netdev_err(dev, "no PHY found\n");
@@ -363,21 +554,18 @@ ltq_etop_mdio_probe(struct net_device *d
@@ -357,21 +545,18 @@ ltq_etop_mdio_probe(struct net_device *d
}
phydev = phy_connect(dev, phydev_name(phydev),
@ -568,7 +556,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
phydev->advertising = phydev->supported;
phy_attached_info(phydev);
@@ -398,8 +586,13 @@ ltq_etop_mdio_init(struct net_device *de
@@ -392,8 +577,13 @@ ltq_etop_mdio_init(struct net_device *de
}
priv->mii_bus->priv = dev;
@ -584,7 +572,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
priv->mii_bus->name = "ltq_mii";
snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
priv->pdev->name, priv->pdev->id);
@@ -436,17 +629,19 @@ static int
@@ -430,17 +620,19 @@ static int
ltq_etop_open(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
@ -613,7 +601,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
netif_tx_start_all_queues(dev);
return 0;
}
@@ -455,18 +650,19 @@ static int
@@ -449,18 +641,19 @@ static int
ltq_etop_stop(struct net_device *dev)
{
struct ltq_etop_priv *priv = netdev_priv(dev);
@ -643,7 +631,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
return 0;
}
@@ -476,16 +672,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
@@ -470,16 +663,16 @@ ltq_etop_tx(struct sk_buff *skb, struct
int queue = skb_get_queue_mapping(skb);
struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
struct ltq_etop_priv *priv = netdev_priv(dev);
@ -665,7 +653,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
netdev_err(dev, "tx ring full\n");
netif_tx_stop_queue(txq);
return NETDEV_TX_BUSY;
@@ -493,7 +689,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
@@ -487,7 +680,7 @@ ltq_etop_tx(struct sk_buff *skb, struct
/* dma needs to start on a 16 byte aligned address */
byte_offset = CPHYSADDR(skb->data) % 16;
@ -674,7 +662,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
netif_trans_update(dev);
@@ -503,11 +699,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
@@ -497,11 +690,11 @@ ltq_etop_tx(struct sk_buff *skb, struct
wmb();
desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
@ -689,19 +677,19 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
netif_tx_stop_queue(txq);
return NETDEV_TX_OK;
@@ -522,8 +718,10 @@ ltq_etop_change_mtu(struct net_device *d
struct ltq_etop_priv *priv = netdev_priv(dev);
unsigned long flags;
@@ -515,8 +708,10 @@ ltq_etop_change_mtu(struct net_device *d
+ int max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
dev->mtu = new_mtu;
+ int max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
+
spin_lock_irqsave(&priv->lock, flags);
- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu,
+ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max,
LTQ_ETOP_IGPLEN);
spin_unlock_irqrestore(&priv->lock, flags);
}
@@ -592,6 +790,9 @@ ltq_etop_init(struct net_device *dev)
spin_lock_irqsave(&priv->lock, flags);
- ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
+ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max, LTQ_ETOP_IGPLEN);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
@@ -584,6 +779,9 @@ ltq_etop_init(struct net_device *dev)
if (err)
goto err_hw;
ltq_etop_change_mtu(dev, 1500);
@ -711,7 +699,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
if (!is_valid_ether_addr(mac.sa_data)) {
@@ -609,9 +810,10 @@ ltq_etop_init(struct net_device *dev)
@@ -601,9 +799,10 @@ ltq_etop_init(struct net_device *dev)
dev->addr_assign_type = NET_ADDR_RANDOM;
ltq_etop_set_multicast_list(dev);
@ -725,7 +713,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
return 0;
err_netdev:
@@ -631,6 +833,9 @@ ltq_etop_tx_timeout(struct net_device *d
@@ -623,6 +822,9 @@ ltq_etop_tx_timeout(struct net_device *d
err = ltq_etop_hw_init(dev);
if (err)
goto err_hw;
@ -735,7 +723,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
netif_trans_update(dev);
netif_wake_queue(dev);
return;
@@ -654,14 +859,19 @@ static const struct net_device_ops ltq_e
@@ -646,14 +848,19 @@ static const struct net_device_ops ltq_e
.ndo_tx_timeout = ltq_etop_tx_timeout,
};
@ -759,7 +747,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
@@ -687,31 +897,62 @@ ltq_etop_probe(struct platform_device *p
@@ -679,31 +886,62 @@ ltq_etop_probe(struct platform_device *p
goto err_out;
}
@ -837,7 +825,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
err = register_netdev(dev);
if (err)
@@ -740,31 +981,22 @@ ltq_etop_remove(struct platform_device *
@@ -732,31 +970,22 @@ ltq_etop_remove(struct platform_device *
return 0;
}

14
target/linux/lantiq/patches-4.14/0030-GPIO-add-named-gpio-exports.patch
View File

@ -22,7 +22,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
#include "gpiolib.h"
@@ -538,3 +540,73 @@ void of_gpiochip_remove(struct gpio_chip
@@ -506,3 +508,73 @@ void of_gpiochip_remove(struct gpio_chip
gpiochip_remove_pin_ranges(chip);
of_node_put(chip->of_node);
}
@ -98,7 +98,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#endif
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -126,6 +126,12 @@ static inline int gpio_export(unsigned g
@@ -127,6 +127,12 @@ static inline int gpio_export(unsigned g
return gpiod_export(gpio_to_desc(gpio), direction_may_change);
}
@ -113,7 +113,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
{
--- a/include/linux/gpio/consumer.h
+++ b/include/linux/gpio/consumer.h
@@ -427,6 +427,7 @@ static inline struct gpio_desc *devm_get
@@ -451,6 +451,7 @@ struct gpio_desc *devm_fwnode_get_gpiod_
#if IS_ENABLED(CONFIG_GPIOLIB) && IS_ENABLED(CONFIG_GPIO_SYSFS)
@ -121,7 +121,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
int gpiod_export_link(struct device *dev, const char *name,
struct gpio_desc *desc);
@@ -434,6 +435,13 @@ void gpiod_unexport(struct gpio_desc *de
@@ -458,6 +459,13 @@ void gpiod_unexport(struct gpio_desc *de
#else /* CONFIG_GPIOLIB && CONFIG_GPIO_SYSFS */
@ -137,7 +137,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
{
--- a/drivers/gpio/gpiolib-sysfs.c
+++ b/drivers/gpio/gpiolib-sysfs.c
@@ -544,7 +544,7 @@ static struct class gpio_class = {
@@ -553,7 +553,7 @@ static struct class gpio_class = {
*
* Returns zero on success, else an error.
*/
@ -146,7 +146,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
{
struct gpio_chip *chip;
struct gpio_device *gdev;
@@ -606,6 +606,8 @@ int gpiod_export(struct gpio_desc *desc,
@@ -615,6 +615,8 @@ int gpiod_export(struct gpio_desc *desc,
offset = gpio_chip_hwgpio(desc);
if (chip->names && chip->names[offset])
ioname = chip->names[offset];
@ -155,7 +155,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
dev = device_create_with_groups(&gpio_class, &gdev->dev,
MKDEV(0, 0), data, gpio_groups,
@@ -627,6 +629,12 @@ err_unlock:
@@ -636,6 +638,12 @@ err_unlock:
gpiod_dbg(desc, "%s: status %d\n", __func__, status);
return status;
}

4
target/linux/lantiq/patches-4.14/0031-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch
View File

@ -18,7 +18,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -643,6 +643,16 @@ config I2C_MESON
@@ -696,6 +696,16 @@ config I2C_MESON
If you say yes to this option, support will be included for the
I2C interface on the Amlogic Meson family of SoCs.
@ -37,7 +37,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
depends on PPC
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_I2C_IMX) += i2c-imx.o
@@ -68,6 +68,7 @@ obj-$(CONFIG_I2C_IMX_LPI2C) += i2c-imx-l
obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o
obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o

9
target/linux/lantiq/patches-4.14/0035-owrt-lantiq-wifi-and-ethernet-eeprom-handling.patch
View File

@ -27,14 +27,13 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
#endif /* _LTQ_XWAY_H__ */
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -8,4 +8,7 @@ endif
@@ -7,3 +7,6 @@ obj-y += timer.o
endif
obj-y += vmmc.o
+
+obj-y += eth_mac.o
+obj-$(CONFIG_PCI) += ath5k_eep.o
+
obj-$(CONFIG_XRX200_PHY_FW) += xrx200_phy_fw.o
--- /dev/null
+++ b/arch/mips/lantiq/xway/ath5k_eep.c
@@ -0,0 +1,136 @@
@ -204,7 +203,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+early_param("ethaddr", setup_ethaddr);
--- a/drivers/net/ethernet/lantiq_etop.c
+++ b/drivers/net/ethernet/lantiq_etop.c
@@ -794,7 +794,11 @@ ltq_etop_init(struct net_device *dev)
@@ -783,7 +783,11 @@ ltq_etop_init(struct net_device *dev)
if (err)
goto err_hw;

35
target/linux/lantiq/patches-4.14/0040-USB-DWC2-enable-usb-power-gpio.patch
View File

@ -1,35 +0,0 @@
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -42,6 +42,7 @@
#include <linux/dma-mapping.h>
#include <linux/of_device.h>
#include <linux/mutex.h>
+#include <linux/of_gpio.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
#include <linux/platform_data/s3c-hsotg.h>
@@ -544,6 +545,7 @@ static int dwc2_driver_probe(struct plat
struct dwc2_hsotg *hsotg;
struct resource *res;
int retval;
+ int gpio_count;
match = of_match_device(dwc2_of_match_table, &dev->dev);
if (match && match->data) {
@@ -562,6 +564,16 @@ static int dwc2_driver_probe(struct plat
defparams.dma_desc_fs_enable = 0;
}
+ gpio_count = of_gpio_count(dev->dev.of_node);
+ while (gpio_count > 0) {
+ enum of_gpio_flags flags;
+ int gpio = of_get_gpio_flags(dev->dev.of_node, --gpio_count, &flags);
+ if (gpio_request(gpio, "usb"))
+ continue;
+ dev_info(&dev->dev, "requested GPIO %d\n", gpio);
+ gpio_direction_output(gpio, (flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1));
+ }
+
hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
if (!hsotg)
return -ENOMEM;

11
target/linux/lantiq/patches-4.14/0044-pinctrl-xway-fix-copy-paste-error-in-xrx200_grps.patch
View File

@ -1,11 +0,0 @@
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -1028,7 +1028,7 @@ static const struct ltq_pin_group xrx200
GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5),
GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6),
GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_rx),
- GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_tx),
+ GRP_MUX("usif uart_tx", USIF, xrx200_pins_usif_uart_tx),
GRP_MUX("usif uart_rts", USIF, xrx200_pins_usif_uart_rts),
GRP_MUX("usif uart_cts", USIF, xrx200_pins_usif_uart_cts),
GRP_MUX("usif uart_dtr", USIF, xrx200_pins_usif_uart_dtr),

23
target/linux/lantiq/patches-4.14/0047-poweroff.patch
View File

@ -1,23 +0,0 @@
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -301,12 +301,6 @@ static void ltq_machine_halt(void)
unreachable();
}
-static void ltq_machine_power_off(void)
-{
- local_irq_disable();
- unreachable();
-}
-
static void ltq_usb_init(void)
{
/* Power for USB cores 1 & 2 */
@@ -379,7 +373,6 @@ static int __init mips_reboot_setup(void
_machine_restart = ltq_machine_restart;
_machine_halt = ltq_machine_halt;
- pm_power_off = ltq_machine_power_off;
return 0;
}

87
target/linux/lantiq/patches-4.14/0050-MIPS-Lantiq-Fix-cascaded-IRQ-setup.patch
View File

@ -1,87 +0,0 @@
From: Felix Fietkau <nbd@nbd.name>
Date: Thu, 19 Jan 2017 12:14:44 +0100
Subject: [PATCH] MIPS: Lantiq: Fix cascaded IRQ setup
With the IRQ stack changes integrated, the XRX200 devices started
emitting a constant stream of kernel messages like this:
[ 565.415310] Spurious IRQ: CAUSE=0x1100c300
This appears to be caused by IP0 firing for some reason without being
handled. Fix this by setting up IP2-6 as a proper chained IRQ handler and
calling do_IRQ for all MIPS CPU interrupts.
Cc: john@phrozen.org
Cc: stable@vger.kernel.org
Signed-off-by: Felix Fietkau <nbd@nbd.name>
---
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -271,6 +271,11 @@ static void ltq_hw5_irqdispatch(void)
DEFINE_HWx_IRQDISPATCH(5)
#endif
+static void ltq_hw_irq_handler(struct irq_desc *desc)
+{
+ ltq_hw_irqdispatch(irq_desc_get_irq(desc) - 2);
+}
+
#ifdef CONFIG_MIPS_MT_SMP
void __init arch_init_ipiirq(int irq, struct irqaction *action)
{
@@ -315,23 +320,19 @@ static struct irqaction irq_call = {
asmlinkage void plat_irq_dispatch(void)
{
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
- unsigned int i;
+ int irq;
- if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
- do_IRQ(MIPS_CPU_TIMER_IRQ);
- goto out;
- } else {
- for (i = 0; i < MAX_IM; i++) {
- if (pending & (CAUSEF_IP2 << i)) {
- ltq_hw_irqdispatch(i);
- goto out;
- }
- }
+ if (!pending) {
+ spurious_interrupt();
+ return;
}
- pr_alert("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
-out:
- return;
+ pending >>= CAUSEB_IP;
+ while (pending) {
+ irq = fls(pending) - 1;
+ do_IRQ(MIPS_CPU_IRQ_BASE + irq);
+ pending &= ~BIT(irq);
+ }
}
static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
@@ -356,11 +357,6 @@ static const struct irq_domain_ops irq_d
.map = icu_map,
};
-static struct irqaction cascade = {
- .handler = no_action,
- .name = "cascade",
-};
-
int __init icu_of_init(struct device_node *node, struct device_node *parent)
{
struct device_node *eiu_node;
@@ -392,7 +388,7 @@ int __init icu_of_init(struct device_nod
mips_cpu_irq_init();
for (i = 0; i < MAX_IM; i++)
- setup_irq(i + 2, &cascade);
+ irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
if (cpu_has_vint) {
pr_info("Setting up vectored interrupts\n");

78
target/linux/lantiq/patches-4.14/0050-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch Normal file
View File

@ -0,0 +1,78 @@
From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Fri, 6 Jan 2017 17:55:24 +0100
Subject: [PATCH 2/2] usb: dwc2: add support for other Lantiq SoCs
The size of the internal RAM of the DesignWare USB controller changed
between the different Lantiq SoCs. We have the following sizes:
Amazon + Danube: 8 KByte
Amazon SE + arx100: 2 KByte
xrx200 + xrx300: 2.5 KByte
For Danube SoC we do not provide the params and let the driver decide
to use sane defaults, for the Amazon SE and arx100 we use small fifos
and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo.
The auto detection of max_transfer_size and max_packet_count should
work, so remove it.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++-------
1 file changed, 39 insertions(+), 7 deletions(-)
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -83,7 +83,14 @@ static void dwc2_set_rk_params(struct dw
GAHBCFG_HBSTLEN_SHIFT;
}
-static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
+static void dwc2_set_ltq_danube_params(struct dwc2_hsotg *hsotg)
+{
+ struct dwc2_core_params *p = &hsotg->params;
+
+ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+}
+
+static void dwc2_set_ltq_ase_params(struct dwc2_hsotg *hsotg)
{
struct dwc2_core_params *p = &hsotg->params;
@@ -91,12 +98,20 @@ static void dwc2_set_ltq_params(struct d
p->host_rx_fifo_size = 288;
p->host_nperio_tx_fifo_size = 128;
p->host_perio_tx_fifo_size = 96;
- p->max_transfer_size = 65535;
- p->max_packet_count = 511;
p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
GAHBCFG_HBSTLEN_SHIFT;
}
+static void dwc2_set_ltq_xrx200_params(struct dwc2_hsotg *hsotg)
+{
+ struct dwc2_core_params *p = &hsotg->params;
+
+ p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
+ p->host_rx_fifo_size = 288;
+ p->host_nperio_tx_fifo_size = 128;
+ p->host_perio_tx_fifo_size = 136;
+}
+
static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
{
struct dwc2_core_params *p = &hsotg->params;
@@ -140,8 +155,11 @@ const struct of_device_id dwc2_of_match_
{ .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
{ .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params },
{ .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
- { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
- { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
+ { .compatible = "lantiq,danube-usb", .data = &dwc2_set_ltq_danube_params },
+ { .compatible = "lantiq,ase-usb", .data = &dwc2_set_ltq_ase_params },
+ { .compatible = "lantiq,arx100-usb", .data = &dwc2_set_ltq_ase_params },
+ { .compatible = "lantiq,xrx200-usb", .data = &dwc2_set_ltq_xrx200_params },
+ { .compatible = "lantiq,xrx300-usb", .data = &dwc2_set_ltq_xrx200_params },
{ .compatible = "snps,dwc2" },
{ .compatible = "samsung,s3c6400-hsotg" },
{ .compatible = "amlogic,meson8-usb",

49
target/linux/lantiq/patches-4.14/0051-MIPS-lantiq-improve-USB-initialization.patch Normal file
View File

@ -0,0 +1,49 @@
From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Fri, 6 Jan 2017 17:40:12 +0100
Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization
This adds code to initialize the USB controller and PHY also on Danube,
Amazon SE and AR10. This code is based on the Vendor driver from
different UGW versions and compared to the hardware documentation.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/mips/lantiq/xway/sysctrl.c | 20 +++++++
2 files changed, 110 insertions(+), 30 deletions(-)
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -246,6 +246,25 @@ static void pmu_disable(struct clk *clk)
pr_warn("deactivating PMU module failed!");
}
+static void usb_set_clock(void)
+{
+ unsigned int val = ltq_cgu_r32(ifccr);
+
+ if (of_machine_is_compatible("lantiq,ar10") ||
+ of_machine_is_compatible("lantiq,grx390")) {
+ val &= ~0x03; /* XTAL divided by 3 */
+ } else if (of_machine_is_compatible("lantiq,ar9") ||
+ of_machine_is_compatible("lantiq,vr9")) {
+ /* TODO: this depends on the XTAL frequency */
+ val |= 0x03; /* XTAL divided by 3 */
+ } else if (of_machine_is_compatible("lantiq,ase")) {
+ val |= 0x20; /* from XTAL */
+ } else if (of_machine_is_compatible("lantiq,danube")) {
+ val |= 0x30; /* 12 MHz, generated from 36 MHz */
+ }
+ ltq_cgu_w32(val, ifccr);
+}
+
/* the pci enable helper */
static int pci_enable(struct clk *clk)
{
@@ -569,4 +588,5 @@ void __init ltq_soc_init(void)
clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
}
+ usb_set_clock();
}

130
target/linux/lantiq/patches-4.14/0061-USB-DWC2-make-the-lantiq-settings-match-vendor-drive.patch
View File

@ -1,130 +0,0 @@
From de2cad82c4d0872066f83ce59462603852b47f03 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Fri, 6 Jan 2017 17:55:24 +0100
Subject: [PATCH 2/2] usb: dwc2: add support for other Lantiq SoCs
The size of the internal RAM of the DesignWare USB controller changed
between the different Lantiq SoCs. We have the following sizes:
Amazon + Danube: 8 KByte
Amazon SE + arx100: 2 KByte
xrx200 + xrx300: 2.5 KByte
For Danube SoC we do not provide the params and let the driver decide
to use sane defaults, for the Amazon SE and arx100 we use small fifos
and for the xrx200 and xrx300 SCs a little bit bigger periodic fifo.
The auto detection of max_transfer_size and max_packet_count should
work, so remove it.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
drivers/usb/dwc2/platform.c | 46 ++++++++++++++++++++++++++++++++++++++-------
1 file changed, 39 insertions(+), 7 deletions(-)
--- a/drivers/usb/dwc2/platform.c
+++ b/drivers/usb/dwc2/platform.c
@@ -151,7 +151,38 @@ static const struct dwc2_core_params par
.hibernation = -1,
};
-static const struct dwc2_core_params params_ltq = {
+static const struct dwc2_core_params params_danube = {
+ .otg_cap = 2, /* non-HNP/non-SRP */
+ .otg_ver = -1,
+ .dma_enable = -1,
+ .dma_desc_enable = -1,
+ .dma_desc_fs_enable = -1,
+ .speed = -1,
+ .enable_dynamic_fifo = -1,
+ .en_multiple_tx_fifo = -1,
+ .host_rx_fifo_size = -1,
+ .host_nperio_tx_fifo_size = -1,
+ .host_perio_tx_fifo_size = -1,
+ .max_transfer_size = -1,
+ .max_packet_count = -1,
+ .host_channels = -1,
+ .phy_type = -1,
+ .phy_utmi_width = -1,
+ .phy_ulpi_ddr = -1,
+ .phy_ulpi_ext_vbus = -1,
+ .i2c_enable = -1,
+ .ulpi_fs_ls = -1,
+ .host_support_fs_ls_low_power = -1,
+ .host_ls_low_power_phy_clk = -1,
+ .ts_dline = -1,
+ .reload_ctl = -1,
+ .ahbcfg = -1,
+ .uframe_sched = -1,
+ .external_id_pin_ctl = -1,
+ .hibernation = -1,
+};
+
+static const struct dwc2_core_params params_ase = {
.otg_cap = 2, /* non-HNP/non-SRP */
.otg_ver = -1,
.dma_enable = -1,
@@ -163,8 +194,8 @@ static const struct dwc2_core_params par
.host_rx_fifo_size = 288, /* 288 DWORDs */
.host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
.host_perio_tx_fifo_size = 96, /* 96 DWORDs */
- .max_transfer_size = 65535,
- .max_packet_count = 511,
+ .max_transfer_size = -1,
+ .max_packet_count = -1,
.host_channels = -1,
.phy_type = -1,
.phy_utmi_width = -1,
@@ -176,8 +207,37 @@ static const struct dwc2_core_params par
.host_ls_low_power_phy_clk = -1,
.ts_dline = -1,
.reload_ctl = -1,
- .ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
- GAHBCFG_HBSTLEN_SHIFT,
+ .ahbcfg = -1,
+ .uframe_sched = -1,
+ .external_id_pin_ctl = -1,
+ .hibernation = -1,
+};
+
+static const struct dwc2_core_params params_xrx200 = {
+ .otg_cap = 2, /* non-HNP/non-SRP */
+ .otg_ver = -1,
+ .dma_enable = -1,
+ .dma_desc_enable = -1,
+ .speed = -1,
+ .enable_dynamic_fifo = -1,
+ .en_multiple_tx_fifo = -1,
+ .host_rx_fifo_size = 288, /* 288 DWORDs */
+ .host_nperio_tx_fifo_size = 128, /* 128 DWORDs */
+ .host_perio_tx_fifo_size = 136, /* 136 DWORDs */
+ .max_transfer_size = -1,
+ .max_packet_count = -1,
+ .host_channels = -1,
+ .phy_type = -1,
+ .phy_utmi_width = -1,
+ .phy_ulpi_ddr = -1,
+ .phy_ulpi_ext_vbus = -1,
+ .i2c_enable = -1,
+ .ulpi_fs_ls = -1,
+ .host_support_fs_ls_low_power = -1,
+ .host_ls_low_power_phy_clk = -1,
+ .ts_dline = -1,
+ .reload_ctl = -1,
+ .ahbcfg = -1,
.uframe_sched = -1,
.external_id_pin_ctl = -1,
.hibernation = -1,
@@ -515,8 +575,11 @@ static const struct of_device_id dwc2_of
{ .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
{ .compatible = "hisilicon,hi6220-usb", .data = &params_hi6220 },
{ .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
- { .compatible = "lantiq,arx100-usb", .data = &params_ltq },
- { .compatible = "lantiq,xrx200-usb", .data = &params_ltq },
+ { .compatible = "lantiq,danube-usb", .data = &params_danube },
+ { .compatible = "lantiq,ase-usb", .data = &params_ase },
+ { .compatible = "lantiq,arx100-usb", .data = &params_ase },
+ { .compatible = "lantiq,xrx200-usb", .data = &params_xrx200 },
+ { .compatible = "lantiq,xrx300-usb", .data = &params_xrx200 },
{ .compatible = "snps,dwc2", .data = NULL },
{ .compatible = "samsung,s3c6400-hsotg", .data = NULL},
{ .compatible = "amlogic,meson8b-usb", .data = &params_amlogic },

202
target/linux/lantiq/patches-4.14/0065-MIPS-lantiq-improve-USB-initialization.patch
View File

@ -1,202 +0,0 @@
From 14909c4e4e836925668e74fc6e0e85ba0283cbf9 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Fri, 6 Jan 2017 17:40:12 +0100
Subject: [PATCH 2/2] MIPS: lantiq: improve USB initialization
This adds code to initialize the USB controller and PHY also on Danube,
Amazon SE and AR10. This code is based on the Vendor driver from
different UGW versions and compared to the hardware documentation.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/mips/lantiq/xway/reset.c | 120 ++++++++++++++++++++++++++++++----------
arch/mips/lantiq/xway/sysctrl.c | 20 +++++++
2 files changed, 110 insertions(+), 30 deletions(-)
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -72,6 +72,8 @@
#define RCU_USBCFG_HDSEL_BIT BIT(11)
#define RCU_USBCFG_HOST_END_BIT BIT(10)
#define RCU_USBCFG_SLV_END_BIT BIT(9)
+#define RCU_USBCFG_SLV_END_BIT_AR9 BIT(17)
+
/* USB reset bits */
#define RCU_USBRESET 0x0010
@@ -85,6 +87,8 @@
#define RCU_CFG1A 0x0038
#define RCU_CFG1B 0x003C
+#define RCU_CFG1_TX_PEE BIT(0)
+#define RCU_CFG1_DIS_THR_SHIFT 15 /* Disconnect Threshold */
/* USB PMU devices */
#define PMU_AHBM BIT(15)
@@ -306,38 +310,91 @@ static void ltq_usb_init(void)
/* Power for USB cores 1 & 2 */
ltq_pmu_enable(PMU_AHBM);
ltq_pmu_enable(PMU_USB0);
- ltq_pmu_enable(PMU_USB1);
- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
- ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
+ if (of_machine_is_compatible("lantiq,ar10") ||
+ of_machine_is_compatible("lantiq,grx390") ||
+ of_machine_is_compatible("lantiq,ar9") ||
+ of_machine_is_compatible("lantiq,vr9"))
+ ltq_pmu_enable(PMU_USB1);
+
+ if (of_machine_is_compatible("lantiq,vr9") ||
+ of_machine_is_compatible("lantiq,ar10")) {
+ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | RCU_CFG1_TX_PEE |
+ 7 << RCU_CFG1_DIS_THR_SHIFT, RCU_CFG1A);
+ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | RCU_CFG1_TX_PEE |
+ 7 << RCU_CFG1_DIS_THR_SHIFT, RCU_CFG1B);
+ }
/* Enable USB PHY power for cores 1 & 2 */
ltq_pmu_enable(PMU_USB0_P);
- ltq_pmu_enable(PMU_USB1_P);
+ if (of_machine_is_compatible("lantiq,ar10") ||
+ of_machine_is_compatible("lantiq,grx390") ||
+ of_machine_is_compatible("lantiq,ar9") ||
+ of_machine_is_compatible("lantiq,vr9"))
+ ltq_pmu_enable(PMU_USB1_P);
+
+ if (of_machine_is_compatible("lantiq,ase") ||
+ of_machine_is_compatible("lantiq,danube")) {
+ /* Configure cores to host mode */
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
+ RCU_USB1CFG);
+
+ /* Select DMA endianness (Host-endian: big-endian) */
+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
+ }
+
+ if (of_machine_is_compatible("lantiq,ar9")) {
+ /* Configure cores to host mode */
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
+ RCU_USB1CFG);
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
+ RCU_USB2CFG);
+
+ /* Select DMA endianness (Host-endian: big-endian) */
+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT_AR9)
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
+ ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT_AR9)
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
+ }
+
+ if (of_machine_is_compatible("lantiq,vr9") ||
+ of_machine_is_compatible("lantiq,ar10")) {
+ /* Configure cores to host mode */
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
+ RCU_USB1CFG);
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
+ RCU_USB2CFG);
+
+ /* Select DMA endianness (Host-endian: big-endian) */
+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
+ ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
+ | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
+ }
+
+ if (of_machine_is_compatible("lantiq,ar9")) {
+ /* Hard reset USB state machines */
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET)
+ | USBRESET_BIT | BIT(28), RCU_USBRESET);
+ udelay(50 * 1000);
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET)
+ & ~(USBRESET_BIT | BIT(28)), RCU_USBRESET);
+ } else {
+ /* Hard reset USB state machines */
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
+ udelay(50 * 1000);
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
+ }
- /* Configure cores to host mode */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
- RCU_USB1CFG);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
- RCU_USB2CFG);
-
- /* Select DMA endianness (Host-endian: big-endian) */
- ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
- | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
- ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
- | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
-
- /* Hard reset USB state machines */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
- udelay(50 * 1000);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
-
- /* Soft reset USB state machines */
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
- | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
- udelay(50 * 1000);
- ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
- & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
+ if (of_machine_is_compatible("lantiq,vr9")) {
+ /* Soft reset USB state machines */
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
+ | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
+ udelay(50 * 1000);
+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
+ & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
+ }
}
static int __init mips_reboot_setup(void)
@@ -363,8 +420,11 @@ static int __init mips_reboot_setup(void
if (!ltq_rcu_membase)
panic("Failed to remap core memory");
- if (of_machine_is_compatible("lantiq,ar9") ||
- of_machine_is_compatible("lantiq,vr9"))
+ if (of_machine_is_compatible("lantiq,danube") ||
+ of_machine_is_compatible("lantiq,ase") ||
+ of_machine_is_compatible("lantiq,ar9") ||
+ of_machine_is_compatible("lantiq,vr9") ||
+ of_machine_is_compatible("lantiq,ar10"))
ltq_usb_init();
if (of_machine_is_compatible("lantiq,vr9"))
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -254,6 +254,25 @@ static void pmu_disable(struct clk *clk)
pr_warn("deactivating PMU module failed!");
}
+static void usb_set_clock(void)
+{
+ unsigned int val = ltq_cgu_r32(ifccr);
+
+ if (of_machine_is_compatible("lantiq,ar10") ||
+ of_machine_is_compatible("lantiq,grx390")) {
+ val &= ~0x03; /* XTAL divided by 3 */
+ } else if (of_machine_is_compatible("lantiq,ar9") ||
+ of_machine_is_compatible("lantiq,vr9")) {
+ /* TODO: this depends on the XTAL frequency */
+ val |= 0x03; /* XTAL divided by 3 */
+ } else if (of_machine_is_compatible("lantiq,ase")) {
+ val |= 0x20; /* from XTAL */
+ } else if (of_machine_is_compatible("lantiq,danube")) {
+ val |= 0x30; /* 12 MHz, generated from 36 MHz */
+ }
+ ltq_cgu_w32(val, ifccr);
+}
+
/* the pci enable helper */
static int pci_enable(struct clk *clk)
{
@@ -608,4 +627,5 @@ void __init ltq_soc_init(void)
if (of_machine_is_compatible("lantiq,vr9"))
xbar_fpi_burst_disable();
+ usb_set_clock();
}

1078
target/linux/lantiq/patches-4.14/0090-spi-lantiq-ssc-add-support-for-Lantiq-SSC-SPI-contro.patch
View File

File diff suppressed because it is too large Load Diff

28
target/linux/lantiq/patches-4.14/0091-spi-lantiq-ssc-fix-platform_no_drv_owner.cocci-warni.patch
View File

@ -1,28 +0,0 @@
From ba6e1e39969fa5435127a632757e2906caca7730 Mon Sep 17 00:00:00 2001
From: kbuild test robot <fengguang.wu@intel.com>
Date: Mon, 20 Feb 2017 01:33:10 +0800
Subject: spi: lantiq-ssc: fix platform_no_drv_owner.cocci warnings
drivers/spi/spi-lantiq-ssc.c:973:3-8: No need to set .owner here. The core will do it.
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
drivers/spi/spi-lantiq-ssc.c | 1 -
1 file changed, 1 deletion(-)
--- a/drivers/spi/spi-lantiq-ssc.c
+++ b/drivers/spi/spi-lantiq-ssc.c
@@ -970,7 +970,6 @@ static struct platform_driver lantiq_ssc
.remove = lantiq_ssc_remove,
.driver = {
.name = "spi-lantiq-ssc",
- .owner = THIS_MODULE,
.of_match_table = lantiq_ssc_match,
},
};

723
target/linux/lantiq/patches-4.14/0092-spi-lantiq-ssc-add-LTQ_-prefix-to-defines.patch
View File

@ -1,723 +0,0 @@
From 1aa83e0a2821cd7f4e8f3ddb367859f52e468bf1 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Mon, 27 Feb 2017 23:21:25 +0100
Subject: spi: lantiq-ssc: add LTQ_ prefix to defines
The blackfin architecture has a SPI_STAT define which conflicts with
the define from the spi-lantiq-ssc driver in compile test mode. Fix
this by adding a prefix in front of every define.
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
drivers/spi/spi-lantiq-ssc.c | 437 ++++++++++++++++++++++---------------------
1 file changed, 222 insertions(+), 215 deletions(-)
--- a/drivers/spi/spi-lantiq-ssc.c
+++ b/drivers/spi/spi-lantiq-ssc.c
@@ -26,136 +26,140 @@
#include <lantiq_soc.h>
#endif
-#define SPI_RX_IRQ_NAME "spi_rx"
-#define SPI_TX_IRQ_NAME "spi_tx"
-#define SPI_ERR_IRQ_NAME "spi_err"
-#define SPI_FRM_IRQ_NAME "spi_frm"
-
-#define SPI_CLC 0x00
-#define SPI_PISEL 0x04
-#define SPI_ID 0x08
-#define SPI_CON 0x10
-#define SPI_STAT 0x14
-#define SPI_WHBSTATE 0x18
-#define SPI_TB 0x20
-#define SPI_RB 0x24
-#define SPI_RXFCON 0x30
-#define SPI_TXFCON 0x34
-#define SPI_FSTAT 0x38
-#define SPI_BRT 0x40
-#define SPI_BRSTAT 0x44
-#define SPI_SFCON 0x60
-#define SPI_SFSTAT 0x64
-#define SPI_GPOCON 0x70
-#define SPI_GPOSTAT 0x74
-#define SPI_FPGO 0x78
-#define SPI_RXREQ 0x80
-#define SPI_RXCNT 0x84
-#define SPI_DMACON 0xec
-#define SPI_IRNEN 0xf4
-#define SPI_IRNICR 0xf8
-#define SPI_IRNCR 0xfc
-
-#define SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
-#define SPI_CLC_SMC_M (0xFF << SPI_CLC_SMC_S)
-#define SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */
-#define SPI_CLC_RMC_M (0xFF << SPI_CLC_RMC_S)
-#define SPI_CLC_DISS BIT(1) /* Disable status bit */
-#define SPI_CLC_DISR BIT(0) /* Disable request bit */
-
-#define SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */
-#define SPI_ID_TXFS_M (0x3F << SPI_ID_TXFS_S)
-#define SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */
-#define SPI_ID_RXFS_M (0x3F << SPI_ID_RXFS_S)
-#define SPI_ID_MOD_S 8 /* Module ID */
-#define SPI_ID_MOD_M (0xff << SPI_ID_MOD_S)
-#define SPI_ID_CFG_S 5 /* DMA interface support */
-#define SPI_ID_CFG_M (1 << SPI_ID_CFG_S)
-#define SPI_ID_REV_M 0x1F /* Hardware revision number */
-
-#define SPI_CON_BM_S 16 /* Data width selection */
-#define SPI_CON_BM_M (0x1F << SPI_CON_BM_S)
-#define SPI_CON_EM BIT(24) /* Echo mode */
-#define SPI_CON_IDLE BIT(23) /* Idle bit value */
-#define SPI_CON_ENBV BIT(22) /* Enable byte valid control */
-#define SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
-#define SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
-#define SPI_CON_AEN BIT(10) /* Abort error enable */
-#define SPI_CON_REN BIT(9) /* Receive overflow error enable */
-#define SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
-#define SPI_CON_LB BIT(7) /* Loopback control */
-#define SPI_CON_PO BIT(6) /* Clock polarity control */
-#define SPI_CON_PH BIT(5) /* Clock phase control */
-#define SPI_CON_HB BIT(4) /* Heading control */
-#define SPI_CON_RXOFF BIT(1) /* Switch receiver off */
-#define SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
-
-#define SPI_STAT_RXBV_S 28
-#define SPI_STAT_RXBV_M (0x7 << SPI_STAT_RXBV_S)
-#define SPI_STAT_BSY BIT(13) /* Busy flag */
-#define SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
-#define SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
-#define SPI_STAT_AE BIT(10) /* Abort error flag */
-#define SPI_STAT_RE BIT(9) /* Receive error flag */
-#define SPI_STAT_TE BIT(8) /* Transmit error flag */
-#define SPI_STAT_ME BIT(7) /* Mode error flag */
-#define SPI_STAT_MS BIT(1) /* Master/slave select bit */
-#define SPI_STAT_EN BIT(0) /* Enable bit */
-#define SPI_STAT_ERRORS (SPI_STAT_ME | SPI_STAT_TE | SPI_STAT_RE | \
- SPI_STAT_AE | SPI_STAT_TUE | SPI_STAT_RUE)
-
-#define SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
-#define SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
-#define SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
-#define SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
-#define SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */
-#define SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
-#define SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
-#define SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
-#define SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
-#define SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
-#define SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
-#define SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
-#define SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
-#define SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
-#define SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
-#define SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
-#define SPI_WHBSTATE_CLR_ERRORS (SPI_WHBSTATE_CLRRUE | SPI_WHBSTATE_CLRME | \
- SPI_WHBSTATE_CLRTE | SPI_WHBSTATE_CLRRE | \
- SPI_WHBSTATE_CLRAE | SPI_WHBSTATE_CLRTUE)
-
-#define SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */
-#define SPI_RXFCON_RXFITL_M (0x3F << SPI_RXFCON_RXFITL_S)
-#define SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
-#define SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
-
-#define SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */
-#define SPI_TXFCON_TXFITL_M (0x3F << SPI_TXFCON_TXFITL_S)
-#define SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
-#define SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
-
-#define SPI_FSTAT_RXFFL_S 0
-#define SPI_FSTAT_RXFFL_M (0x3f << SPI_FSTAT_RXFFL_S)
-#define SPI_FSTAT_TXFFL_S 8
-#define SPI_FSTAT_TXFFL_M (0x3f << SPI_FSTAT_TXFFL_S)
-
-#define SPI_GPOCON_ISCSBN_S 8
-#define SPI_GPOCON_INVOUTN_S 0
-
-#define SPI_FGPO_SETOUTN_S 8
-#define SPI_FGPO_CLROUTN_S 0
-
-#define SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */
-#define SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
-
-#define SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */
-#define SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
-#define SPI_IRNEN_E BIT(2) /* Error end interrupt request */
-#define SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */
-#define SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */
-#define SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */
-#define SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */
-#define SPI_IRNEN_ALL 0x1F
+#define LTQ_SPI_RX_IRQ_NAME "spi_rx"
+#define LTQ_SPI_TX_IRQ_NAME "spi_tx"
+#define LTQ_SPI_ERR_IRQ_NAME "spi_err"
+#define LTQ_SPI_FRM_IRQ_NAME "spi_frm"
+
+#define LTQ_SPI_CLC 0x00
+#define LTQ_SPI_PISEL 0x04
+#define LTQ_SPI_ID 0x08
+#define LTQ_SPI_CON 0x10
+#define LTQ_SPI_STAT 0x14
+#define LTQ_SPI_WHBSTATE 0x18
+#define LTQ_SPI_TB 0x20
+#define LTQ_SPI_RB 0x24
+#define LTQ_SPI_RXFCON 0x30
+#define LTQ_SPI_TXFCON 0x34
+#define LTQ_SPI_FSTAT 0x38
+#define LTQ_SPI_BRT 0x40
+#define LTQ_SPI_BRSTAT 0x44
+#define LTQ_SPI_SFCON 0x60
+#define LTQ_SPI_SFSTAT 0x64
+#define LTQ_SPI_GPOCON 0x70
+#define LTQ_SPI_GPOSTAT 0x74
+#define LTQ_SPI_FPGO 0x78
+#define LTQ_SPI_RXREQ 0x80
+#define LTQ_SPI_RXCNT 0x84
+#define LTQ_SPI_DMACON 0xec
+#define LTQ_SPI_IRNEN 0xf4
+#define LTQ_SPI_IRNICR 0xf8
+#define LTQ_SPI_IRNCR 0xfc
+
+#define LTQ_SPI_CLC_SMC_S 16 /* Clock divider for sleep mode */
+#define LTQ_SPI_CLC_SMC_M (0xFF << LTQ_SPI_CLC_SMC_S)
+#define LTQ_SPI_CLC_RMC_S 8 /* Clock divider for normal run mode */
+#define LTQ_SPI_CLC_RMC_M (0xFF << LTQ_SPI_CLC_RMC_S)
+#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */
+#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */
+
+#define LTQ_SPI_ID_TXFS_S 24 /* Implemented TX FIFO size */
+#define LTQ_SPI_ID_TXFS_M (0x3F << LTQ_SPI_ID_TXFS_S)
+#define LTQ_SPI_ID_RXFS_S 16 /* Implemented RX FIFO size */
+#define LTQ_SPI_ID_RXFS_M (0x3F << LTQ_SPI_ID_RXFS_S)
+#define LTQ_SPI_ID_MOD_S 8 /* Module ID */
+#define LTQ_SPI_ID_MOD_M (0xff << LTQ_SPI_ID_MOD_S)
+#define LTQ_SPI_ID_CFG_S 5 /* DMA interface support */
+#define LTQ_SPI_ID_CFG_M (1 << LTQ_SPI_ID_CFG_S)
+#define LTQ_SPI_ID_REV_M 0x1F /* Hardware revision number */
+
+#define LTQ_SPI_CON_BM_S 16 /* Data width selection */
+#define LTQ_SPI_CON_BM_M (0x1F << LTQ_SPI_CON_BM_S)
+#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */
+#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */
+#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */
+#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */
+#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */
+#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */
+#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */
+#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */
+#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */
+#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */
+#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */
+#define LTQ_SPI_CON_HB BIT(4) /* Heading control */
+#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */
+#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */
+
+#define LTQ_SPI_STAT_RXBV_S 28
+#define LTQ_SPI_STAT_RXBV_M (0x7 << LTQ_SPI_STAT_RXBV_S)
+#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */
+#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */
+#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */
+#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */
+#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */
+#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */
+#define LTQ_SPI_STAT_ME BIT(7) /* Mode error flag */
+#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */
+#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */
+#define LTQ_SPI_STAT_ERRORS (LTQ_SPI_STAT_ME | LTQ_SPI_STAT_TE | \
+ LTQ_SPI_STAT_RE | LTQ_SPI_STAT_AE | \
+ LTQ_SPI_STAT_TUE | LTQ_SPI_STAT_RUE)
+
+#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */
+#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */
+#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */
+#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */
+#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */
+#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */
+#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */
+#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */
+#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */
+#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */
+#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */
+#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */
+#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */
+#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */
+#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */
+#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */
+#define LTQ_SPI_WHBSTATE_CLR_ERRORS (LTQ_SPI_WHBSTATE_CLRRUE | \
+ LTQ_SPI_WHBSTATE_CLRME | \
+ LTQ_SPI_WHBSTATE_CLRTE | \
+ LTQ_SPI_WHBSTATE_CLRRE | \
+ LTQ_SPI_WHBSTATE_CLRAE | \
+ LTQ_SPI_WHBSTATE_CLRTUE)
+
+#define LTQ_SPI_RXFCON_RXFITL_S 8 /* FIFO interrupt trigger level */
+#define LTQ_SPI_RXFCON_RXFITL_M (0x3F << LTQ_SPI_RXFCON_RXFITL_S)
+#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */
+#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */
+
+#define LTQ_SPI_TXFCON_TXFITL_S 8 /* FIFO interrupt trigger level */
+#define LTQ_SPI_TXFCON_TXFITL_M (0x3F << LTQ_SPI_TXFCON_TXFITL_S)
+#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */
+#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */
+
+#define LTQ_SPI_FSTAT_RXFFL_S 0
+#define LTQ_SPI_FSTAT_RXFFL_M (0x3f << LTQ_SPI_FSTAT_RXFFL_S)
+#define LTQ_SPI_FSTAT_TXFFL_S 8
+#define LTQ_SPI_FSTAT_TXFFL_M (0x3f << LTQ_SPI_FSTAT_TXFFL_S)
+
+#define LTQ_SPI_GPOCON_ISCSBN_S 8
+#define LTQ_SPI_GPOCON_INVOUTN_S 0
+
+#define LTQ_SPI_FGPO_SETOUTN_S 8
+#define LTQ_SPI_FGPO_CLROUTN_S 0
+
+#define LTQ_SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */
+#define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */
+
+#define LTQ_SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */
+#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */
+#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */
+#define LTQ_SPI_IRNEN_T_XWAY BIT(1) /* Transmit end interrupt request */
+#define LTQ_SPI_IRNEN_R_XWAY BIT(0) /* Receive end interrupt request */
+#define LTQ_SPI_IRNEN_R_XRX BIT(1) /* Transmit end interrupt request */
+#define LTQ_SPI_IRNEN_T_XRX BIT(0) /* Receive end interrupt request */
+#define LTQ_SPI_IRNEN_ALL 0x1F
struct lantiq_ssc_hwcfg {
unsigned int irnen_r;
@@ -208,16 +212,16 @@ static void lantiq_ssc_maskl(const struc
static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
{
- u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT);
+ u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
- return (fstat & SPI_FSTAT_TXFFL_M) >> SPI_FSTAT_TXFFL_S;
+ return (fstat & LTQ_SPI_FSTAT_TXFFL_M) >> LTQ_SPI_FSTAT_TXFFL_S;
}
static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
{
- u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT);
+ u32 fstat = lantiq_ssc_readl(spi, LTQ_SPI_FSTAT);
- return fstat & SPI_FSTAT_RXFFL_M;
+ return fstat & LTQ_SPI_FSTAT_RXFFL_M;
}
static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
@@ -227,38 +231,38 @@ static unsigned int tx_fifo_free(const s
static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)
{
- u32 val = spi->rx_fifo_size << SPI_RXFCON_RXFITL_S;
+ u32 val = spi->rx_fifo_size << LTQ_SPI_RXFCON_RXFITL_S;
- val |= SPI_RXFCON_RXFEN | SPI_RXFCON_RXFLU;
- lantiq_ssc_writel(spi, val, SPI_RXFCON);
+ val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
+ lantiq_ssc_writel(spi, val, LTQ_SPI_RXFCON);
}
static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)
{
- u32 val = 1 << SPI_TXFCON_TXFITL_S;
+ u32 val = 1 << LTQ_SPI_TXFCON_TXFITL_S;
- val |= SPI_TXFCON_TXFEN | SPI_TXFCON_TXFLU;
- lantiq_ssc_writel(spi, val, SPI_TXFCON);
+ val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
+ lantiq_ssc_writel(spi, val, LTQ_SPI_TXFCON);
}
static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)
{
- lantiq_ssc_maskl(spi, 0, SPI_RXFCON_RXFLU, SPI_RXFCON);
+ lantiq_ssc_maskl(spi, 0, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON);
}
static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)
{
- lantiq_ssc_maskl(spi, 0, SPI_TXFCON_TXFLU, SPI_TXFCON);
+ lantiq_ssc_maskl(spi, 0, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON);
}
static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)
{
- lantiq_ssc_writel(spi, SPI_WHBSTATE_CLREN, SPI_WHBSTATE);
+ lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE);
}
static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)
{
- lantiq_ssc_writel(spi, SPI_WHBSTATE_SETEN, SPI_WHBSTATE);
+ lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE);
}
static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,
@@ -287,7 +291,7 @@ static void hw_setup_speed_hz(const stru
dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",
spi_clk, max_speed_hz, brt);
- lantiq_ssc_writel(spi, brt, SPI_BRT);
+ lantiq_ssc_writel(spi, brt, LTQ_SPI_BRT);
}
static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,
@@ -296,9 +300,9 @@ static void hw_setup_bits_per_word(const
u32 bm;
/* CON.BM value = bits_per_word - 1 */
- bm = (bits_per_word - 1) << SPI_CON_BM_S;
+ bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_S;
- lantiq_ssc_maskl(spi, SPI_CON_BM_M, bm, SPI_CON);
+ lantiq_ssc_maskl(spi, LTQ_SPI_CON_BM_M, bm, LTQ_SPI_CON);
}
static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,
@@ -315,28 +319,28 @@ static void hw_setup_clock_mode(const st
* 3 1 1 1 0
*/
if (mode & SPI_CPHA)
- con_clr |= SPI_CON_PH;
+ con_clr |= LTQ_SPI_CON_PH;
else
- con_set |= SPI_CON_PH;
+ con_set |= LTQ_SPI_CON_PH;
if (mode & SPI_CPOL)
- con_set |= SPI_CON_PO | SPI_CON_IDLE;
+ con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
else
- con_clr |= SPI_CON_PO | SPI_CON_IDLE;
+ con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
/* Set heading control */
if (mode & SPI_LSB_FIRST)
- con_clr |= SPI_CON_HB;
+ con_clr |= LTQ_SPI_CON_HB;
else
- con_set |= SPI_CON_HB;
+ con_set |= LTQ_SPI_CON_HB;
/* Set loopback mode */
if (mode & SPI_LOOP)
- con_set |= SPI_CON_LB;
+ con_set |= LTQ_SPI_CON_LB;
else
- con_clr |= SPI_CON_LB;
+ con_clr |= LTQ_SPI_CON_LB;
- lantiq_ssc_maskl(spi, con_clr, con_set, SPI_CON);
+ lantiq_ssc_maskl(spi, con_clr, con_set, LTQ_SPI_CON);
}
static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
@@ -347,37 +351,39 @@ static void lantiq_ssc_hw_init(const str
* Set clock divider for run mode to 1 to
* run at same frequency as FPI bus
*/
- lantiq_ssc_writel(spi, 1 << SPI_CLC_RMC_S, SPI_CLC);
+ lantiq_ssc_writel(spi, 1 << LTQ_SPI_CLC_RMC_S, LTQ_SPI_CLC);
/* Put controller into config mode */
hw_enter_config_mode(spi);
/* Clear error flags */
- lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE);
+ lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
/* Enable error checking, disable TX/RX */
- lantiq_ssc_writel(spi, SPI_CON_RUEN | SPI_CON_AEN | SPI_CON_TEN |
- SPI_CON_REN | SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON);
+ lantiq_ssc_writel(spi, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
+ LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF |
+ LTQ_SPI_CON_RXOFF, LTQ_SPI_CON);
/* Setup default SPI mode */
hw_setup_bits_per_word(spi, spi->bits_per_word);
hw_setup_clock_mode(spi, SPI_MODE_0);
/* Enable master mode and clear error flags */
- lantiq_ssc_writel(spi, SPI_WHBSTATE_SETMS | SPI_WHBSTATE_CLR_ERRORS,
- SPI_WHBSTATE);
+ lantiq_ssc_writel(spi, LTQ_SPI_WHBSTATE_SETMS |
+ LTQ_SPI_WHBSTATE_CLR_ERRORS,
+ LTQ_SPI_WHBSTATE);
/* Reset GPIO/CS registers */
- lantiq_ssc_writel(spi, 0, SPI_GPOCON);
- lantiq_ssc_writel(spi, 0xFF00, SPI_FPGO);
+ lantiq_ssc_writel(spi, 0, LTQ_SPI_GPOCON);
+ lantiq_ssc_writel(spi, 0xFF00, LTQ_SPI_FPGO);
/* Enable and flush FIFOs */
rx_fifo_reset(spi);
tx_fifo_reset(spi);
/* Enable interrupts */
- lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | SPI_IRNEN_E,
- SPI_IRNEN);
+ lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r |
+ LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN);
}
static int lantiq_ssc_setup(struct spi_device *spidev)
@@ -400,13 +406,13 @@ static int lantiq_ssc_setup(struct spi_d
}
/* set GPO pin to CS mode */
- gpocon = 1 << ((cs - spi->base_cs) + SPI_GPOCON_ISCSBN_S);
+ gpocon = 1 << ((cs - spi->base_cs) + LTQ_SPI_GPOCON_ISCSBN_S);
/* invert GPO pin */
if (spidev->mode & SPI_CS_HIGH)
gpocon |= 1 << (cs - spi->base_cs);
- lantiq_ssc_maskl(spi, 0, gpocon, SPI_GPOCON);
+ lantiq_ssc_maskl(spi, 0, gpocon, LTQ_SPI_GPOCON);
return 0;
}
@@ -442,18 +448,18 @@ static void hw_setup_transfer(struct lan
}
/* Configure transmitter and receiver */
- con = lantiq_ssc_readl(spi, SPI_CON);
+ con = lantiq_ssc_readl(spi, LTQ_SPI_CON);
if (t->tx_buf)
- con &= ~SPI_CON_TXOFF;
+ con &= ~LTQ_SPI_CON_TXOFF;
else
- con |= SPI_CON_TXOFF;
+ con |= LTQ_SPI_CON_TXOFF;
if (t->rx_buf)
- con &= ~SPI_CON_RXOFF;
+ con &= ~LTQ_SPI_CON_RXOFF;
else
- con |= SPI_CON_RXOFF;
+ con |= LTQ_SPI_CON_RXOFF;
- lantiq_ssc_writel(spi, con, SPI_CON);
+ lantiq_ssc_writel(spi, con, LTQ_SPI_CON);
}
static int lantiq_ssc_unprepare_message(struct spi_master *master,
@@ -464,7 +470,8 @@ static int lantiq_ssc_unprepare_message(
flush_workqueue(spi->wq);
/* Disable transmitter and receiver while idle */
- lantiq_ssc_maskl(spi, 0, SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON);
+ lantiq_ssc_maskl(spi, 0, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF,
+ LTQ_SPI_CON);
return 0;
}
@@ -503,7 +510,7 @@ static void tx_fifo_write(struct lantiq_
break;
}
- lantiq_ssc_writel(spi, data, SPI_TB);
+ lantiq_ssc_writel(spi, data, LTQ_SPI_TB);
tx_free--;
}
}
@@ -517,7 +524,7 @@ static void rx_fifo_read_full_duplex(str
unsigned int rx_fill = rx_fifo_level(spi);
while (rx_fill) {
- data = lantiq_ssc_readl(spi, SPI_RB);
+ data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
switch (spi->bits_per_word) {
case 2 ... 8:
@@ -563,9 +570,9 @@ static void rx_fifo_read_half_duplex(str
*/
while (rx_fill) {
if (spi->rx_todo < 4) {
- rxbv = (lantiq_ssc_readl(spi, SPI_STAT) &
- SPI_STAT_RXBV_M) >> SPI_STAT_RXBV_S;
- data = lantiq_ssc_readl(spi, SPI_RB);
+ rxbv = (lantiq_ssc_readl(spi, LTQ_SPI_STAT) &
+ LTQ_SPI_STAT_RXBV_M) >> LTQ_SPI_STAT_RXBV_S;
+ data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
shift = (rxbv - 1) * 8;
rx8 = spi->rx;
@@ -578,7 +585,7 @@ static void rx_fifo_read_half_duplex(str
spi->rx++;
}
} else {
- data = lantiq_ssc_readl(spi, SPI_RB);
+ data = lantiq_ssc_readl(spi, LTQ_SPI_RB);
rx32 = (u32 *) spi->rx;
*rx32++ = data;
@@ -603,7 +610,7 @@ static void rx_request(struct lantiq_ssc
if (rxreq > rxreq_max)
rxreq = rxreq_max;
- lantiq_ssc_writel(spi, rxreq, SPI_RXREQ);
+ lantiq_ssc_writel(spi, rxreq, LTQ_SPI_RXREQ);
}
static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
@@ -642,26 +649,26 @@ completed:
static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
{
struct lantiq_ssc_spi *spi = data;
- u32 stat = lantiq_ssc_readl(spi, SPI_STAT);
+ u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
- if (!(stat & SPI_STAT_ERRORS))
+ if (!(stat & LTQ_SPI_STAT_ERRORS))
return IRQ_NONE;
- if (stat & SPI_STAT_RUE)
+ if (stat & LTQ_SPI_STAT_RUE)
dev_err(spi->dev, "receive underflow error\n");
- if (stat & SPI_STAT_TUE)
+ if (stat & LTQ_SPI_STAT_TUE)
dev_err(spi->dev, "transmit underflow error\n");
- if (stat & SPI_STAT_AE)
+ if (stat & LTQ_SPI_STAT_AE)
dev_err(spi->dev, "abort error\n");
- if (stat & SPI_STAT_RE)
+ if (stat & LTQ_SPI_STAT_RE)
dev_err(spi->dev, "receive overflow error\n");
- if (stat & SPI_STAT_TE)
+ if (stat & LTQ_SPI_STAT_TE)
dev_err(spi->dev, "transmit overflow error\n");
- if (stat & SPI_STAT_ME)
+ if (stat & LTQ_SPI_STAT_ME)
dev_err(spi->dev, "mode error\n");
/* Clear error flags */
- lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE);
+ lantiq_ssc_maskl(spi, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE);
/* set bad status so it can be retried */
if (spi->master->cur_msg)
@@ -721,9 +728,9 @@ static void lantiq_ssc_bussy_work(struct
end = jiffies + msecs_to_jiffies(timeout);
do {
- u32 stat = lantiq_ssc_readl(spi, SPI_STAT);
+ u32 stat = lantiq_ssc_readl(spi, LTQ_SPI_STAT);
- if (!(stat & SPI_STAT_BSY)) {
+ if (!(stat & LTQ_SPI_STAT_BSY)) {
spi_finalize_current_transfer(spi->master);
return;
}
@@ -755,9 +762,9 @@ static void lantiq_ssc_set_cs(struct spi
if (!!(spidev->mode & SPI_CS_HIGH) == enable)
fgpo = (1 << (cs - spi->base_cs));
else
- fgpo = (1 << (cs - spi->base_cs + SPI_FGPO_SETOUTN_S));
+ fgpo = (1 << (cs - spi->base_cs + LTQ_SPI_FGPO_SETOUTN_S));
- lantiq_ssc_writel(spi, fgpo, SPI_FPGO);
+ lantiq_ssc_writel(spi, fgpo, LTQ_SPI_FPGO);
}
static int lantiq_ssc_transfer_one(struct spi_master *master,
@@ -772,13 +779,13 @@ static int lantiq_ssc_transfer_one(struc
}
static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
- .irnen_r = SPI_IRNEN_R_XWAY,
- .irnen_t = SPI_IRNEN_T_XWAY,
+ .irnen_r = LTQ_SPI_IRNEN_R_XWAY,
+ .irnen_t = LTQ_SPI_IRNEN_T_XWAY,
};
static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
- .irnen_r = SPI_IRNEN_R_XRX,
- .irnen_t = SPI_IRNEN_T_XRX,
+ .irnen_r = LTQ_SPI_IRNEN_R_XRX,
+ .irnen_t = LTQ_SPI_IRNEN_T_XRX,
};
static const struct of_device_id lantiq_ssc_match[] = {
@@ -814,21 +821,21 @@ static int lantiq_ssc_probe(struct platf
return -ENXIO;
}
- rx_irq = platform_get_irq_byname(pdev, SPI_RX_IRQ_NAME);
+ rx_irq = platform_get_irq_byname(pdev, LTQ_SPI_RX_IRQ_NAME);
if (rx_irq < 0) {
- dev_err(dev, "failed to get %s\n", SPI_RX_IRQ_NAME);
+ dev_err(dev, "failed to get %s\n", LTQ_SPI_RX_IRQ_NAME);
return -ENXIO;
}
- tx_irq = platform_get_irq_byname(pdev, SPI_TX_IRQ_NAME);
+ tx_irq = platform_get_irq_byname(pdev, LTQ_SPI_TX_IRQ_NAME);
if (tx_irq < 0) {
- dev_err(dev, "failed to get %s\n", SPI_TX_IRQ_NAME);
+ dev_err(dev, "failed to get %s\n", LTQ_SPI_TX_IRQ_NAME);
return -ENXIO;
}
- err_irq = platform_get_irq_byname(pdev, SPI_ERR_IRQ_NAME);
+ err_irq = platform_get_irq_byname(pdev, LTQ_SPI_ERR_IRQ_NAME);
if (err_irq < 0) {
- dev_err(dev, "failed to get %s\n", SPI_ERR_IRQ_NAME);
+ dev_err(dev, "failed to get %s\n", LTQ_SPI_ERR_IRQ_NAME);
return -ENXIO;
}
@@ -849,17 +856,17 @@ static int lantiq_ssc_probe(struct platf
}
err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt,
- 0, SPI_RX_IRQ_NAME, spi);
+ 0, LTQ_SPI_RX_IRQ_NAME, spi);
if (err)
goto err_master_put;
err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt,
- 0, SPI_TX_IRQ_NAME, spi);
+ 0, LTQ_SPI_TX_IRQ_NAME, spi);
if (err)
goto err_master_put;
err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt,
- 0, SPI_ERR_IRQ_NAME, spi);
+ 0, LTQ_SPI_ERR_IRQ_NAME, spi);
if (err)
goto err_master_put;
@@ -916,11 +923,11 @@ static int lantiq_ssc_probe(struct platf
}
INIT_WORK(&spi->work, lantiq_ssc_bussy_work);
- id = lantiq_ssc_readl(spi, SPI_ID);
- spi->tx_fifo_size = (id & SPI_ID_TXFS_M) >> SPI_ID_TXFS_S;
- spi->rx_fifo_size = (id & SPI_ID_RXFS_M) >> SPI_ID_RXFS_S;
- supports_dma = (id & SPI_ID_CFG_M) >> SPI_ID_CFG_S;
- revision = id & SPI_ID_REV_M;
+ id = lantiq_ssc_readl(spi, LTQ_SPI_ID);
+ spi->tx_fifo_size = (id & LTQ_SPI_ID_TXFS_M) >> LTQ_SPI_ID_TXFS_S;
+ spi->rx_fifo_size = (id & LTQ_SPI_ID_RXFS_M) >> LTQ_SPI_ID_RXFS_S;
+ supports_dma = (id & LTQ_SPI_ID_CFG_M) >> LTQ_SPI_ID_CFG_S;
+ revision = id & LTQ_SPI_ID_REV_M;
lantiq_ssc_hw_init(spi);
@@ -952,8 +959,8 @@ static int lantiq_ssc_remove(struct plat
{
struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);
- lantiq_ssc_writel(spi, 0, SPI_IRNEN);
- lantiq_ssc_writel(spi, 0, SPI_CLC);
+ lantiq_ssc_writel(spi, 0, LTQ_SPI_IRNEN);
+ lantiq_ssc_writel(spi, 0, LTQ_SPI_CLC);
rx_fifo_flush(spi);
tx_fifo_flush(spi);
hw_enter_config_mode(spi);

8
target/linux/lantiq/patches-4.14/0152-lantiq-VPE.patch
View File

@ -1,6 +1,6 @@
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2320,6 +2320,12 @@ config MIPS_VPE_LOADER
@@ -2323,6 +2323,12 @@ config MIPS_VPE_LOADER
Includes a loader for loading an elf relocatable object
onto another VPE and running it.
@ -142,7 +142,7 @@
{
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -31,10 +31,14 @@ EXPORT_SYMBOL_GPL(ebu_lock);
@@ -37,10 +37,14 @@ unsigned long physical_memsize = 0L;
*/
static struct ltq_soc_info soc_info;
@ -159,7 +159,7 @@
{
--- a/arch/mips/include/asm/mipsmtregs.h
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -31,6 +31,9 @@
@@ -32,6 +32,9 @@
#define read_c0_vpeconf1() __read_32bit_c0_register($1, 3)
#define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val)
@ -169,7 +169,7 @@
#define read_c0_tcstatus() __read_32bit_c0_register($2, 1)
#define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val)
@@ -376,6 +379,8 @@ do { \
@@ -377,6 +380,8 @@ do { \
#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val)
#define read_vpe_c0_vpeconf1() mftc0(1, 3)
#define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val)

31
target/linux/lantiq/patches-4.14/0160-owrt-lantiq-multiple-flash.patch
View File

@ -71,9 +71,9 @@
+ };
+ const char **type;
if (of_machine_is_compatible("lantiq,falcon") &&
(ltq_boot_select() != BS_FLASH)) {
@@ -126,75 +162,89 @@ ltq_mtd_probe(struct platform_device *pd
ltq_mtd = devm_kzalloc(&pdev->dev, sizeof(struct ltq_mtd), GFP_KERNEL);
if (!ltq_mtd)
@@ -120,75 +156,89 @@ ltq_mtd_probe(struct platform_device *pd
platform_set_drvdata(pdev, ltq_mtd);
@ -141,17 +141,7 @@
- GFP_KERNEL);
- if (!ltq_mtd->map)
- return -ENOMEM;
+ if (devices_found == 1) {
+ ltq_mtd->cmtd = ltq_mtd->mtd[0];
+ } else if (devices_found > 1) {
+ /*
+ * We detected multiple devices. Concatenate them together.
+ */
+ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev));
+ if (ltq_mtd->cmtd == NULL)
+ err = -ENXIO;
+ }
-
- if (of_find_property(pdev->dev.of_node, "lantiq,noxip", NULL))
- ltq_mtd->map->phys = NO_XIP;
- else
@ -176,8 +166,17 @@
- if (!ltq_mtd->mtd) {
- dev_err(&pdev->dev, "probing failed\n");
- return -ENXIO;
- }
-
+ if (devices_found == 1) {
+ ltq_mtd->cmtd = ltq_mtd->mtd[0];
+ } else if (devices_found > 1) {
+ /*
+ * We detected multiple devices. Concatenate them together.
+ */
+ ltq_mtd->cmtd = mtd_concat_create(ltq_mtd->mtd, devices_found, dev_name(&pdev->dev));
+ if (ltq_mtd->cmtd == NULL)
+ err = -ENXIO;
}
- ltq_mtd->mtd->dev.parent = &pdev->dev;
- mtd_set_of_node(ltq_mtd->mtd, pdev->dev.of_node);
-

152
target/linux/lantiq/patches-4.14/0170-MIPS-lantiq-lock-DMA-register-accesses-for-SMP.patch
View File

@ -1,152 +0,0 @@
From 58078a30038b578c26c532545448fe3746648390 Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Thu, 29 Dec 2016 21:02:57 +0100
Subject: [PATCH] MIPS: lantiq: lock DMA register accesses for SMP
The DMA controller channel and port configuration is changed by
selecting the port or channel in one register and then update the
configuration in other registers. This has to be done in an atomic
operation. Previously only the local interrupts were deactivated which
works for single CPU systems. If the system supports SMP a better
locking is needed, use spinlocks instead.
On more recent SoCs (at least xrx200 and later) there are two memory
regions to change the configuration, there we could use one area for
each CPU and do not have to synchronize between the CPUs and more.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
---
arch/mips/lantiq/xway/dma.c | 38 ++++++++++++++++++++------------------
1 file changed, 20 insertions(+), 18 deletions(-)
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -20,6 +20,7 @@
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/module.h>
+#include <linux/spinlock.h>
#include <linux/clk.h>
#include <linux/err.h>
@@ -59,16 +60,17 @@
ltq_dma_membase + (z))
static void __iomem *ltq_dma_membase;
+static DEFINE_SPINLOCK(ltq_dma_lock);
void
ltq_dma_enable_irq(struct ltq_dma_channel *ch)
{
unsigned long flags;
- local_irq_save(flags);
+ spin_lock_irqsave(&ltq_dma_lock, flags);
ltq_dma_w32(ch->nr, LTQ_DMA_CS);
ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
- local_irq_restore(flags);
+ spin_unlock_irqrestore(&ltq_dma_lock, flags);
}
EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
@@ -77,10 +79,10 @@ ltq_dma_disable_irq(struct ltq_dma_chann
{
unsigned long flags;
- local_irq_save(flags);
+ spin_lock_irqsave(&ltq_dma_lock, flags);
ltq_dma_w32(ch->nr, LTQ_DMA_CS);
ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
- local_irq_restore(flags);
+ spin_unlock_irqrestore(&ltq_dma_lock, flags);
}
EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
@@ -89,10 +91,10 @@ ltq_dma_ack_irq(struct ltq_dma_channel *
{
unsigned long flags;
- local_irq_save(flags);
+ spin_lock_irqsave(&ltq_dma_lock, flags);
ltq_dma_w32(ch->nr, LTQ_DMA_CS);
ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
- local_irq_restore(flags);
+ spin_unlock_irqrestore(&ltq_dma_lock, flags);
}
EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
@@ -101,11 +103,11 @@ ltq_dma_open(struct ltq_dma_channel *ch)
{
unsigned long flag;
- local_irq_save(flag);
+ spin_lock_irqsave(&ltq_dma_lock, flag);
ltq_dma_w32(ch->nr, LTQ_DMA_CS);
ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
- ltq_dma_enable_irq(ch);
- local_irq_restore(flag);
+ ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
+ spin_unlock_irqrestore(&ltq_dma_lock, flag);
}
EXPORT_SYMBOL_GPL(ltq_dma_open);
@@ -114,11 +116,11 @@ ltq_dma_close(struct ltq_dma_channel *ch
{
unsigned long flag;
- local_irq_save(flag);
+ spin_lock_irqsave(&ltq_dma_lock, flag);
ltq_dma_w32(ch->nr, LTQ_DMA_CS);
ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
- ltq_dma_disable_irq(ch);
- local_irq_restore(flag);
+ ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
+ spin_unlock_irqrestore(&ltq_dma_lock, flag);
}
EXPORT_SYMBOL_GPL(ltq_dma_close);
@@ -133,7 +135,7 @@ ltq_dma_alloc(struct ltq_dma_channel *ch
&ch->phys, GFP_ATOMIC);
memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE);
- local_irq_save(flags);
+ spin_lock_irqsave(&ltq_dma_lock, flags);
ltq_dma_w32(ch->nr, LTQ_DMA_CS);
ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
@@ -142,7 +144,7 @@ ltq_dma_alloc(struct ltq_dma_channel *ch
ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
;
- local_irq_restore(flags);
+ spin_unlock_irqrestore(&ltq_dma_lock, flags);
}
void
@@ -152,11 +154,11 @@ ltq_dma_alloc_tx(struct ltq_dma_channel
ltq_dma_alloc(ch);
- local_irq_save(flags);
+ spin_lock_irqsave(&ltq_dma_lock, flags);
ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
- local_irq_restore(flags);
+ spin_unlock_irqrestore(&ltq_dma_lock, flags);
}
EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
@@ -167,11 +169,11 @@ ltq_dma_alloc_rx(struct ltq_dma_channel
ltq_dma_alloc(ch);
- local_irq_save(flags);
+ spin_lock_irqsave(&ltq_dma_lock, flags);
ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
- local_irq_restore(flags);
+ spin_unlock_irqrestore(&ltq_dma_lock, flags);
}
EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);

8
target/linux/lantiq/patches-4.14/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch
View File

@ -1,6 +1,6 @@
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -442,6 +442,20 @@ static void clkdev_add_clkout(void)
@@ -424,6 +424,20 @@ static void clkdev_add_clkout(void)
}
}
@ -21,9 +21,9 @@
/* bring up all register ranges that we need for basic system control */
void __init ltq_soc_init(void)
{
@@ -628,4 +642,6 @@ void __init ltq_soc_init(void)
if (of_machine_is_compatible("lantiq,vr9"))
xbar_fpi_burst_disable();
@@ -589,4 +603,6 @@ void __init ltq_soc_init(void)
clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
}
usb_set_clock();
+
+ set_phy_clock_source(np_cgu);

184
target/linux/lantiq/patches-4.14/0302-xrx200-add-sensors-driver.patch
View File

@ -1,184 +0,0 @@
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -109,6 +109,7 @@ obj-$(CONFIG_SENSORS_LTC4222) += ltc4222
obj-$(CONFIG_SENSORS_LTC4245) += ltc4245.o
obj-$(CONFIG_SENSORS_LTC4260) += ltc4260.o
obj-$(CONFIG_SENSORS_LTC4261) += ltc4261.o
+obj-$(CONFIG_SENSORS_LTQ_CPUTEMP) += ltq-cputemp.o
obj-$(CONFIG_SENSORS_MAX1111) += max1111.o
obj-$(CONFIG_SENSORS_MAX16065) += max16065.o
obj-$(CONFIG_SENSORS_MAX1619) += max1619.o
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -780,6 +780,14 @@ config SENSORS_LTC4261
This driver can also be built as a module. If so, the module will
be called ltc4261.
+config SENSORS_LTQ_CPUTEMP
+ bool "Lantiq CPU temperature sensor"
+ depends on LANTIQ
+ default n
+ help
+ If you say yes here you get support for the temperature
+ sensor inside your CPU.
+
config SENSORS_MAX1111
tristate "Maxim MAX1111 Serial 8-bit ADC chip and compatibles"
depends on SPI_MASTER
--- /dev/null
+++ b/drivers/hwmon/ltq-cputemp.c
@@ -0,0 +1,154 @@
+/* Lantiq CPU Temperatur sensor driver for xrx200
+ *
+ * Copyright (C) 2016 Florian Eckert <feckert@tdt.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/of_device.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+
+#include <lantiq_soc.h>
+
+/* gphy1 configuration register contains cpu temperature */
+#define CGU_GPHY1_CR 0x0040
+#define CGU_TEMP_PD BIT(19)
+
+static void ltq_cputemp_enable(void)
+{
+ ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) | CGU_TEMP_PD, CGU_GPHY1_CR);
+
+ /* wait a short moment to let the SoC get the first temperatur value */
+ mdelay(100);
+}
+
+static void ltq_cputemp_disable(void)
+{
+ ltq_cgu_w32(ltq_cgu_r32(CGU_GPHY1_CR) & ~CGU_TEMP_PD, CGU_GPHY1_CR);
+}
+
+static int ltq_cputemp_read(void)
+{
+ int value;
+
+ /* get the temperature including one decimal place */
+ value = (ltq_cgu_r32(CGU_GPHY1_CR) >> 9) & 0x01FF;
+ value = (value << 2 ) + value;
+
+ /* range -38 to +154 °C, register value zero is -38.0 °C */
+ value -= 380;
+
+ return value;
+}
+
+static ssize_t show_cputemp(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int value;
+
+ value = ltq_cputemp_read();
+ /* scale temp to millidegree */
+ value = value * 100;
+
+ return sprintf(buf, "%d\n", value);
+}
+
+static DEVICE_ATTR(temp1_input, S_IRUGO, show_cputemp, NULL);
+
+static struct attribute *ltq_cputemp_attrs[] = {
+ &dev_attr_temp1_input.attr,
+ NULL
+};
+
+ATTRIBUTE_GROUPS(ltq_cputemp);
+
+static int ltq_cputemp_probe(struct platform_device *pdev)
+{
+ int value = 0;
+ int ret;
+ struct device *hwmon_dev;
+
+ /* available on vr9 v1.2 SoCs only */
+ if (ltq_soc_type() != SOC_TYPE_VR9_2)
+ return -ENODEV;
+
+ hwmon_dev = devm_hwmon_device_register_with_groups(&pdev->dev,
+ "CPU0",
+ NULL,
+ ltq_cputemp_groups);
+
+ if (IS_ERR(hwmon_dev)) {
+ dev_err(&pdev->dev, "Failed to register as hwmon device");
+ ret = PTR_ERR(hwmon_dev);
+ goto error_hwmon;
+ }
+
+ ltq_cputemp_enable();
+ value = ltq_cputemp_read();
+ dev_info(&pdev->dev, "Current CPU die temperature: %d.%d °C", value / 10, value % 10);
+
+ return 0;
+
+error_hwmon:
+ return ret;
+}
+
+static int ltq_cputemp_release(struct platform_device *pdev)
+{
+ hwmon_device_unregister(&pdev->dev);
+ ltq_cputemp_disable();
+ return 0;
+}
+
+const struct of_device_id ltq_cputemp_match[] = {
+ { .compatible = "lantiq,cputemp" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ltq_cputemp_match);
+
+static struct platform_driver ltq_cputemp_driver = {
+ .probe = ltq_cputemp_probe,
+ .remove = ltq_cputemp_release,
+ .driver = {
+ .name = "ltq-cputemp",
+ .owner = THIS_MODULE,
+ .of_match_table = ltq_cputemp_match,
+ },
+};
+
+int __init init_ltq_cputemp(void)
+{
+ int ret;
+
+ ret = platform_driver_register(&ltq_cputemp_driver);
+ return ret;
+}
+
+void clean_ltq_cputemp(void)
+{
+ platform_driver_unregister(&ltq_cputemp_driver);
+ return;
+}
+
+module_init(init_ltq_cputemp);
+module_exit(clean_ltq_cputemp);
+
+MODULE_AUTHOR("Florian Eckert <feckert@tdt.de>");
+
+MODULE_DESCRIPTION("Lantiq Temperature Sensor");
+MODULE_LICENSE("GPL");

11
target/linux/lantiq/xrx200/config-4.14
View File

@ -6,6 +6,7 @@ CONFIG_CPU_MIPSR2_IRQ_EI=y
CONFIG_CPU_MIPSR2_IRQ_VI=y
CONFIG_CPU_RMAP=y
CONFIG_CRC16=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_AEAD=y
CONFIG_CRYPTO_AEAD2=y
CONFIG_CRYPTO_DEFLATE=y
@ -13,6 +14,8 @@ CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_MANAGER=y
CONFIG_CRYPTO_MANAGER2=y
CONFIG_CRYPTO_NULL2=y
CONFIG_EXTRA_FIRMWARE="lantiq/xrx200_phy11g_a14.bin lantiq/xrx200_phy11g_a22.bin lantiq/xrx200_phy22f_a14.bin lantiq/xrx200_phy22f_a22.bin"
CONFIG_EXTRA_FIRMWARE_DIR="firmware"
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_HWMON=y
CONFIG_ICPLUS_PHY=y
@ -57,10 +60,14 @@ CONFIG_PCI=y
CONFIG_PCIE_LANTIQ=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_LANTIQ=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_GPIO=y
CONFIG_POWER_SUPPLY=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RCU_NEED_SEGCBLIST=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTL8306_PHY=y
@ -75,6 +82,7 @@ CONFIG_SYNC_R4K=y
CONFIG_SYS_SUPPORTS_SCHED_SMT=y
CONFIG_SYS_SUPPORTS_SMP=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_UBIFS_FS_LZO=y
@ -83,7 +91,6 @@ CONFIG_USB=y
CONFIG_USB_COMMON=y
# CONFIG_USB_EHCI_HCD is not set
CONFIG_USB_SUPPORT=y
# CONFIG_USB_UHCI_HCD is not set
CONFIG_XPS=y
CONFIG_XRX200_PHY_FW=y
CONFIG_ZLIB_DEFLATE=y

4
target/linux/lantiq/xway/config-4.14
View File

@ -2,6 +2,7 @@ CONFIG_ADM6996_PHY=y
CONFIG_AR8216_PHY=y
CONFIG_BLK_MQ_PCI=y
CONFIG_CRC16=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_FIRMWARE_IN_KERNEL=y
@ -31,6 +32,8 @@ CONFIG_PCI=y
# CONFIG_PCIE_LANTIQ is not set
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_LANTIQ=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_RTL8306_PHY=y
CONFIG_RTL8366S_PHY=y
CONFIG_RTL8367B_PHY=y
@ -43,6 +46,5 @@ CONFIG_USB=y
CONFIG_USB_COMMON=y
# CONFIG_USB_EHCI_HCD is not set
CONFIG_USB_SUPPORT=y
# CONFIG_USB_UHCI_HCD is not set
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

4
target/linux/lantiq/xway_legacy/config-4.14
View File

@ -2,6 +2,7 @@ CONFIG_ADM6996_PHY=y
CONFIG_AR8216_PHY=y
CONFIG_BLK_MQ_PCI=y
CONFIG_CRC16=y
CONFIG_CRYPTO_ACOMP2=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
CONFIG_FIRMWARE_IN_KERNEL=y
@ -24,6 +25,8 @@ CONFIG_PCI=y
# CONFIG_PCIE_LANTIQ is not set
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_LANTIQ=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_RTL8306_PHY=y
CONFIG_RTL8366S_PHY=y
CONFIG_RTL8367B_PHY=y
@ -32,6 +35,5 @@ CONFIG_USB=y
CONFIG_USB_COMMON=y
# CONFIG_USB_EHCI_HCD is not set
CONFIG_USB_SUPPORT=y
# CONFIG_USB_UHCI_HCD is not set
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y