bcm53xx: update PCIe driver

This updates the iProc PCIe driver to the version currently submitted
for kernel 4.5.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

SVN-Revision: 47688

target/linux/bcm53xx/patches-4.1/035-PCI-iproc-Delete-unnecessary-checks-before-phy-calls.patch

@@ -0,0 +1,79 @@
+From 93972d18bbaba6f34e21742400b6e7461edc4837 Mon Sep 17 00:00:00 2001
+From: Markus Elfring <elfring@users.sourceforge.net>
+Date: Sun, 28 Jun 2015 16:42:04 +0200
+Subject: [PATCH] PCI: iproc: Delete unnecessary checks before phy calls
+
+The functions phy_exit() and phy_power_off() test whether their argument is
+NULL and then return immediately.  Thus the test around the calls is not
+needed.
+
+This issue was detected by using the Coccinelle software.
+
+[bhelgaas: also phy_init() and phy_power_on(), as Ray Jui suggested]
+[bhelgaas: also remove tests in iproc_pcie_remove()]
+Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Ray Jui <rjui@broadcom.com>
+---
+ drivers/pci/host/pcie-iproc.c | 34 +++++++++++++---------------------
+ 1 file changed, 13 insertions(+), 21 deletions(-)
+
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -191,19 +191,16 @@ int iproc_pcie_setup(struct iproc_pcie *
+ 	if (!pcie || !pcie->dev || !pcie->base)
+ 		return -EINVAL;
+ 
+-	if (pcie->phy) {
+-		ret = phy_init(pcie->phy);
+-		if (ret) {
+-			dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
+-			return ret;
+-		}
+-
+-		ret = phy_power_on(pcie->phy);
+-		if (ret) {
+-			dev_err(pcie->dev, "unable to power on PCIe PHY\n");
+-			goto err_exit_phy;
+-		}
++	ret = phy_init(pcie->phy);
++	if (ret) {
++		dev_err(pcie->dev, "unable to initialize PCIe PHY\n");
++		return ret;
++	}
+ 
++	ret = phy_power_on(pcie->phy);
++	if (ret) {
++		dev_err(pcie->dev, "unable to power on PCIe PHY\n");
++		goto err_exit_phy;
+ 	}
+ 
+ 	iproc_pcie_reset(pcie);
+@@ -239,12 +236,9 @@ err_rm_root_bus:
+ 	pci_remove_root_bus(bus);
+ 
+ err_power_off_phy:
+-	if (pcie->phy)
+-		phy_power_off(pcie->phy);
++	phy_power_off(pcie->phy);
+ err_exit_phy:
+-	if (pcie->phy)
+-		phy_exit(pcie->phy);
+-
++	phy_exit(pcie->phy);
+ 	return ret;
+ }
+ EXPORT_SYMBOL(iproc_pcie_setup);
+@@ -254,10 +248,8 @@ int iproc_pcie_remove(struct iproc_pcie
+ 	pci_stop_root_bus(pcie->root_bus);
+ 	pci_remove_root_bus(pcie->root_bus);
+ 
+-	if (pcie->phy) {
+-		phy_power_off(pcie->phy);
+-		phy_exit(pcie->phy);
+-	}
++	phy_power_off(pcie->phy);
++	phy_exit(pcie->phy);
+ 
+ 	return 0;
+ }

target/linux/bcm53xx/patches-4.1/037-PCI-iproc-enable-arm64-support-for-iProc-PCIe.patch

@@ -0,0 +1,116 @@
+From db9d6d790968fd6df9faa7fa1f51967e05afd492 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Mon, 27 Jul 2015 15:42:18 -0700
+Subject: [PATCH 37/40] PCI: iproc: enable arm64 support for iProc PCIe
+
+PCI: iproc: Add arm64 support
+
+Add arm64 support to the iProc PCIe driver.
+
+Note that on arm32, bus->sysdata points to the arm32-specific
+pci_sys_data struct, and pci_sys_data.private_data contains the
+iproc_pcie pointer. For arm64, there's nothing corresponding to
+pci_sys_data, so we keep the iproc_pcie pointer directly in
+bus->sysdata.
+
+In addition, arm64 does IRQ mapping in pcibios_add_device(), so it
+doesn't need pci_fixup_irqs() as arm32 does.
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Olof Johansson <olof@lixom.net>
+---
+ drivers/pci/host/pcie-iproc.c | 27 ++++++++++++++++++++-------
+ drivers/pci/host/pcie-iproc.h |  4 +++-
+ 2 files changed, 23 insertions(+), 8 deletions(-)
+
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -58,9 +58,17 @@
+ #define SYS_RC_INTX_EN               0x330
+ #define SYS_RC_INTX_MASK             0xf
+ 
+-static inline struct iproc_pcie *sys_to_pcie(struct pci_sys_data *sys)
++static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
+ {
+-	return sys->private_data;
++	struct iproc_pcie *pcie;
++#ifdef CONFIG_ARM
++	struct pci_sys_data *sys = bus->sysdata;
++
++	pcie = sys->private_data;
++#else
++	pcie = bus->sysdata;
++#endif
++	return pcie;
+ }
+ 
+ /**
+@@ -71,8 +79,7 @@ static void __iomem *iproc_pcie_map_cfg_
+ 					    unsigned int devfn,
+ 					    int where)
+ {
+-	struct pci_sys_data *sys = bus->sysdata;
+-	struct iproc_pcie *pcie = sys_to_pcie(sys);
++	struct iproc_pcie *pcie = iproc_data(bus);
+ 	unsigned slot = PCI_SLOT(devfn);
+ 	unsigned fn = PCI_FUNC(devfn);
+ 	unsigned busno = bus->number;
+@@ -186,6 +193,7 @@ static void iproc_pcie_enable(struct ipr
+ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
+ {
+ 	int ret;
++	void *sysdata;
+ 	struct pci_bus *bus;
+ 
+ 	if (!pcie || !pcie->dev || !pcie->base)
+@@ -205,10 +213,13 @@ int iproc_pcie_setup(struct iproc_pcie *
+ 
+ 	iproc_pcie_reset(pcie);
+ 
++#ifdef CONFIG_ARM
+ 	pcie->sysdata.private_data = pcie;
+-
+-	bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops,
+-				  &pcie->sysdata, res);
++	sysdata = &pcie->sysdata;
++#else
++	sysdata = pcie;
++#endif
++	bus = pci_create_root_bus(pcie->dev, 0, &iproc_pcie_ops, sysdata, res);
+ 	if (!bus) {
+ 		dev_err(pcie->dev, "unable to create PCI root bus\n");
+ 		ret = -ENOMEM;
+@@ -226,7 +237,9 @@ int iproc_pcie_setup(struct iproc_pcie *
+ 
+ 	pci_scan_child_bus(bus);
+ 	pci_assign_unassigned_bus_resources(bus);
++#ifdef CONFIG_ARM
+ 	pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
++#endif
+ 	pci_bus_add_devices(bus);
+ 
+ 	return 0;
+--- a/drivers/pci/host/pcie-iproc.h
++++ b/drivers/pci/host/pcie-iproc.h
+@@ -21,7 +21,7 @@
+  * @dev: pointer to device data structure
+  * @base: PCIe host controller I/O register base
+  * @resources: linked list of all PCI resources
+- * @sysdata: Per PCI controller data
++ * @sysdata: Per PCI controller data (ARM-specific)
+  * @root_bus: pointer to root bus
+  * @phy: optional PHY device that controls the Serdes
+  * @irqs: interrupt IDs
+@@ -29,7 +29,9 @@
+ struct iproc_pcie {
+ 	struct device *dev;
+ 	void __iomem *base;
++#ifdef CONFIG_ARM
+ 	struct pci_sys_data sysdata;
++#endif
+ 	struct pci_bus *root_bus;
+ 	struct phy *phy;
+ 	int irqs[IPROC_PCIE_MAX_NUM_IRQS];

target/linux/bcm53xx/patches-4.1/038-PCI-iproc-Fix-ARM64-dependency-in-Kconfig.patch

@@ -0,0 +1,27 @@
+From b00c4415fb231f276221c634a47ce7328df9aae5 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Mon, 27 Jul 2015 15:42:19 -0700
+Subject: [PATCH 38/40] PCI: iproc: Fix ARM64 dependency in Kconfig
+
+Allow Broadcom iProc PCIe core driver to be compiled for ARM64
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+Acked-by: Bjorn Helgaas <bhelgaas@google.com>
+Signed-off-by: Olof Johansson <olof@lixom.net>
+---
+ drivers/pci/host/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pci/host/Kconfig
++++ b/drivers/pci/host/Kconfig
+@@ -108,7 +108,7 @@ config PCI_VERSATILE
+ 
+ config PCIE_IPROC
+ 	tristate "Broadcom iProc PCIe controller"
+-	depends on OF && ARM
++	depends on OF && (ARM || ARM64)
+ 	default n
+ 	help
+ 	  This enables the iProc PCIe core controller support for Broadcom's

target/linux/bcm53xx/patches-4.1/140-PCI-iproc-Fix-code-comment-to-match-code.patch

@@ -0,0 +1,28 @@
+From 5d92f41c48c5e3c6fa5be87e3d6fca57e2fbb127 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 15 Sep 2015 17:39:15 -0700
+Subject: [PATCH 140/147] PCI: iproc: Fix code comment to match code
+
+Fix code comment in pcie-iproc.h so it matches the code.
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ drivers/pci/host/pcie-iproc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pci/host/pcie-iproc.h
++++ b/drivers/pci/host/pcie-iproc.h
+@@ -20,11 +20,11 @@
+  * iProc PCIe device
+  * @dev: pointer to device data structure
+  * @base: PCIe host controller I/O register base
+- * @resources: linked list of all PCI resources
+  * @sysdata: Per PCI controller data (ARM-specific)
+  * @root_bus: pointer to root bus
+  * @phy: optional PHY device that controls the Serdes
+  * @irqs: interrupt IDs
++ * @map_irq: function callback to map interrupts
+  */
+ struct iproc_pcie {
+ 	struct device *dev;

target/linux/bcm53xx/patches-4.1/141-PCI-iproc-Remove-unused-struct-iproc_pcie.irqs.patch

@@ -0,0 +1,33 @@
+From 98aac697a83db6e1d004e5d61cf6c976a0b1c35a Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 15 Sep 2015 17:39:16 -0700
+Subject: [PATCH 141/147] PCI: iproc: Remove unused struct iproc_pcie.irqs[]
+
+Remove unused struct iproc_pcie member irqs[] and unused #define
+IPROC_PCIE_MAX_NUM_IRQS.
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ drivers/pci/host/pcie-iproc.h | 3 ---
+ 1 file changed, 3 deletions(-)
+
+--- a/drivers/pci/host/pcie-iproc.h
++++ b/drivers/pci/host/pcie-iproc.h
+@@ -14,8 +14,6 @@
+ #ifndef _PCIE_IPROC_H
+ #define _PCIE_IPROC_H
+ 
+-#define IPROC_PCIE_MAX_NUM_IRQS 6
+-
+ /**
+  * iProc PCIe device
+  * @dev: pointer to device data structure
+@@ -34,7 +32,6 @@ struct iproc_pcie {
+ #endif
+ 	struct pci_bus *root_bus;
+ 	struct phy *phy;
+-	int irqs[IPROC_PCIE_MAX_NUM_IRQS];
+ 	int (*map_irq)(const struct pci_dev *, u8, u8);
+ };
+ 

target/linux/bcm53xx/patches-4.1/142-PCI-iproc-Call-pci_fixup_irqs-for-ARM64-as-well-as-A.patch

@@ -0,0 +1,31 @@
+From bdb8a1844f3113ec08915d1e8e3fd5686fb2fb78 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 15 Sep 2015 17:39:17 -0700
+Subject: [PATCH 142/147] PCI: iproc: Call pci_fixup_irqs() for ARM64 as well
+ as ARM
+
+After 459a07721c11 ("PCI: Build setup-irq.o for arm64"), we build
+setup-irq.o for arm64, so we can use pci_fixup_irqs() on both arm and
+arm64.
+
+Remove the "#ifdef CONFIG_ARM" around the call to pci_fixup_irqs().
+
+[bhelgaas: changelog]
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ drivers/pci/host/pcie-iproc.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -237,9 +237,7 @@ int iproc_pcie_setup(struct iproc_pcie *
+ 
+ 	pci_scan_child_bus(bus);
+ 	pci_assign_unassigned_bus_resources(bus);
+-#ifdef CONFIG_ARM
+ 	pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
+-#endif
+ 	pci_bus_add_devices(bus);
+ 
+ 	return 0;

target/linux/bcm53xx/patches-4.1/143-PCI-iproc-Fix-PCIe-reset-logic.patch

@@ -0,0 +1,62 @@
+From 199ff14100095d52cd1b232cc0f3b12f348b5b07 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 15 Sep 2015 17:39:18 -0700
+Subject: [PATCH 143/147] PCI: iproc: Fix PCIe reset logic
+
+The current reset logic does not always properly reset the device.  For
+example, in the case when the perst_b signal is already de-asserted in the
+bootloader, the current reset logic fails to trigger a proper assert ->
+de-assert reset sequence.
+
+Fix the issue by always triggering the proper reset sequence.
+
+Also explicitly select the desired reset source, i.e., perst_b, and reduce
+the wait time after the device comes out of reset from 250 ms to 100 ms,
+based on recommendation from the ASIC team.
+
+Tested-by: Vladimir Dreizin <vdreizin@broadcom.com>
+Tested-by: Darren Edamura <dedamura@broadcom.com>
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Vladimir Dreizin <vdreizin@broadcom.com>
+Reviewed-by: Trac Hoang <trhoang@broadcom.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+---
+ drivers/pci/host/pcie-iproc.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -31,6 +31,8 @@
+ #include "pcie-iproc.h"
+ 
+ #define CLK_CONTROL_OFFSET           0x000
++#define EP_PERST_SOURCE_SELECT_SHIFT 2
++#define EP_PERST_SOURCE_SELECT       BIT(EP_PERST_SOURCE_SELECT_SHIFT)
+ #define EP_MODE_SURVIVE_PERST_SHIFT  1
+ #define EP_MODE_SURVIVE_PERST        BIT(EP_MODE_SURVIVE_PERST_SHIFT)
+ #define RC_PCIE_RST_OUTPUT_SHIFT     0
+@@ -119,15 +121,18 @@ static void iproc_pcie_reset(struct ipro
+ 	u32 val;
+ 
+ 	/*
+-	 * Configure the PCIe controller as root complex and send a downstream
+-	 * reset
++	 * Select perst_b signal as reset source. Put the device into reset,
++	 * and then bring it out of reset
+ 	 */
+-	val = EP_MODE_SURVIVE_PERST | RC_PCIE_RST_OUTPUT;
++	val = readl(pcie->base + CLK_CONTROL_OFFSET);
++	val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
++		~RC_PCIE_RST_OUTPUT;
+ 	writel(val, pcie->base + CLK_CONTROL_OFFSET);
+ 	udelay(250);
+-	val &= ~EP_MODE_SURVIVE_PERST;
++
++	val |= RC_PCIE_RST_OUTPUT;
+ 	writel(val, pcie->base + CLK_CONTROL_OFFSET);
+-	msleep(250);
++	msleep(100);
+ }
+ 
+ static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)

target/linux/bcm53xx/patches-4.1/144-PCI-iproc-Improve-link-detection-logic.patch

@@ -0,0 +1,84 @@
+From aaf22ab4e916afa68a2e1aed4e913b76cbd58276 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 15 Sep 2015 17:39:19 -0700
+Subject: [PATCH 144/147] PCI: iproc: Improve link detection logic
+
+Improve the link detection logic by explicitly querying the link status
+register to ensure link is active.
+
+Also force class to PCI_CLASS_BRIDGE_PCI (0x0604) through the host
+configuration space register.
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Anup Patel <anup.patel@broadcom.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+---
+ drivers/pci/host/pcie-iproc.c | 29 +++++++++++++++++++++++------
+ 1 file changed, 23 insertions(+), 6 deletions(-)
+
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -60,6 +60,12 @@
+ #define SYS_RC_INTX_EN               0x330
+ #define SYS_RC_INTX_MASK             0xf
+ 
++#define PCIE_LINK_STATUS_OFFSET      0xf0c
++#define PCIE_PHYLINKUP_SHIFT         3
++#define PCIE_PHYLINKUP               BIT(PCIE_PHYLINKUP_SHIFT)
++#define PCIE_DL_ACTIVE_SHIFT         2
++#define PCIE_DL_ACTIVE               BIT(PCIE_DL_ACTIVE_SHIFT)
++
+ static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
+ {
+ 	struct iproc_pcie *pcie;
+@@ -138,9 +144,15 @@ static void iproc_pcie_reset(struct ipro
+ static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
+ {
+ 	u8 hdr_type;
+-	u32 link_ctrl;
++	u32 link_ctrl, class, val;
+ 	u16 pos, link_status;
+-	int link_is_active = 0;
++	bool link_is_active = false;
++
++	val = readl(pcie->base + PCIE_LINK_STATUS_OFFSET);
++	if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
++		dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
++		return -ENODEV;
++	}
+ 
+ 	/* make sure we are not in EP mode */
+ 	pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
+@@ -150,14 +162,19 @@ static int iproc_pcie_check_link(struct
+ 	}
+ 
+ 	/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
+-	pci_bus_write_config_word(bus, 0, PCI_CLASS_DEVICE,
+-				  PCI_CLASS_BRIDGE_PCI);
++#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
++#define PCI_CLASS_BRIDGE_MASK      0xffff00
++#define PCI_CLASS_BRIDGE_SHIFT     8
++	pci_bus_read_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, &class);
++	class &= ~PCI_CLASS_BRIDGE_MASK;
++	class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
++	pci_bus_write_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, class);
+ 
+ 	/* check link status to see if link is active */
+ 	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
+ 	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
+ 	if (link_status & PCI_EXP_LNKSTA_NLW)
+-		link_is_active = 1;
++		link_is_active = true;
+ 
+ 	if (!link_is_active) {
+ 		/* try GEN 1 link speed */
+@@ -181,7 +198,7 @@ static int iproc_pcie_check_link(struct
+ 			pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
+ 						 &link_status);
+ 			if (link_status & PCI_EXP_LNKSTA_NLW)
+-				link_is_active = 1;
++				link_is_active = true;
+ 		}
+ 	}
+ 

target/linux/bcm53xx/patches-4.1/145-PCI-iproc-Update-PCIe-device-tree-bindings.patch

@@ -0,0 +1,50 @@
+From 8d0afa1a93be2da954c85392bbc7b2264c9d241c Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 15 Sep 2015 17:39:20 -0700
+Subject: [PATCH 145/147] PCI: iproc: Update PCIe device tree bindings
+
+Update the device tree bindings with added support for outbound mapping
+configurations.
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ .../devicetree/bindings/pci/brcm,iproc-pcie.txt      | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
++++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
+@@ -17,6 +17,21 @@ Optional properties:
+ - phys: phandle of the PCIe PHY device
+ - phy-names: must be "pcie-phy"
+ 
++- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done
++by the ASIC after power on reset. In this case, SW needs to configure it
++
++If the brcm,pcie-ob property is present, the following properties become
++effective:
++
++Required:
++- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal
++address used by the iProc PCIe core (not the PCIe address)
++- brcm,pcie-ob-window-size: The outbound address mapping window size (in MB)
++
++Optional:
++- brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
++increase the outbound window size
++
+ Example:
+ 	pcie0: pcie@18012000 {
+ 		compatible = "brcm,iproc-pcie";
+@@ -38,6 +53,11 @@ Example:
+ 
+ 		phys = <&phy 0 5>;
+ 		phy-names = "pcie-phy";
++
++		brcm,pcie-ob;
++		brcm,pcie-ob-oarr-size;
++		brcm,pcie-ob-axi-offset = <0x00000000>;
++		brcm,pcie-ob-window-size = <256>;
+ 	};
+ 
+ 	pcie1: pcie@18013000 {

target/linux/bcm53xx/patches-4.1/146-PCI-iproc-Add-outbound-mapping-support.patch

@@ -0,0 +1,236 @@
+From e99a187b5c5f60fe55ca586f82ac1a3557fb166a Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Fri, 16 Oct 2015 08:18:24 -0500
+Subject: [PATCH 146/147] PCI: iproc: Add outbound mapping support
+
+Certain SoCs require the PCIe outbound mapping to be configured in
+software.  Add support for those chips.
+
+[jonmason: Use %pap format when printing size_t to avoid warnings in 32-bit
+build.]
+[arnd: Use div64_u64() instead of "%" to avoid __aeabi_uldivmod link error
+in 32-bit build.]
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Jon Mason <jonmason@broadcom.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ drivers/pci/host/pcie-iproc-platform.c |  27 ++++++++
+ drivers/pci/host/pcie-iproc.c          | 115 +++++++++++++++++++++++++++++++++
+ drivers/pci/host/pcie-iproc.h          |  17 +++++
+ 3 files changed, 159 insertions(+)
+
+--- a/drivers/pci/host/pcie-iproc-platform.c
++++ b/drivers/pci/host/pcie-iproc-platform.c
+@@ -54,6 +54,33 @@ static int iproc_pcie_pltfm_probe(struct
+ 		return -ENOMEM;
+ 	}
+ 
++	if (of_property_read_bool(np, "brcm,pcie-ob")) {
++		u32 val;
++
++		ret = of_property_read_u32(np, "brcm,pcie-ob-axi-offset",
++					   &val);
++		if (ret) {
++			dev_err(pcie->dev,
++				"missing brcm,pcie-ob-axi-offset property\n");
++			return ret;
++		}
++		pcie->ob.axi_offset = val;
++
++		ret = of_property_read_u32(np, "brcm,pcie-ob-window-size",
++					   &val);
++		if (ret) {
++			dev_err(pcie->dev,
++				"missing brcm,pcie-ob-window-size property\n");
++			return ret;
++		}
++		pcie->ob.window_size = (resource_size_t)val * SZ_1M;
++
++		if (of_property_read_bool(np, "brcm,pcie-ob-oarr-size"))
++			pcie->ob.set_oarr_size = true;
++
++		pcie->need_ob_cfg = true;
++	}
++
+ 	/* PHY use is optional */
+ 	pcie->phy = devm_phy_get(&pdev->dev, "pcie-phy");
+ 	if (IS_ERR(pcie->phy)) {
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -66,6 +66,18 @@
+ #define PCIE_DL_ACTIVE_SHIFT         2
+ #define PCIE_DL_ACTIVE               BIT(PCIE_DL_ACTIVE_SHIFT)
+ 
++#define OARR_VALID_SHIFT             0
++#define OARR_VALID                   BIT(OARR_VALID_SHIFT)
++#define OARR_SIZE_CFG_SHIFT          1
++#define OARR_SIZE_CFG                BIT(OARR_SIZE_CFG_SHIFT)
++
++#define OARR_LO(window)              (0xd20 + (window) * 8)
++#define OARR_HI(window)              (0xd24 + (window) * 8)
++#define OMAP_LO(window)              (0xd40 + (window) * 8)
++#define OMAP_HI(window)              (0xd44 + (window) * 8)
++
++#define MAX_NUM_OB_WINDOWS           2
++
+ static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
+ {
+ 	struct iproc_pcie *pcie;
+@@ -212,6 +224,101 @@ static void iproc_pcie_enable(struct ipr
+ 	writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
+ }
+ 
++/**
++ * Some iProc SoCs require the SW to configure the outbound address mapping
++ *
++ * Outbound address translation:
++ *
++ * iproc_pcie_address = axi_address - axi_offset
++ * OARR = iproc_pcie_address
++ * OMAP = pci_addr
++ *
++ * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
++ */
++static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
++			       u64 pci_addr, resource_size_t size)
++{
++	struct iproc_pcie_ob *ob = &pcie->ob;
++	unsigned i;
++	u64 max_size = (u64)ob->window_size * MAX_NUM_OB_WINDOWS;
++	u64 remainder;
++
++	if (size > max_size) {
++		dev_err(pcie->dev,
++			"res size 0x%pap exceeds max supported size 0x%llx\n",
++			&size, max_size);
++		return -EINVAL;
++	}
++
++	div64_u64_rem(size, ob->window_size, &remainder);
++	if (remainder) {
++		dev_err(pcie->dev,
++			"res size %pap needs to be multiple of window size %pap\n",
++			&size, &ob->window_size);
++		return -EINVAL;
++	}
++
++	if (axi_addr < ob->axi_offset) {
++		dev_err(pcie->dev,
++			"axi address %pap less than offset %pap\n",
++			&axi_addr, &ob->axi_offset);
++		return -EINVAL;
++	}
++
++	/*
++	 * Translate the AXI address to the internal address used by the iProc
++	 * PCIe core before programming the OARR
++	 */
++	axi_addr -= ob->axi_offset;
++
++	for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) {
++		writel(lower_32_bits(axi_addr) | OARR_VALID |
++		       (ob->set_oarr_size ? 1 : 0), pcie->base + OARR_LO(i));
++		writel(upper_32_bits(axi_addr), pcie->base + OARR_HI(i));
++		writel(lower_32_bits(pci_addr), pcie->base + OMAP_LO(i));
++		writel(upper_32_bits(pci_addr), pcie->base + OMAP_HI(i));
++
++		size -= ob->window_size;
++		if (size == 0)
++			break;
++
++		axi_addr += ob->window_size;
++		pci_addr += ob->window_size;
++	}
++
++	return 0;
++}
++
++static int iproc_pcie_map_ranges(struct iproc_pcie *pcie,
++				 struct list_head *resources)
++{
++	struct resource_entry *window;
++	int ret;
++
++	resource_list_for_each_entry(window, resources) {
++		struct resource *res = window->res;
++		u64 res_type = resource_type(res);
++
++		switch (res_type) {
++		case IORESOURCE_IO:
++		case IORESOURCE_BUS:
++			break;
++		case IORESOURCE_MEM:
++			ret = iproc_pcie_setup_ob(pcie, res->start,
++						  res->start - window->offset,
++						  resource_size(res));
++			if (ret)
++				return ret;
++			break;
++		default:
++			dev_err(pcie->dev, "invalid resource %pR\n", res);
++			return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
+ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
+ {
+ 	int ret;
+@@ -235,6 +342,14 @@ int iproc_pcie_setup(struct iproc_pcie *
+ 
+ 	iproc_pcie_reset(pcie);
+ 
++	if (pcie->need_ob_cfg) {
++		ret = iproc_pcie_map_ranges(pcie, res);
++		if (ret) {
++			dev_err(pcie->dev, "map failed\n");
++			goto err_power_off_phy;
++		}
++	}
++
+ #ifdef CONFIG_ARM
+ 	pcie->sysdata.private_data = pcie;
+ 	sysdata = &pcie->sysdata;
+--- a/drivers/pci/host/pcie-iproc.h
++++ b/drivers/pci/host/pcie-iproc.h
+@@ -15,6 +15,19 @@
+ #define _PCIE_IPROC_H
+ 
+ /**
++ * iProc PCIe outbound mapping
++ * @set_oarr_size: indicates the OARR size bit needs to be set
++ * @axi_offset: offset from the AXI address to the internal address used by
++ * the iProc PCIe core
++ * @window_size: outbound window size
++ */
++struct iproc_pcie_ob {
++	bool set_oarr_size;
++	resource_size_t axi_offset;
++	resource_size_t window_size;
++};
++
++/**
+  * iProc PCIe device
+  * @dev: pointer to device data structure
+  * @base: PCIe host controller I/O register base
+@@ -23,6 +36,8 @@
+  * @phy: optional PHY device that controls the Serdes
+  * @irqs: interrupt IDs
+  * @map_irq: function callback to map interrupts
++ * @need_ob_cfg: indidates SW needs to configure the outbound mapping window
++ * @ob: outbound mapping parameters
+  */
+ struct iproc_pcie {
+ 	struct device *dev;
+@@ -33,6 +48,8 @@ struct iproc_pcie {
+ 	struct pci_bus *root_bus;
+ 	struct phy *phy;
+ 	int (*map_irq)(const struct pci_dev *, u8, u8);
++	bool need_ob_cfg;
++	struct iproc_pcie_ob ob;
+ };
+ 
+ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res);

target/linux/bcm53xx/patches-4.1/147-PCI-iproc-Fix-header-comment-Corporation-misspelling.patch

@@ -0,0 +1,25 @@
+From be908d21b2e9c2cab1ef568dfca4f9777611b3dd Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <f.fainelli@gmail.com>
+Date: Fri, 16 Oct 2015 12:04:04 -0700
+Subject: [PATCH 147/147] PCI: iproc: Fix header comment "Corporation"
+ misspelling
+
+Fix an obvious "Broadcom Corporation" typo in a header comment.
+
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Ray Jui <rjui@broadcom.com>
+---
+ drivers/pci/host/pcie-iproc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -1,6 +1,6 @@
+ /*
+  * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
+- * Copyright (C) 2015 Broadcom Corporatcommon ion
++ * Copyright (C) 2015 Broadcom Corporation
+  *
+  * This program is free software; you can redistribute it and/or
+  * modify it under the terms of the GNU General Public License as

target/linux/bcm53xx/patches-4.1/150-PCI-iproc-Update-iProc-PCIe-device-tree-binding.patch

@@ -0,0 +1,29 @@
+From d85a955118c8d8679d4f746fe2189c172d7c365f Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Mon, 16 Nov 2015 17:18:05 -0800
+Subject: [PATCH 150/154] PCI: iproc: Update iProc PCIe device tree binding
+
+Add a new compatible string "brcm,iproc-pcie-paxc", for PAXC based iProc
+PCIe root complex. A PAXC based PCIe root complex is connected to
+emulated endpoint devices internal to the ASIC
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+---
+ Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
++++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
+@@ -1,7 +1,10 @@
+ * Broadcom iProc PCIe controller with the platform bus interface
+ 
+ Required properties:
+-- compatible: Must be "brcm,iproc-pcie"
++- compatible: Must be "brcm,iproc-pcie" for PAXB, or "brcm,iproc-pcie-paxc"
++  for PAXC. PAXB based root complex is used for external endpoint devices.
++  PAXC based root complex is connected to emulated endpoint devices
++  internal to the ASIC
+ - reg: base address and length of the PCIe controller I/O register space
+ - #interrupt-cells: set to <1>
+ - interrupt-map-mask and interrupt-map, standard PCI properties to define the

target/linux/bcm53xx/patches-4.1/151-PCI-iproc-Add-PAXC-interface-support.patch

@@ -0,0 +1,428 @@
+From a13fc4733b25d6dad6ec1826f09225c69ee21e3a Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Mon, 16 Nov 2015 17:41:43 -0800
+Subject: [PATCH 151/154] PCI: iproc: Add PAXC interface support
+
+Traditionally, all iProc PCIe root complexes use PAXB based wrapper,
+with an integrated on-chip Serdes to support external endpoint devices.
+On newer iProc platforms, a PAXC based wrapper is introduced, for
+connection with internally emulated PCIe endpoint devices in the ASIC
+
+This patch adds support for PAXC based iProc PCIe root complex in the
+iProc PCIe core driver. This change fators out common logic between
+PAXB and PAXC, and use tables to store register offsets that are
+different between PAXB and PAXC. This allows the driver to be scaled to
+support subsequent PAXC revisions in the future
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+---
+ drivers/pci/host/pcie-iproc-platform.c |  24 +++-
+ drivers/pci/host/pcie-iproc.c          | 202 +++++++++++++++++++++++++++------
+ drivers/pci/host/pcie-iproc.h          |  19 ++++
+ 3 files changed, 205 insertions(+), 40 deletions(-)
+
+--- a/drivers/pci/host/pcie-iproc-platform.c
++++ b/drivers/pci/host/pcie-iproc-platform.c
+@@ -26,8 +26,21 @@
+ 
+ #include "pcie-iproc.h"
+ 
++static const struct of_device_id iproc_pcie_of_match_table[] = {
++	{
++		.compatible = "brcm,iproc-pcie",
++		.data = (int *)IPROC_PCIE_PAXB,
++	}, {
++		.compatible = "brcm,iproc-pcie-paxc",
++		.data = (int *)IPROC_PCIE_PAXC,
++	},
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
++
+ static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
+ {
++	const struct of_device_id *of_id;
+ 	struct iproc_pcie *pcie;
+ 	struct device_node *np = pdev->dev.of_node;
+ 	struct resource reg;
+@@ -35,11 +48,16 @@ static int iproc_pcie_pltfm_probe(struct
+ 	LIST_HEAD(res);
+ 	int ret;
+ 
++	of_id = of_match_device(iproc_pcie_of_match_table, &pdev->dev);
++	if (!of_id)
++		return -EINVAL;
++
+ 	pcie = devm_kzalloc(&pdev->dev, sizeof(struct iproc_pcie), GFP_KERNEL);
+ 	if (!pcie)
+ 		return -ENOMEM;
+ 
+ 	pcie->dev = &pdev->dev;
++	pcie->type = (enum iproc_pcie_type)of_id->data;
+ 	platform_set_drvdata(pdev, pcie);
+ 
+ 	ret = of_address_to_resource(np, 0, &reg);
+@@ -114,12 +132,6 @@ static int iproc_pcie_pltfm_remove(struc
+ 	return iproc_pcie_remove(pcie);
+ }
+ 
+-static const struct of_device_id iproc_pcie_of_match_table[] = {
+-	{ .compatible = "brcm,iproc-pcie", },
+-	{ /* sentinel */ }
+-};
+-MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
+-
+ static struct platform_driver iproc_pcie_pltfm_driver = {
+ 	.driver = {
+ 		.name = "iproc-pcie",
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -30,20 +30,16 @@
+ 
+ #include "pcie-iproc.h"
+ 
+-#define CLK_CONTROL_OFFSET           0x000
+ #define EP_PERST_SOURCE_SELECT_SHIFT 2
+ #define EP_PERST_SOURCE_SELECT       BIT(EP_PERST_SOURCE_SELECT_SHIFT)
+ #define EP_MODE_SURVIVE_PERST_SHIFT  1
+ #define EP_MODE_SURVIVE_PERST        BIT(EP_MODE_SURVIVE_PERST_SHIFT)
+ #define RC_PCIE_RST_OUTPUT_SHIFT     0
+ #define RC_PCIE_RST_OUTPUT           BIT(RC_PCIE_RST_OUTPUT_SHIFT)
++#define PAXC_RESET_MASK              0x7f
+ 
+-#define CFG_IND_ADDR_OFFSET          0x120
+ #define CFG_IND_ADDR_MASK            0x00001ffc
+ 
+-#define CFG_IND_DATA_OFFSET          0x124
+-
+-#define CFG_ADDR_OFFSET              0x1f8
+ #define CFG_ADDR_BUS_NUM_SHIFT       20
+ #define CFG_ADDR_BUS_NUM_MASK        0x0ff00000
+ #define CFG_ADDR_DEV_NUM_SHIFT       15
+@@ -55,12 +51,8 @@
+ #define CFG_ADDR_CFG_TYPE_SHIFT      0
+ #define CFG_ADDR_CFG_TYPE_MASK       0x00000003
+ 
+-#define CFG_DATA_OFFSET              0x1fc
+-
+-#define SYS_RC_INTX_EN               0x330
+ #define SYS_RC_INTX_MASK             0xf
+ 
+-#define PCIE_LINK_STATUS_OFFSET      0xf0c
+ #define PCIE_PHYLINKUP_SHIFT         3
+ #define PCIE_PHYLINKUP               BIT(PCIE_PHYLINKUP_SHIFT)
+ #define PCIE_DL_ACTIVE_SHIFT         2
+@@ -71,12 +63,54 @@
+ #define OARR_SIZE_CFG_SHIFT          1
+ #define OARR_SIZE_CFG                BIT(OARR_SIZE_CFG_SHIFT)
+ 
+-#define OARR_LO(window)              (0xd20 + (window) * 8)
+-#define OARR_HI(window)              (0xd24 + (window) * 8)
+-#define OMAP_LO(window)              (0xd40 + (window) * 8)
+-#define OMAP_HI(window)              (0xd44 + (window) * 8)
+-
+ #define MAX_NUM_OB_WINDOWS           2
++#define MAX_NUM_PAXC_PF              4
++
++#define IPROC_PCIE_REG_INVALID 0xffff
++
++enum iproc_pcie_reg {
++	IPROC_PCIE_CLK_CTRL = 0,
++	IPROC_PCIE_CFG_IND_ADDR,
++	IPROC_PCIE_CFG_IND_DATA,
++	IPROC_PCIE_CFG_ADDR,
++	IPROC_PCIE_CFG_DATA,
++	IPROC_PCIE_INTX_EN,
++	IPROC_PCIE_OARR_LO,
++	IPROC_PCIE_OARR_HI,
++	IPROC_PCIE_OMAP_LO,
++	IPROC_PCIE_OMAP_HI,
++	IPROC_PCIE_LINK_STATUS,
++};
++
++/* iProc PCIe PAXB registers */
++static const u16 iproc_pcie_reg_paxb[] = {
++	[IPROC_PCIE_CLK_CTRL]     = 0x000,
++	[IPROC_PCIE_CFG_IND_ADDR] = 0x120,
++	[IPROC_PCIE_CFG_IND_DATA] = 0x124,
++	[IPROC_PCIE_CFG_ADDR]     = 0x1f8,
++	[IPROC_PCIE_CFG_DATA]     = 0x1fc,
++	[IPROC_PCIE_INTX_EN]      = 0x330,
++	[IPROC_PCIE_OARR_LO]      = 0xd20,
++	[IPROC_PCIE_OARR_HI]      = 0xd24,
++	[IPROC_PCIE_OMAP_LO]      = 0xd40,
++	[IPROC_PCIE_OMAP_HI]      = 0xd44,
++	[IPROC_PCIE_LINK_STATUS]  = 0xf0c,
++};
++
++/* iProc PCIe PAXC v1 registers */
++static const u16 iproc_pcie_reg_paxc[] = {
++	[IPROC_PCIE_CLK_CTRL]     = 0x000,
++	[IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
++	[IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
++	[IPROC_PCIE_CFG_ADDR]     = 0x1f8,
++	[IPROC_PCIE_CFG_DATA]     = 0x1fc,
++	[IPROC_PCIE_INTX_EN]      = IPROC_PCIE_REG_INVALID,
++	[IPROC_PCIE_OARR_LO]      = IPROC_PCIE_REG_INVALID,
++	[IPROC_PCIE_OARR_HI]      = IPROC_PCIE_REG_INVALID,
++	[IPROC_PCIE_OMAP_LO]      = IPROC_PCIE_REG_INVALID,
++	[IPROC_PCIE_OMAP_HI]      = IPROC_PCIE_REG_INVALID,
++	[IPROC_PCIE_LINK_STATUS]  = IPROC_PCIE_REG_INVALID,
++};
+ 
+ static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
+ {
+@@ -91,6 +125,65 @@ static inline struct iproc_pcie *iproc_d
+ 	return pcie;
+ }
+ 
++static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
++{
++	return !!(reg_offset == IPROC_PCIE_REG_INVALID);
++}
++
++static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
++					enum iproc_pcie_reg reg)
++{
++	return pcie->reg_offsets[reg];
++}
++
++static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
++				      enum iproc_pcie_reg reg)
++{
++	u16 offset = iproc_pcie_reg_offset(pcie, reg);
++
++	if (iproc_pcie_reg_is_invalid(offset))
++		return 0;
++
++	return readl(pcie->base + offset);
++}
++
++static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
++					enum iproc_pcie_reg reg, u32 val)
++{
++	u16 offset = iproc_pcie_reg_offset(pcie, reg);
++
++	if (iproc_pcie_reg_is_invalid(offset))
++		return;
++
++	writel(val, pcie->base + offset);
++}
++
++static inline void iproc_pcie_ob_write(struct iproc_pcie *pcie,
++				       enum iproc_pcie_reg reg,
++				       unsigned window, u32 val)
++{
++	u16 offset = iproc_pcie_reg_offset(pcie, reg);
++
++	if (iproc_pcie_reg_is_invalid(offset))
++		return;
++
++	writel(val, pcie->base + offset + (window * 8));
++}
++
++static inline bool iproc_pcie_device_is_valid(struct iproc_pcie *pcie,
++					      unsigned int slot,
++					      unsigned int fn)
++{
++	if (slot > 0)
++		return false;
++
++	/* PAXC can only support limited number of functions */
++	if (pcie->type == IPROC_PCIE_PAXC && fn >= MAX_NUM_PAXC_PF)
++		return false;
++
++	return true;
++}
++
+ /**
+  * Note access to the configuration registers are protected at the higher layer
+  * by 'pci_lock' in drivers/pci/access.c
+@@ -104,28 +197,34 @@ static void __iomem *iproc_pcie_map_cfg_
+ 	unsigned fn = PCI_FUNC(devfn);
+ 	unsigned busno = bus->number;
+ 	u32 val;
++	u16 offset;
++
++	if (!iproc_pcie_device_is_valid(pcie, slot, fn))
++		return NULL;
+ 
+ 	/* root complex access */
+ 	if (busno == 0) {
+-		if (slot >= 1)
++		iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
++				     where & CFG_IND_ADDR_MASK);
++		offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
++		if (iproc_pcie_reg_is_invalid(offset))
+ 			return NULL;
+-		writel(where & CFG_IND_ADDR_MASK,
+-		       pcie->base + CFG_IND_ADDR_OFFSET);
+-		return (pcie->base + CFG_IND_DATA_OFFSET);
++		else
++			return (pcie->base + offset);
+ 	}
+ 
+-	if (fn > 1)
+-		return NULL;
+-
+ 	/* EP device access */
+ 	val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
+ 		(slot << CFG_ADDR_DEV_NUM_SHIFT) |
+ 		(fn << CFG_ADDR_FUNC_NUM_SHIFT) |
+ 		(where & CFG_ADDR_REG_NUM_MASK) |
+ 		(1 & CFG_ADDR_CFG_TYPE_MASK);
+-	writel(val, pcie->base + CFG_ADDR_OFFSET);
+-
+-	return (pcie->base + CFG_DATA_OFFSET);
++	iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
++	offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
++	if (iproc_pcie_reg_is_invalid(offset))
++		return NULL;
++	else
++		return (pcie->base + offset);
+ }
+ 
+ static struct pci_ops iproc_pcie_ops = {
+@@ -138,18 +237,29 @@ static void iproc_pcie_reset(struct ipro
+ {
+ 	u32 val;
+ 
++	if (pcie->type == IPROC_PCIE_PAXC) {
++		val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
++		val &= ~PAXC_RESET_MASK;
++		iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
++		udelay(100);
++		val |= PAXC_RESET_MASK;
++		iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
++		udelay(100);
++		return;
++	}
++
+ 	/*
+ 	 * Select perst_b signal as reset source. Put the device into reset,
+ 	 * and then bring it out of reset
+ 	 */
+-	val = readl(pcie->base + CLK_CONTROL_OFFSET);
++	val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
+ 	val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
+ 		~RC_PCIE_RST_OUTPUT;
+-	writel(val, pcie->base + CLK_CONTROL_OFFSET);
++	iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
+ 	udelay(250);
+ 
+ 	val |= RC_PCIE_RST_OUTPUT;
+-	writel(val, pcie->base + CLK_CONTROL_OFFSET);
++	iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
+ 	msleep(100);
+ }
+ 
+@@ -160,7 +270,14 @@ static int iproc_pcie_check_link(struct
+ 	u16 pos, link_status;
+ 	bool link_is_active = false;
+ 
+-	val = readl(pcie->base + PCIE_LINK_STATUS_OFFSET);
++	/*
++	 * PAXC connects to emulated endpoint devices directly and does not
++	 * have a Serdes. Therefore skip the link detection logic here
++	 */
++	if (pcie->type == IPROC_PCIE_PAXC)
++		return 0;
++
++	val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
+ 	if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
+ 		dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
+ 		return -ENODEV;
+@@ -221,7 +338,7 @@ static int iproc_pcie_check_link(struct
+ 
+ static void iproc_pcie_enable(struct iproc_pcie *pcie)
+ {
+-	writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
++	iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
+ }
+ 
+ /**
+@@ -272,11 +389,15 @@ static int iproc_pcie_setup_ob(struct ip
+ 	axi_addr -= ob->axi_offset;
+ 
+ 	for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) {
+-		writel(lower_32_bits(axi_addr) | OARR_VALID |
+-		       (ob->set_oarr_size ? 1 : 0), pcie->base + OARR_LO(i));
+-		writel(upper_32_bits(axi_addr), pcie->base + OARR_HI(i));
+-		writel(lower_32_bits(pci_addr), pcie->base + OMAP_LO(i));
+-		writel(upper_32_bits(pci_addr), pcie->base + OMAP_HI(i));
++		iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_LO, i,
++				    lower_32_bits(axi_addr) | OARR_VALID |
++				    (ob->set_oarr_size ? 1 : 0));
++		iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_HI, i,
++				    upper_32_bits(axi_addr));
++		iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_LO, i,
++				    lower_32_bits(pci_addr));
++		iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_HI, i,
++				    upper_32_bits(pci_addr));
+ 
+ 		size -= ob->window_size;
+ 		if (size == 0)
+@@ -340,6 +461,19 @@ int iproc_pcie_setup(struct iproc_pcie *
+ 		goto err_exit_phy;
+ 	}
+ 
++	switch (pcie->type) {
++	case IPROC_PCIE_PAXB:
++		pcie->reg_offsets = iproc_pcie_reg_paxb;
++		break;
++	case IPROC_PCIE_PAXC:
++		pcie->reg_offsets = iproc_pcie_reg_paxc;
++		break;
++	default:
++		dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
++		ret = -EINVAL;
++		goto err_power_off_phy;
++	}
++
+ 	iproc_pcie_reset(pcie);
+ 
+ 	if (pcie->need_ob_cfg) {
+--- a/drivers/pci/host/pcie-iproc.h
++++ b/drivers/pci/host/pcie-iproc.h
+@@ -15,6 +15,20 @@
+ #define _PCIE_IPROC_H
+ 
+ /**
++ * iProc PCIe interface type
++ *
++ * PAXB is the wrapper used in root complex that can be connected to an
++ * external endpoint device
++ *
++ * PAXC is the wrapper used in root complex dedicated for internal emulated
++ * endpoint devices
++ */
++enum iproc_pcie_type {
++	IPROC_PCIE_PAXB = 0,
++	IPROC_PCIE_PAXC,
++};
++
++/**
+  * iProc PCIe outbound mapping
+  * @set_oarr_size: indicates the OARR size bit needs to be set
+  * @axi_offset: offset from the AXI address to the internal address used by
+@@ -29,7 +43,10 @@ struct iproc_pcie_ob {
+ 
+ /**
+  * iProc PCIe device
++ *
+  * @dev: pointer to device data structure
++ * @type: iProc PCIe interface type
++ * @reg_offsets: register offsets
+  * @base: PCIe host controller I/O register base
+  * @sysdata: Per PCI controller data (ARM-specific)
+  * @root_bus: pointer to root bus
+@@ -41,6 +58,8 @@ struct iproc_pcie_ob {
+  */
+ struct iproc_pcie {
+ 	struct device *dev;
++	enum iproc_pcie_type type;
++	const u16 *reg_offsets;
+ 	void __iomem *base;
+ #ifdef CONFIG_ARM
+ 	struct pci_sys_data sysdata;

target/linux/bcm53xx/patches-4.1/152-PCI-iproc-Add-iProc-PCIe-MSI-device-tree-binding.patch

@@ -0,0 +1,67 @@
+From 96b40de5e36ec479dabb88500f1830a87818a809 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Mon, 16 Nov 2015 17:57:33 -0800
+Subject: [PATCH 152/154] PCI: iproc: Add iProc PCIe MSI device tree binding
+
+This patch updates the iProc PCIe device tree bindings with added
+binding information for MSI
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Reviewed-by: Anup Patel <anup.patel@broadcom.com>
+Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+---
+ .../devicetree/bindings/pci/brcm,iproc-pcie.txt    | 35 ++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+--- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
++++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
+@@ -35,6 +35,28 @@ Optional:
+ - brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
+ increase the outbound window size
+ 
++MSI support (optional):
++
++For older platforms without MSI integrated in the GIC, iProc PCIe core provides
++an event queue based MSI support. The iProc MSI uses host memories to store
++MSI posted writes in the event queues
++
++- msi-parent: Link to the device node of the MSI controller. On newer iProc
++platforms, the MSI controller may be gicv2m or gicv3-its. On older iProc
++platforms without MSI support in its interrupt controller, one may use the
++event queue based MSI support integrated within the iProc PCIe core
++
++When the iProc event queue based MSI is used, one needs to define the
++following properties in the MSI device node:
++- compatible: Must be "brcm,iproc-msi"
++- msi-controller: claims itself as an MSI controller
++- interrupt-parent: Link to its parent interrupt device
++- interrupts: List of interrupt IDs from its parent interrupt device
++
++Optional properties:
++- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that
++require the interrupt enable registers to be set explicitly to enable MSI
++
+ Example:
+ 	pcie0: pcie@18012000 {
+ 		compatible = "brcm,iproc-pcie";
+@@ -61,6 +83,19 @@ Example:
+ 		brcm,pcie-ob-oarr-size;
+ 		brcm,pcie-ob-axi-offset = <0x00000000>;
+ 		brcm,pcie-ob-window-size = <256>;
++
++		msi-parent = <&msi0>;
++
++		/* iProc event queue based MSI */
++		msi0: msi@18012000 {
++			compatible = "brcm,iproc-msi";
++			msi-controller;
++			interrupt-parent = <&gic>;
++			interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
++				     <GIC_SPI 97 IRQ_TYPE_NONE>,
++				     <GIC_SPI 98 IRQ_TYPE_NONE>,
++				     <GIC_SPI 99 IRQ_TYPE_NONE>,
++		};
+ 	};
+ 
+ 	pcie1: pcie@18013000 {

target/linux/bcm53xx/patches-4.1/153-PCI-iproc-Add-iProc-PCIe-MSI-support.patch

@@ -0,0 +1,886 @@
+From c81922174d61127ff5baad6059ae148794c72276 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 17 Nov 2015 13:14:37 -0800
+Subject: [PATCH 153/154] PCI: iproc: Add iProc PCIe MSI support
+
+This patch adds PCIe MSI support for both PAXB and PAXC interfaces on
+all iProc based platforms
+
+The iProc PCIe MSI support deploys an event queue based implementation.
+Each event queue is serviced by a GIC interrupt and can support up to 64
+MSI vectors. Host memory is allocated for the event queues, and each event
+queue consists of 64 word-sized entries. MSI data is written to the
+lower 16-bit of each entry, whereas the upper 16-bit of the entry is
+reserved for the controller for internal processing
+
+Each event queue is tracked by a head pointer and tail pointer. Head
+pointer indicates the next entry in the event queue to be processed by
+the driver and is updated by the driver after processing is done.
+The controller uses the tail pointer as the next MSI data insertion
+point. The controller ensures MSI data is flushed to host memory before
+updating the tail pointer and then triggering the interrupt
+
+MSI IRQ affinity is supported by evenly distributing the interrupts to
+each CPU core. MSI vector is moved from one GIC interrupt to another in
+order to steer to the target CPU
+
+Therefore, the actual number of supported MSI vectors is:
+
+M * 64 / N
+
+where M denotes the number of GIC interrupts (event queues), and N
+denotes the number of CPU cores
+
+This iProc event queue based MSI support should not be used with newer
+platforms with integrated MSI support in the GIC (e.g., giv2m or
+gicv3-its)
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Reviewed-by: Anup Patel <anup.patel@broadcom.com>
+Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+---
+ drivers/pci/host/Kconfig               |   9 +
+ drivers/pci/host/Makefile              |   1 +
+ drivers/pci/host/pcie-iproc-bcma.c     |   1 +
+ drivers/pci/host/pcie-iproc-msi.c      | 675 +++++++++++++++++++++++++++++++++
+ drivers/pci/host/pcie-iproc-platform.c |   1 +
+ drivers/pci/host/pcie-iproc.c          |  26 ++
+ drivers/pci/host/pcie-iproc.h          |  23 +-
+ 7 files changed, 734 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/pci/host/pcie-iproc-msi.c
+
+--- a/drivers/pci/host/Kconfig
++++ b/drivers/pci/host/Kconfig
+@@ -115,6 +115,15 @@ config PCIE_IPROC
+ 	  iProc family of SoCs. An appropriate bus interface driver also needs
+ 	  to be enabled
+ 
++config PCIE_IPROC_MSI
++	bool "Broadcom iProc PCIe MSI support"
++	depends on ARCH_BCM_IPROC && PCI_MSI
++	select PCI_MSI_IRQ_DOMAIN
++	default ARCH_BCM_IPROC
++	help
++	  Say Y here if you want to enable MSI support for Broadcom's iProc
++	  PCIe controller
++
+ config PCIE_IPROC_PLATFORM
+ 	tristate "Broadcom iProc PCIe platform bus driver"
+ 	depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST)
+--- a/drivers/pci/host/Makefile
++++ b/drivers/pci/host/Makefile
+@@ -14,5 +14,6 @@ obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
+ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
+ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
+ obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
++obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
+ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
+ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
+--- a/drivers/pci/host/pcie-iproc-bcma.c
++++ b/drivers/pci/host/pcie-iproc-bcma.c
+@@ -55,6 +55,7 @@ static int iproc_pcie_bcma_probe(struct
+ 	bcma_set_drvdata(bdev, pcie);
+ 
+ 	pcie->base = bdev->io_addr;
++	pcie->base_addr = bdev->addr;
+ 
+ 	res_mem.start = bdev->addr_s[0];
+ 	res_mem.end = bdev->addr_s[0] + SZ_128M - 1;
+--- /dev/null
++++ b/drivers/pci/host/pcie-iproc-msi.c
+@@ -0,0 +1,675 @@
++/*
++ * Copyright (C) 2015 Broadcom Corporation
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation version 2.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
++ * kind, whether express or implied; without even the implied warranty
++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/interrupt.h>
++#include <linux/irqchip/chained_irq.h>
++#include <linux/irqdomain.h>
++#include <linux/msi.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
++#include <linux/pci.h>
++
++#include "pcie-iproc.h"
++
++#define IPROC_MSI_INTR_EN_SHIFT        11
++#define IPROC_MSI_INTR_EN              BIT(IPROC_MSI_INTR_EN_SHIFT)
++#define IPROC_MSI_INT_N_EVENT_SHIFT    1
++#define IPROC_MSI_INT_N_EVENT          BIT(IPROC_MSI_INT_N_EVENT_SHIFT)
++#define IPROC_MSI_EQ_EN_SHIFT          0
++#define IPROC_MSI_EQ_EN                BIT(IPROC_MSI_EQ_EN_SHIFT)
++
++#define IPROC_MSI_EQ_MASK              0x3f
++
++/* max number of GIC interrupts */
++#define NR_HW_IRQS                     6
++
++/* number of entries in each event queue */
++#define EQ_LEN                         64
++
++/* size of each event queue memory region */
++#define EQ_MEM_REGION_SIZE             SZ_4K
++
++/* size of each MSI address region */
++#define MSI_MEM_REGION_SIZE            SZ_4K
++
++enum iproc_msi_reg {
++	IPROC_MSI_EQ_PAGE = 0,
++	IPROC_MSI_EQ_PAGE_UPPER,
++	IPROC_MSI_PAGE,
++	IPROC_MSI_PAGE_UPPER,
++	IPROC_MSI_CTRL,
++	IPROC_MSI_EQ_HEAD,
++	IPROC_MSI_EQ_TAIL,
++	IPROC_MSI_INTS_EN,
++	IPROC_MSI_REG_SIZE,
++};
++
++struct iproc_msi;
++
++/**
++ * iProc MSI group
++ *
++ * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
++ * event queue
++ *
++ * @msi: pointer to iProc MSI data
++ * @gic_irq: GIC interrupt
++ * @eq: Event queue number
++ */
++struct iproc_msi_grp {
++	struct iproc_msi *msi;
++	int gic_irq;
++	unsigned int eq;
++};
++
++/**
++ * iProc event queue based MSI
++ *
++ * Only meant to be used on platforms without MSI support integrated into the
++ * GIC
++ *
++ * @pcie: pointer to iProc PCIe data
++ * @reg_offsets: MSI register offsets
++ * @grps: MSI groups
++ * @nr_irqs: number of total interrupts connected to GIC
++ * @nr_cpus: number of toal CPUs
++ * @has_inten_reg: indicates the MSI interrupt enable register needs to be
++ * set explicitly (required for some legacy platforms)
++ * @bitmap: MSI vector bitmap
++ * @bitmap_lock: lock to protect access to the MSI bitmap
++ * @nr_msi_vecs: total number of MSI vectors
++ * @inner_domain: inner IRQ domain
++ * @msi_domain: MSI IRQ domain
++ * @nr_eq_region: required number of 4K aligned memory region for MSI event
++ * queues
++ * @nr_msi_region: required number of 4K aligned address region for MSI posted
++ * writes
++ * @eq_cpu: pointer to allocated memory region for MSI event queues
++ * @eq_dma: DMA address of MSI event queues
++ * @msi_addr: MSI address
++ */
++struct iproc_msi {
++	struct iproc_pcie *pcie;
++	const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE];
++	struct iproc_msi_grp *grps;
++	int nr_irqs;
++	int nr_cpus;
++	bool has_inten_reg;
++	unsigned long *bitmap;
++	struct mutex bitmap_lock;
++	unsigned int nr_msi_vecs;
++	struct irq_domain *inner_domain;
++	struct irq_domain *msi_domain;
++	unsigned int nr_eq_region;
++	unsigned int nr_msi_region;
++	void *eq_cpu;
++	dma_addr_t eq_dma;
++	phys_addr_t msi_addr;
++};
++
++static const u16 iproc_msi_reg_paxb[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
++	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x210, 0x250, 0x254, 0x208 },
++	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x214, 0x258, 0x25c, 0x208 },
++	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x218, 0x260, 0x264, 0x208 },
++	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x21c, 0x268, 0x26c, 0x208 },
++	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x220, 0x270, 0x274, 0x208 },
++	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x224, 0x278, 0x27c, 0x208 },
++};
++
++static const u16 iproc_msi_reg_paxc[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
++	{ 0xc00, 0xc04, 0xc08, 0xc0c, 0xc40, 0xc50, 0xc60 },
++	{ 0xc10, 0xc14, 0xc18, 0xc1c, 0xc44, 0xc54, 0xc64 },
++	{ 0xc20, 0xc24, 0xc28, 0xc2c, 0xc48, 0xc58, 0xc68 },
++	{ 0xc30, 0xc34, 0xc38, 0xc3c, 0xc4c, 0xc5c, 0xc6c },
++};
++
++static inline u32 iproc_msi_read_reg(struct iproc_msi *msi,
++				     enum iproc_msi_reg reg,
++				     unsigned int eq)
++{
++	struct iproc_pcie *pcie = msi->pcie;
++
++	return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]);
++}
++
++static inline void iproc_msi_write_reg(struct iproc_msi *msi,
++				       enum iproc_msi_reg reg,
++				       int eq, u32 val)
++{
++	struct iproc_pcie *pcie = msi->pcie;
++
++	writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]);
++}
++
++static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq)
++{
++	return (hwirq % msi->nr_irqs);
++}
++
++static inline unsigned int iproc_msi_addr_offset(struct iproc_msi *msi,
++						 unsigned long hwirq)
++{
++	if (msi->nr_msi_region > 1)
++		return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE;
++	else
++		return hwirq_to_group(msi, hwirq) * sizeof(u32);
++}
++
++static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq)
++{
++	if (msi->nr_eq_region > 1)
++		return eq * EQ_MEM_REGION_SIZE;
++	else
++		return eq * EQ_LEN * sizeof(u32);
++}
++
++static struct irq_chip iproc_msi_irq_chip = {
++	.name = "iProc-MSI",
++};
++
++static struct msi_domain_info iproc_msi_domain_info = {
++	.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
++		MSI_FLAG_PCI_MSIX,
++	.chip = &iproc_msi_irq_chip,
++};
++
++/*
++ * In iProc PCIe core, each MSI group is serviced by a GIC interrupt and a
++ * dedicated event queue. Each MSI group can support up to 64 MSI vectors
++ *
++ * The number of MSI groups varies between different iProc SoCs. The total
++ * number of CPU cores also varies. To support MSI IRQ affinity, we
++ * distribute GIC interrupts across all available CPUs. MSI vector is moved
++ * from one GIC interrupt to another to steer to the target CPU
++ *
++ * Assuming:
++ * - the number of MSI groups is M
++ * - the number of CPU cores is N
++ * - M is always a multiple of N
++ *
++ * Total number of raw MSI vectors = M * 64
++ * Total number of supported MSI vectors = (M * 64) / N
++ */
++static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq)
++{
++	return (hwirq % msi->nr_cpus);
++}
++
++static inline unsigned long hwirq_to_canonical_hwirq(struct iproc_msi *msi,
++						     unsigned long hwirq)
++{
++	return (hwirq - hwirq_to_cpu(msi, hwirq));
++}
++
++static int iproc_msi_irq_set_affinity(struct irq_data *data,
++				      const struct cpumask *mask, bool force)
++{
++	struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
++	int target_cpu = cpumask_first(mask);
++	int curr_cpu;
++
++	curr_cpu = hwirq_to_cpu(msi, data->hwirq);
++	if (curr_cpu == target_cpu)
++		return IRQ_SET_MASK_OK_DONE;
++
++	/* steer MSI to the target CPU */
++	data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu;
++
++	return IRQ_SET_MASK_OK;
++}
++
++static void iproc_msi_irq_compose_msi_msg(struct irq_data *data,
++					  struct msi_msg *msg)
++{
++	struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
++	dma_addr_t addr;
++
++	addr = msi->msi_addr + iproc_msi_addr_offset(msi, data->hwirq);
++	msg->address_lo = lower_32_bits(addr);
++	msg->address_hi = upper_32_bits(addr);
++	msg->data = data->hwirq;
++}
++
++static struct irq_chip iproc_msi_bottom_irq_chip = {
++	.name = "MSI",
++	.irq_set_affinity = iproc_msi_irq_set_affinity,
++	.irq_compose_msi_msg = iproc_msi_irq_compose_msi_msg,
++};
++
++static int iproc_msi_irq_domain_alloc(struct irq_domain *domain,
++				      unsigned int virq, unsigned int nr_irqs,
++				      void *args)
++{
++	struct iproc_msi *msi = domain->host_data;
++	int hwirq;
++
++	mutex_lock(&msi->bitmap_lock);
++
++	/* allocate 'nr_cpus' number of MSI vectors each time */
++	hwirq = bitmap_find_next_zero_area(msi->bitmap, msi->nr_msi_vecs, 0,
++					   msi->nr_cpus, 0);
++	if (hwirq < msi->nr_msi_vecs) {
++		bitmap_set(msi->bitmap, hwirq, msi->nr_cpus);
++	} else {
++		mutex_unlock(&msi->bitmap_lock);
++		return -ENOSPC;
++	}
++
++	mutex_unlock(&msi->bitmap_lock);
++
++	irq_domain_set_info(domain, virq, hwirq, &iproc_msi_bottom_irq_chip,
++			    domain->host_data, handle_simple_irq, NULL, NULL);
++
++	return 0;
++}
++
++static void iproc_msi_irq_domain_free(struct irq_domain *domain,
++				      unsigned int virq, unsigned int nr_irqs)
++{
++	struct irq_data *data = irq_domain_get_irq_data(domain, virq);
++	struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
++	unsigned int hwirq;
++
++	mutex_lock(&msi->bitmap_lock);
++
++	hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq);
++	bitmap_clear(msi->bitmap, hwirq, msi->nr_cpus);
++
++	mutex_unlock(&msi->bitmap_lock);
++
++	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
++}
++
++static const struct irq_domain_ops msi_domain_ops = {
++	.alloc = iproc_msi_irq_domain_alloc,
++	.free = iproc_msi_irq_domain_free,
++};
++
++static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head)
++{
++	u32 *msg, hwirq;
++	unsigned int offs;
++
++	offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32);
++	msg = (u32 *)(msi->eq_cpu + offs);
++	hwirq = *msg & IPROC_MSI_EQ_MASK;
++
++	/*
++	 * Since we have multiple hwirq mapped to a single MSI vector,
++	 * now we need to derive the hwirq at CPU0. It can then be used to
++	 * mapped back to virq
++	 */
++	return hwirq_to_canonical_hwirq(msi, hwirq);
++}
++
++static void iproc_msi_handler(struct irq_desc *desc)
++{
++	struct irq_chip *chip = irq_desc_get_chip(desc);
++	struct iproc_msi_grp *grp;
++	struct iproc_msi *msi;
++	struct iproc_pcie *pcie;
++	u32 eq, head, tail, nr_events;
++	unsigned long hwirq;
++	int virq;
++
++	chained_irq_enter(chip, desc);
++
++	grp = irq_desc_get_handler_data(desc);
++	msi = grp->msi;
++	pcie = msi->pcie;
++	eq = grp->eq;
++
++	/*
++	 * iProc MSI event queue is tracked by head and tail pointers. Head
++	 * pointer indicates the next entry (MSI data) to be consumed by SW in
++	 * the queue and needs to be updated by SW. iProc MSI core uses the
++	 * tail pointer as the next data insertion point
++	 *
++	 * Entries between head and tail pointers contain valid MSI data. MSI
++	 * data is guaranteed to be in the event queue memory before the tail
++	 * pointer is updated by the iProc MSI core
++	 */
++	head = iproc_msi_read_reg(msi, IPROC_MSI_EQ_HEAD,
++				  eq) & IPROC_MSI_EQ_MASK;
++	do {
++		tail = iproc_msi_read_reg(msi, IPROC_MSI_EQ_TAIL,
++					  eq) & IPROC_MSI_EQ_MASK;
++
++		/*
++		 * Figure out total number of events (MSI data) to be
++		 * processed
++		 */
++		nr_events = (tail < head) ?
++			(EQ_LEN - (head - tail)) : (tail - head);
++		if (!nr_events)
++			break;
++
++		/* process all outstanding events */
++		while (nr_events--) {
++			hwirq = decode_msi_hwirq(msi, eq, head);
++			virq = irq_find_mapping(msi->inner_domain, hwirq);
++			generic_handle_irq(virq);
++
++			head++;
++			head %= EQ_LEN;
++		}
++
++		/*
++		 * Now all outstanding events have been processed. Update the
++		 * head pointer
++		 */
++		iproc_msi_write_reg(msi, IPROC_MSI_EQ_HEAD, eq, head);
++
++		/*
++		 * Now go read the tail pointer again to see if there are new
++		 * oustanding events that came in during the above window
++		 */
++	} while (true);
++
++	chained_irq_exit(chip, desc);
++}
++
++static void iproc_msi_enable(struct iproc_msi *msi)
++{
++	int i, eq;
++	u32 val;
++
++	/* program memory region for each event queue */
++	for (i = 0; i < msi->nr_eq_region; i++) {
++		dma_addr_t addr = msi->eq_dma + (i * EQ_MEM_REGION_SIZE);
++
++		iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE, i,
++				    lower_32_bits(addr));
++		iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE_UPPER, i,
++				    upper_32_bits(addr));
++	}
++
++	/* program address region for MSI posted writes */
++	for (i = 0; i < msi->nr_msi_region; i++) {
++		phys_addr_t addr = msi->msi_addr + (i * MSI_MEM_REGION_SIZE);
++
++		iproc_msi_write_reg(msi, IPROC_MSI_PAGE, i,
++				    lower_32_bits(addr));
++		iproc_msi_write_reg(msi, IPROC_MSI_PAGE_UPPER, i,
++				    upper_32_bits(addr));
++	}
++
++	for (eq = 0; eq < msi->nr_irqs; eq++) {
++		/* enable MSI event queue */
++		val = IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
++			IPROC_MSI_EQ_EN;
++		iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
++
++		/*
++		 * Some legacy platforms require the MSI interrupt enable
++		 * register to be set explicitly
++		 */
++		if (msi->has_inten_reg) {
++			val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
++			val |= BIT(eq);
++			iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
++		}
++	}
++}
++
++static void iproc_msi_disable(struct iproc_msi *msi)
++{
++	u32 eq, val;
++
++	for (eq = 0; eq < msi->nr_irqs; eq++) {
++		if (msi->has_inten_reg) {
++			val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
++			val &= ~BIT(eq);
++			iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
++		}
++
++		val = iproc_msi_read_reg(msi, IPROC_MSI_CTRL, eq);
++		val &= ~(IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
++			 IPROC_MSI_EQ_EN);
++		iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
++	}
++}
++
++static int iproc_msi_alloc_domains(struct device_node *node,
++				   struct iproc_msi *msi)
++{
++	msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_msi_vecs,
++						  &msi_domain_ops, msi);
++	if (!msi->inner_domain)
++		return -ENOMEM;
++
++	msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
++						    &iproc_msi_domain_info,
++						    msi->inner_domain);
++	if (!msi->msi_domain) {
++		irq_domain_remove(msi->inner_domain);
++		return -ENOMEM;
++	}
++
++	return 0;
++}
++
++static void iproc_msi_free_domains(struct iproc_msi *msi)
++{
++	if (msi->msi_domain)
++		irq_domain_remove(msi->msi_domain);
++
++	if (msi->inner_domain)
++		irq_domain_remove(msi->inner_domain);
++}
++
++static void iproc_msi_irq_free(struct iproc_msi *msi, unsigned int cpu)
++{
++	int i;
++
++	for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
++		irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
++						 NULL, NULL);
++	}
++}
++
++static int iproc_msi_irq_setup(struct iproc_msi *msi, unsigned int cpu)
++{
++	int i, ret;
++	cpumask_var_t mask;
++	struct iproc_pcie *pcie = msi->pcie;
++
++	for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
++		irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
++						 iproc_msi_handler,
++						 &msi->grps[i]);
++		/* dedicate GIC interrupt to each CPU core */
++		if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
++			cpumask_clear(mask);
++			cpumask_set_cpu(cpu, mask);
++			ret = irq_set_affinity(msi->grps[i].gic_irq, mask);
++			if (ret)
++				dev_err(pcie->dev,
++					"failed to set affinity for IRQ%d\n",
++					msi->grps[i].gic_irq);
++			free_cpumask_var(mask);
++		} else {
++			dev_err(pcie->dev, "failed to alloc CPU mask\n");
++			ret = -EINVAL;
++		}
++
++		if (ret) {
++			/* free all configured/unconfigured irqs */
++			iproc_msi_irq_free(msi, cpu);
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node)
++{
++	struct iproc_msi *msi;
++	int i, ret;
++	unsigned int cpu;
++
++	if (!of_device_is_compatible(node, "brcm,iproc-msi"))
++		return -ENODEV;
++
++	if (!of_find_property(node, "msi-controller", NULL))
++		return -ENODEV;
++
++	if (pcie->msi)
++		return -EBUSY;
++
++	msi = devm_kzalloc(pcie->dev, sizeof(*msi), GFP_KERNEL);
++	if (!msi)
++		return -ENOMEM;
++
++	msi->pcie = pcie;
++	pcie->msi = msi;
++	msi->msi_addr = pcie->base_addr;
++	mutex_init(&msi->bitmap_lock);
++	msi->nr_cpus = num_possible_cpus();
++
++	msi->nr_irqs = of_irq_count(node);
++	if (!msi->nr_irqs) {
++		dev_err(pcie->dev, "found no MSI GIC interrupt\n");
++		return -ENODEV;
++	}
++
++	if (msi->nr_irqs > NR_HW_IRQS) {
++		dev_warn(pcie->dev, "too many MSI GIC interrupts defined %d\n",
++			 msi->nr_irqs);
++		msi->nr_irqs = NR_HW_IRQS;
++	}
++
++	if (msi->nr_irqs < msi->nr_cpus) {
++		dev_err(pcie->dev,
++			"not enough GIC interrupts for MSI affinity\n");
++		return -EINVAL;
++	}
++
++	if (msi->nr_irqs % msi->nr_cpus != 0) {
++		msi->nr_irqs -= msi->nr_irqs % msi->nr_cpus;
++		dev_warn(pcie->dev, "Reducing number of interrupts to %d\n",
++			 msi->nr_irqs);
++	}
++
++	switch (pcie->type) {
++	case IPROC_PCIE_PAXB:
++		msi->reg_offsets = iproc_msi_reg_paxb;
++		msi->nr_eq_region = 1;
++		msi->nr_msi_region = 1;
++		break;
++	case IPROC_PCIE_PAXC:
++		msi->reg_offsets = iproc_msi_reg_paxc;
++		msi->nr_eq_region = msi->nr_irqs;
++		msi->nr_msi_region = msi->nr_irqs;
++		break;
++	default:
++		dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
++		return -EINVAL;
++	}
++
++	if (of_find_property(node, "brcm,pcie-msi-inten", NULL))
++		msi->has_inten_reg = true;
++
++	msi->nr_msi_vecs = msi->nr_irqs * EQ_LEN;
++	msi->bitmap = devm_kcalloc(pcie->dev, BITS_TO_LONGS(msi->nr_msi_vecs),
++				   sizeof(*msi->bitmap), GFP_KERNEL);
++	if (!msi->bitmap)
++		return -ENOMEM;
++
++	msi->grps = devm_kcalloc(pcie->dev, msi->nr_irqs, sizeof(*msi->grps),
++				 GFP_KERNEL);
++	if (!msi->grps)
++		return -ENOMEM;
++
++	for (i = 0; i < msi->nr_irqs; i++) {
++		unsigned int irq = irq_of_parse_and_map(node, i);
++
++		if (!irq) {
++			dev_err(pcie->dev, "unable to parse/map interrupt\n");
++			ret = -ENODEV;
++			goto free_irqs;
++		}
++		msi->grps[i].gic_irq = irq;
++		msi->grps[i].msi = msi;
++		msi->grps[i].eq = i;
++	}
++
++	/* reserve memory for event queue and make sure memories are zeroed */
++	msi->eq_cpu = dma_zalloc_coherent(pcie->dev,
++					  msi->nr_eq_region * EQ_MEM_REGION_SIZE,
++					  &msi->eq_dma, GFP_KERNEL);
++	if (!msi->eq_cpu) {
++		ret = -ENOMEM;
++		goto free_irqs;
++	}
++
++	ret = iproc_msi_alloc_domains(node, msi);
++	if (ret) {
++		dev_err(pcie->dev, "failed to create MSI domains\n");
++		goto free_eq_dma;
++	}
++
++	for_each_online_cpu(cpu) {
++		ret = iproc_msi_irq_setup(msi, cpu);
++		if (ret)
++			goto free_msi_irq;
++	}
++
++	iproc_msi_enable(msi);
++
++	return 0;
++
++free_msi_irq:
++	for_each_online_cpu(cpu)
++		iproc_msi_irq_free(msi, cpu);
++	iproc_msi_free_domains(msi);
++
++free_eq_dma:
++	dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
++			  msi->eq_cpu, msi->eq_dma);
++
++free_irqs:
++	for (i = 0; i < msi->nr_irqs; i++) {
++		if (msi->grps[i].gic_irq)
++			irq_dispose_mapping(msi->grps[i].gic_irq);
++	}
++	pcie->msi = NULL;
++	return ret;
++}
++EXPORT_SYMBOL(iproc_msi_init);
++
++void iproc_msi_exit(struct iproc_pcie *pcie)
++{
++	struct iproc_msi *msi = pcie->msi;
++	unsigned int i, cpu;
++
++	if (!msi)
++		return;
++
++	iproc_msi_disable(msi);
++
++	for_each_online_cpu(cpu)
++		iproc_msi_irq_free(msi, cpu);
++
++	iproc_msi_free_domains(msi);
++
++	dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
++			  msi->eq_cpu, msi->eq_dma);
++
++	for (i = 0; i < msi->nr_irqs; i++) {
++		if (msi->grps[i].gic_irq)
++			irq_dispose_mapping(msi->grps[i].gic_irq);
++	}
++}
++EXPORT_SYMBOL(iproc_msi_exit);
+--- a/drivers/pci/host/pcie-iproc-platform.c
++++ b/drivers/pci/host/pcie-iproc-platform.c
+@@ -71,6 +71,7 @@ static int iproc_pcie_pltfm_probe(struct
+ 		dev_err(pcie->dev, "unable to map controller registers\n");
+ 		return -ENOMEM;
+ 	}
++	pcie->base_addr = reg.start;
+ 
+ 	if (of_property_read_bool(np, "brcm,pcie-ob")) {
+ 		u32 val;
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -440,6 +440,26 @@ static int iproc_pcie_map_ranges(struct
+ 	return 0;
+ }
+ 
++static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
++{
++	struct device_node *msi_node;
++
++	msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
++	if (!msi_node)
++		return -ENODEV;
++
++	/*
++	 * If another MSI controller is being used, the call below should fail
++	 * but that is okay
++	 */
++	return iproc_msi_init(pcie, msi_node);
++}
++
++static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
++{
++	iproc_msi_exit(pcie);
++}
++
+ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
+ {
+ 	int ret;
+@@ -506,6 +526,10 @@ int iproc_pcie_setup(struct iproc_pcie *
+ 
+ 	iproc_pcie_enable(pcie);
+ 
++	if (IS_ENABLED(CONFIG_PCI_MSI))
++		if (iproc_pcie_msi_enable(pcie))
++			dev_info(pcie->dev, "not using iProc MSI\n");
++
+ 	pci_scan_child_bus(bus);
+ 	pci_assign_unassigned_bus_resources(bus);
+ 	pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
+@@ -530,6 +554,8 @@ int iproc_pcie_remove(struct iproc_pcie
+ 	pci_stop_root_bus(pcie->root_bus);
+ 	pci_remove_root_bus(pcie->root_bus);
+ 
++	iproc_pcie_msi_disable(pcie);
++
+ 	phy_power_off(pcie->phy);
+ 	phy_exit(pcie->phy);
+ 
+--- a/drivers/pci/host/pcie-iproc.h
++++ b/drivers/pci/host/pcie-iproc.h
+@@ -41,6 +41,8 @@ struct iproc_pcie_ob {
+ 	resource_size_t window_size;
+ };
+ 
++struct iproc_msi;
++
+ /**
+  * iProc PCIe device
+  *
+@@ -48,19 +50,21 @@ struct iproc_pcie_ob {
+  * @type: iProc PCIe interface type
+  * @reg_offsets: register offsets
+  * @base: PCIe host controller I/O register base
++ * @base_addr: PCIe host controller register base physical address
+  * @sysdata: Per PCI controller data (ARM-specific)
+  * @root_bus: pointer to root bus
+  * @phy: optional PHY device that controls the Serdes
+- * @irqs: interrupt IDs
+  * @map_irq: function callback to map interrupts
+- * @need_ob_cfg: indidates SW needs to configure the outbound mapping window
++ * @need_ob_cfg: indicates SW needs to configure the outbound mapping window
+  * @ob: outbound mapping parameters
++ * @msi: MSI data
+  */
+ struct iproc_pcie {
+ 	struct device *dev;
+ 	enum iproc_pcie_type type;
+ 	const u16 *reg_offsets;
+ 	void __iomem *base;
++	phys_addr_t base_addr;
+ #ifdef CONFIG_ARM
+ 	struct pci_sys_data sysdata;
+ #endif
+@@ -69,9 +73,24 @@ struct iproc_pcie {
+ 	int (*map_irq)(const struct pci_dev *, u8, u8);
+ 	bool need_ob_cfg;
+ 	struct iproc_pcie_ob ob;
++	struct iproc_msi *msi;
+ };
+ 
+ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res);
+ int iproc_pcie_remove(struct iproc_pcie *pcie);
+ 
++#ifdef CONFIG_PCI_MSI
++int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node);
++void iproc_msi_exit(struct iproc_pcie *pcie);
++#else
++static inline int iproc_msi_init(struct iproc_pcie *pcie,
++				 struct device_node *node)
++{
++	return -ENODEV;
++}
++static void iproc_msi_exit(struct iproc_pcie *pcie)
++{
++}
++#endif
++
+ #endif /* _PCIE_IPROC_H */

target/linux/bcm53xx/patches-4.3/140-PCI-iproc-Fix-code-comment-to-match-code.patch

@@ -0,0 +1,28 @@
+From 5d92f41c48c5e3c6fa5be87e3d6fca57e2fbb127 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 15 Sep 2015 17:39:15 -0700
+Subject: [PATCH 140/147] PCI: iproc: Fix code comment to match code
+
+Fix code comment in pcie-iproc.h so it matches the code.
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ drivers/pci/host/pcie-iproc.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pci/host/pcie-iproc.h
++++ b/drivers/pci/host/pcie-iproc.h
+@@ -20,11 +20,11 @@
+  * iProc PCIe device
+  * @dev: pointer to device data structure
+  * @base: PCIe host controller I/O register base
+- * @resources: linked list of all PCI resources
+  * @sysdata: Per PCI controller data (ARM-specific)
+  * @root_bus: pointer to root bus
+  * @phy: optional PHY device that controls the Serdes
+  * @irqs: interrupt IDs
++ * @map_irq: function callback to map interrupts
+  */
+ struct iproc_pcie {
+ 	struct device *dev;

target/linux/bcm53xx/patches-4.3/141-PCI-iproc-Remove-unused-struct-iproc_pcie.irqs.patch

@@ -0,0 +1,33 @@
+From 98aac697a83db6e1d004e5d61cf6c976a0b1c35a Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 15 Sep 2015 17:39:16 -0700
+Subject: [PATCH 141/147] PCI: iproc: Remove unused struct iproc_pcie.irqs[]
+
+Remove unused struct iproc_pcie member irqs[] and unused #define
+IPROC_PCIE_MAX_NUM_IRQS.
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ drivers/pci/host/pcie-iproc.h | 3 ---
+ 1 file changed, 3 deletions(-)
+
+--- a/drivers/pci/host/pcie-iproc.h
++++ b/drivers/pci/host/pcie-iproc.h
+@@ -14,8 +14,6 @@
+ #ifndef _PCIE_IPROC_H
+ #define _PCIE_IPROC_H
+ 
+-#define IPROC_PCIE_MAX_NUM_IRQS 6
+-
+ /**
+  * iProc PCIe device
+  * @dev: pointer to device data structure
+@@ -34,7 +32,6 @@ struct iproc_pcie {
+ #endif
+ 	struct pci_bus *root_bus;
+ 	struct phy *phy;
+-	int irqs[IPROC_PCIE_MAX_NUM_IRQS];
+ 	int (*map_irq)(const struct pci_dev *, u8, u8);
+ };
+ 

target/linux/bcm53xx/patches-4.3/142-PCI-iproc-Call-pci_fixup_irqs-for-ARM64-as-well-as-A.patch

@@ -0,0 +1,31 @@
+From bdb8a1844f3113ec08915d1e8e3fd5686fb2fb78 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 15 Sep 2015 17:39:17 -0700
+Subject: [PATCH 142/147] PCI: iproc: Call pci_fixup_irqs() for ARM64 as well
+ as ARM
+
+After 459a07721c11 ("PCI: Build setup-irq.o for arm64"), we build
+setup-irq.o for arm64, so we can use pci_fixup_irqs() on both arm and
+arm64.
+
+Remove the "#ifdef CONFIG_ARM" around the call to pci_fixup_irqs().
+
+[bhelgaas: changelog]
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ drivers/pci/host/pcie-iproc.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -238,9 +238,7 @@ int iproc_pcie_setup(struct iproc_pcie *
+ 
+ 	pci_scan_child_bus(bus);
+ 	pci_assign_unassigned_bus_resources(bus);
+-#ifdef CONFIG_ARM
+ 	pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
+-#endif
+ 	pci_bus_add_devices(bus);
+ 
+ 	return 0;

target/linux/bcm53xx/patches-4.3/143-PCI-iproc-Fix-PCIe-reset-logic.patch

@@ -0,0 +1,62 @@
+From 199ff14100095d52cd1b232cc0f3b12f348b5b07 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 15 Sep 2015 17:39:18 -0700
+Subject: [PATCH 143/147] PCI: iproc: Fix PCIe reset logic
+
+The current reset logic does not always properly reset the device.  For
+example, in the case when the perst_b signal is already de-asserted in the
+bootloader, the current reset logic fails to trigger a proper assert ->
+de-assert reset sequence.
+
+Fix the issue by always triggering the proper reset sequence.
+
+Also explicitly select the desired reset source, i.e., perst_b, and reduce
+the wait time after the device comes out of reset from 250 ms to 100 ms,
+based on recommendation from the ASIC team.
+
+Tested-by: Vladimir Dreizin <vdreizin@broadcom.com>
+Tested-by: Darren Edamura <dedamura@broadcom.com>
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Vladimir Dreizin <vdreizin@broadcom.com>
+Reviewed-by: Trac Hoang <trhoang@broadcom.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+---
+ drivers/pci/host/pcie-iproc.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -31,6 +31,8 @@
+ #include "pcie-iproc.h"
+ 
+ #define CLK_CONTROL_OFFSET           0x000
++#define EP_PERST_SOURCE_SELECT_SHIFT 2
++#define EP_PERST_SOURCE_SELECT       BIT(EP_PERST_SOURCE_SELECT_SHIFT)
+ #define EP_MODE_SURVIVE_PERST_SHIFT  1
+ #define EP_MODE_SURVIVE_PERST        BIT(EP_MODE_SURVIVE_PERST_SHIFT)
+ #define RC_PCIE_RST_OUTPUT_SHIFT     0
+@@ -119,15 +121,18 @@ static void iproc_pcie_reset(struct ipro
+ 	u32 val;
+ 
+ 	/*
+-	 * Configure the PCIe controller as root complex and send a downstream
+-	 * reset
++	 * Select perst_b signal as reset source. Put the device into reset,
++	 * and then bring it out of reset
+ 	 */
+-	val = EP_MODE_SURVIVE_PERST | RC_PCIE_RST_OUTPUT;
++	val = readl(pcie->base + CLK_CONTROL_OFFSET);
++	val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
++		~RC_PCIE_RST_OUTPUT;
+ 	writel(val, pcie->base + CLK_CONTROL_OFFSET);
+ 	udelay(250);
+-	val &= ~EP_MODE_SURVIVE_PERST;
++
++	val |= RC_PCIE_RST_OUTPUT;
+ 	writel(val, pcie->base + CLK_CONTROL_OFFSET);
+-	msleep(250);
++	msleep(100);
+ }
+ 
+ static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)

target/linux/bcm53xx/patches-4.3/144-PCI-iproc-Improve-link-detection-logic.patch

@@ -0,0 +1,84 @@
+From aaf22ab4e916afa68a2e1aed4e913b76cbd58276 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 15 Sep 2015 17:39:19 -0700
+Subject: [PATCH 144/147] PCI: iproc: Improve link detection logic
+
+Improve the link detection logic by explicitly querying the link status
+register to ensure link is active.
+
+Also force class to PCI_CLASS_BRIDGE_PCI (0x0604) through the host
+configuration space register.
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Reviewed-by: Anup Patel <anup.patel@broadcom.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+---
+ drivers/pci/host/pcie-iproc.c | 29 +++++++++++++++++++++++------
+ 1 file changed, 23 insertions(+), 6 deletions(-)
+
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -60,6 +60,12 @@
+ #define SYS_RC_INTX_EN               0x330
+ #define SYS_RC_INTX_MASK             0xf
+ 
++#define PCIE_LINK_STATUS_OFFSET      0xf0c
++#define PCIE_PHYLINKUP_SHIFT         3
++#define PCIE_PHYLINKUP               BIT(PCIE_PHYLINKUP_SHIFT)
++#define PCIE_DL_ACTIVE_SHIFT         2
++#define PCIE_DL_ACTIVE               BIT(PCIE_DL_ACTIVE_SHIFT)
++
+ static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
+ {
+ 	struct iproc_pcie *pcie;
+@@ -138,9 +144,15 @@ static void iproc_pcie_reset(struct ipro
+ static int iproc_pcie_check_link(struct iproc_pcie *pcie, struct pci_bus *bus)
+ {
+ 	u8 hdr_type;
+-	u32 link_ctrl;
++	u32 link_ctrl, class, val;
+ 	u16 pos, link_status;
+-	int link_is_active = 0;
++	bool link_is_active = false;
++
++	val = readl(pcie->base + PCIE_LINK_STATUS_OFFSET);
++	if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
++		dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
++		return -ENODEV;
++	}
+ 
+ 	/* make sure we are not in EP mode */
+ 	pci_bus_read_config_byte(bus, 0, PCI_HEADER_TYPE, &hdr_type);
+@@ -150,14 +162,19 @@ static int iproc_pcie_check_link(struct
+ 	}
+ 
+ 	/* force class to PCI_CLASS_BRIDGE_PCI (0x0604) */
+-	pci_bus_write_config_word(bus, 0, PCI_CLASS_DEVICE,
+-				  PCI_CLASS_BRIDGE_PCI);
++#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
++#define PCI_CLASS_BRIDGE_MASK      0xffff00
++#define PCI_CLASS_BRIDGE_SHIFT     8
++	pci_bus_read_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, &class);
++	class &= ~PCI_CLASS_BRIDGE_MASK;
++	class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
++	pci_bus_write_config_dword(bus, 0, PCI_BRIDGE_CTRL_REG_OFFSET, class);
+ 
+ 	/* check link status to see if link is active */
+ 	pos = pci_bus_find_capability(bus, 0, PCI_CAP_ID_EXP);
+ 	pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA, &link_status);
+ 	if (link_status & PCI_EXP_LNKSTA_NLW)
+-		link_is_active = 1;
++		link_is_active = true;
+ 
+ 	if (!link_is_active) {
+ 		/* try GEN 1 link speed */
+@@ -181,7 +198,7 @@ static int iproc_pcie_check_link(struct
+ 			pci_bus_read_config_word(bus, 0, pos + PCI_EXP_LNKSTA,
+ 						 &link_status);
+ 			if (link_status & PCI_EXP_LNKSTA_NLW)
+-				link_is_active = 1;
++				link_is_active = true;
+ 		}
+ 	}
+ 

target/linux/bcm53xx/patches-4.3/145-PCI-iproc-Update-PCIe-device-tree-bindings.patch

@@ -0,0 +1,50 @@
+From 8d0afa1a93be2da954c85392bbc7b2264c9d241c Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 15 Sep 2015 17:39:20 -0700
+Subject: [PATCH 145/147] PCI: iproc: Update PCIe device tree bindings
+
+Update the device tree bindings with added support for outbound mapping
+configurations.
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ .../devicetree/bindings/pci/brcm,iproc-pcie.txt      | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
++++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
+@@ -17,6 +17,21 @@ Optional properties:
+ - phys: phandle of the PCIe PHY device
+ - phy-names: must be "pcie-phy"
+ 
++- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done
++by the ASIC after power on reset. In this case, SW needs to configure it
++
++If the brcm,pcie-ob property is present, the following properties become
++effective:
++
++Required:
++- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal
++address used by the iProc PCIe core (not the PCIe address)
++- brcm,pcie-ob-window-size: The outbound address mapping window size (in MB)
++
++Optional:
++- brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
++increase the outbound window size
++
+ Example:
+ 	pcie0: pcie@18012000 {
+ 		compatible = "brcm,iproc-pcie";
+@@ -38,6 +53,11 @@ Example:
+ 
+ 		phys = <&phy 0 5>;
+ 		phy-names = "pcie-phy";
++
++		brcm,pcie-ob;
++		brcm,pcie-ob-oarr-size;
++		brcm,pcie-ob-axi-offset = <0x00000000>;
++		brcm,pcie-ob-window-size = <256>;
+ 	};
+ 
+ 	pcie1: pcie@18013000 {

target/linux/bcm53xx/patches-4.3/146-PCI-iproc-Add-outbound-mapping-support.patch

@@ -0,0 +1,236 @@
+From e99a187b5c5f60fe55ca586f82ac1a3557fb166a Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Fri, 16 Oct 2015 08:18:24 -0500
+Subject: [PATCH 146/147] PCI: iproc: Add outbound mapping support
+
+Certain SoCs require the PCIe outbound mapping to be configured in
+software.  Add support for those chips.
+
+[jonmason: Use %pap format when printing size_t to avoid warnings in 32-bit
+build.]
+[arnd: Use div64_u64() instead of "%" to avoid __aeabi_uldivmod link error
+in 32-bit build.]
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Signed-off-by: Jon Mason <jonmason@broadcom.com>
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+---
+ drivers/pci/host/pcie-iproc-platform.c |  27 ++++++++
+ drivers/pci/host/pcie-iproc.c          | 115 +++++++++++++++++++++++++++++++++
+ drivers/pci/host/pcie-iproc.h          |  17 +++++
+ 3 files changed, 159 insertions(+)
+
+--- a/drivers/pci/host/pcie-iproc-platform.c
++++ b/drivers/pci/host/pcie-iproc-platform.c
+@@ -54,6 +54,33 @@ static int iproc_pcie_pltfm_probe(struct
+ 		return -ENOMEM;
+ 	}
+ 
++	if (of_property_read_bool(np, "brcm,pcie-ob")) {
++		u32 val;
++
++		ret = of_property_read_u32(np, "brcm,pcie-ob-axi-offset",
++					   &val);
++		if (ret) {
++			dev_err(pcie->dev,
++				"missing brcm,pcie-ob-axi-offset property\n");
++			return ret;
++		}
++		pcie->ob.axi_offset = val;
++
++		ret = of_property_read_u32(np, "brcm,pcie-ob-window-size",
++					   &val);
++		if (ret) {
++			dev_err(pcie->dev,
++				"missing brcm,pcie-ob-window-size property\n");
++			return ret;
++		}
++		pcie->ob.window_size = (resource_size_t)val * SZ_1M;
++
++		if (of_property_read_bool(np, "brcm,pcie-ob-oarr-size"))
++			pcie->ob.set_oarr_size = true;
++
++		pcie->need_ob_cfg = true;
++	}
++
+ 	/* PHY use is optional */
+ 	pcie->phy = devm_phy_get(&pdev->dev, "pcie-phy");
+ 	if (IS_ERR(pcie->phy)) {
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -66,6 +66,18 @@
+ #define PCIE_DL_ACTIVE_SHIFT         2
+ #define PCIE_DL_ACTIVE               BIT(PCIE_DL_ACTIVE_SHIFT)
+ 
++#define OARR_VALID_SHIFT             0
++#define OARR_VALID                   BIT(OARR_VALID_SHIFT)
++#define OARR_SIZE_CFG_SHIFT          1
++#define OARR_SIZE_CFG                BIT(OARR_SIZE_CFG_SHIFT)
++
++#define OARR_LO(window)              (0xd20 + (window) * 8)
++#define OARR_HI(window)              (0xd24 + (window) * 8)
++#define OMAP_LO(window)              (0xd40 + (window) * 8)
++#define OMAP_HI(window)              (0xd44 + (window) * 8)
++
++#define MAX_NUM_OB_WINDOWS           2
++
+ static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
+ {
+ 	struct iproc_pcie *pcie;
+@@ -212,6 +224,101 @@ static void iproc_pcie_enable(struct ipr
+ 	writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
+ }
+ 
++/**
++ * Some iProc SoCs require the SW to configure the outbound address mapping
++ *
++ * Outbound address translation:
++ *
++ * iproc_pcie_address = axi_address - axi_offset
++ * OARR = iproc_pcie_address
++ * OMAP = pci_addr
++ *
++ * axi_addr -> iproc_pcie_address -> OARR -> OMAP -> pci_address
++ */
++static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
++			       u64 pci_addr, resource_size_t size)
++{
++	struct iproc_pcie_ob *ob = &pcie->ob;
++	unsigned i;
++	u64 max_size = (u64)ob->window_size * MAX_NUM_OB_WINDOWS;
++	u64 remainder;
++
++	if (size > max_size) {
++		dev_err(pcie->dev,
++			"res size 0x%pap exceeds max supported size 0x%llx\n",
++			&size, max_size);
++		return -EINVAL;
++	}
++
++	div64_u64_rem(size, ob->window_size, &remainder);
++	if (remainder) {
++		dev_err(pcie->dev,
++			"res size %pap needs to be multiple of window size %pap\n",
++			&size, &ob->window_size);
++		return -EINVAL;
++	}
++
++	if (axi_addr < ob->axi_offset) {
++		dev_err(pcie->dev,
++			"axi address %pap less than offset %pap\n",
++			&axi_addr, &ob->axi_offset);
++		return -EINVAL;
++	}
++
++	/*
++	 * Translate the AXI address to the internal address used by the iProc
++	 * PCIe core before programming the OARR
++	 */
++	axi_addr -= ob->axi_offset;
++
++	for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) {
++		writel(lower_32_bits(axi_addr) | OARR_VALID |
++		       (ob->set_oarr_size ? 1 : 0), pcie->base + OARR_LO(i));
++		writel(upper_32_bits(axi_addr), pcie->base + OARR_HI(i));
++		writel(lower_32_bits(pci_addr), pcie->base + OMAP_LO(i));
++		writel(upper_32_bits(pci_addr), pcie->base + OMAP_HI(i));
++
++		size -= ob->window_size;
++		if (size == 0)
++			break;
++
++		axi_addr += ob->window_size;
++		pci_addr += ob->window_size;
++	}
++
++	return 0;
++}
++
++static int iproc_pcie_map_ranges(struct iproc_pcie *pcie,
++				 struct list_head *resources)
++{
++	struct resource_entry *window;
++	int ret;
++
++	resource_list_for_each_entry(window, resources) {
++		struct resource *res = window->res;
++		u64 res_type = resource_type(res);
++
++		switch (res_type) {
++		case IORESOURCE_IO:
++		case IORESOURCE_BUS:
++			break;
++		case IORESOURCE_MEM:
++			ret = iproc_pcie_setup_ob(pcie, res->start,
++						  res->start - window->offset,
++						  resource_size(res));
++			if (ret)
++				return ret;
++			break;
++		default:
++			dev_err(pcie->dev, "invalid resource %pR\n", res);
++			return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
+ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
+ {
+ 	int ret;
+@@ -235,6 +342,14 @@ int iproc_pcie_setup(struct iproc_pcie *
+ 
+ 	iproc_pcie_reset(pcie);
+ 
++	if (pcie->need_ob_cfg) {
++		ret = iproc_pcie_map_ranges(pcie, res);
++		if (ret) {
++			dev_err(pcie->dev, "map failed\n");
++			goto err_power_off_phy;
++		}
++	}
++
+ #ifdef CONFIG_ARM
+ 	pcie->sysdata.private_data = pcie;
+ 	sysdata = &pcie->sysdata;
+--- a/drivers/pci/host/pcie-iproc.h
++++ b/drivers/pci/host/pcie-iproc.h
+@@ -15,6 +15,19 @@
+ #define _PCIE_IPROC_H
+ 
+ /**
++ * iProc PCIe outbound mapping
++ * @set_oarr_size: indicates the OARR size bit needs to be set
++ * @axi_offset: offset from the AXI address to the internal address used by
++ * the iProc PCIe core
++ * @window_size: outbound window size
++ */
++struct iproc_pcie_ob {
++	bool set_oarr_size;
++	resource_size_t axi_offset;
++	resource_size_t window_size;
++};
++
++/**
+  * iProc PCIe device
+  * @dev: pointer to device data structure
+  * @base: PCIe host controller I/O register base
+@@ -23,6 +36,8 @@
+  * @phy: optional PHY device that controls the Serdes
+  * @irqs: interrupt IDs
+  * @map_irq: function callback to map interrupts
++ * @need_ob_cfg: indidates SW needs to configure the outbound mapping window
++ * @ob: outbound mapping parameters
+  */
+ struct iproc_pcie {
+ 	struct device *dev;
+@@ -33,6 +48,8 @@ struct iproc_pcie {
+ 	struct pci_bus *root_bus;
+ 	struct phy *phy;
+ 	int (*map_irq)(const struct pci_dev *, u8, u8);
++	bool need_ob_cfg;
++	struct iproc_pcie_ob ob;
+ };
+ 
+ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res);

target/linux/bcm53xx/patches-4.3/147-PCI-iproc-Fix-header-comment-Corporation-misspelling.patch

@@ -0,0 +1,25 @@
+From be908d21b2e9c2cab1ef568dfca4f9777611b3dd Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <f.fainelli@gmail.com>
+Date: Fri, 16 Oct 2015 12:04:04 -0700
+Subject: [PATCH 147/147] PCI: iproc: Fix header comment "Corporation"
+ misspelling
+
+Fix an obvious "Broadcom Corporation" typo in a header comment.
+
+Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Ray Jui <rjui@broadcom.com>
+---
+ drivers/pci/host/pcie-iproc.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -1,6 +1,6 @@
+ /*
+  * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
+- * Copyright (C) 2015 Broadcom Corporatcommon ion
++ * Copyright (C) 2015 Broadcom Corporation
+  *
+  * This program is free software; you can redistribute it and/or
+  * modify it under the terms of the GNU General Public License as

target/linux/bcm53xx/patches-4.3/150-PCI-iproc-Update-iProc-PCIe-device-tree-binding.patch

@@ -0,0 +1,29 @@
+From d85a955118c8d8679d4f746fe2189c172d7c365f Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Mon, 16 Nov 2015 17:18:05 -0800
+Subject: [PATCH 150/154] PCI: iproc: Update iProc PCIe device tree binding
+
+Add a new compatible string "brcm,iproc-pcie-paxc", for PAXC based iProc
+PCIe root complex. A PAXC based PCIe root complex is connected to
+emulated endpoint devices internal to the ASIC
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+---
+ Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
++++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
+@@ -1,7 +1,10 @@
+ * Broadcom iProc PCIe controller with the platform bus interface
+ 
+ Required properties:
+-- compatible: Must be "brcm,iproc-pcie"
++- compatible: Must be "brcm,iproc-pcie" for PAXB, or "brcm,iproc-pcie-paxc"
++  for PAXC. PAXB based root complex is used for external endpoint devices.
++  PAXC based root complex is connected to emulated endpoint devices
++  internal to the ASIC
+ - reg: base address and length of the PCIe controller I/O register space
+ - #interrupt-cells: set to <1>
+ - interrupt-map-mask and interrupt-map, standard PCI properties to define the

target/linux/bcm53xx/patches-4.3/151-PCI-iproc-Add-PAXC-interface-support.patch

@@ -0,0 +1,428 @@
+From a13fc4733b25d6dad6ec1826f09225c69ee21e3a Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Mon, 16 Nov 2015 17:41:43 -0800
+Subject: [PATCH 151/154] PCI: iproc: Add PAXC interface support
+
+Traditionally, all iProc PCIe root complexes use PAXB based wrapper,
+with an integrated on-chip Serdes to support external endpoint devices.
+On newer iProc platforms, a PAXC based wrapper is introduced, for
+connection with internally emulated PCIe endpoint devices in the ASIC
+
+This patch adds support for PAXC based iProc PCIe root complex in the
+iProc PCIe core driver. This change fators out common logic between
+PAXB and PAXC, and use tables to store register offsets that are
+different between PAXB and PAXC. This allows the driver to be scaled to
+support subsequent PAXC revisions in the future
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+---
+ drivers/pci/host/pcie-iproc-platform.c |  24 +++-
+ drivers/pci/host/pcie-iproc.c          | 202 +++++++++++++++++++++++++++------
+ drivers/pci/host/pcie-iproc.h          |  19 ++++
+ 3 files changed, 205 insertions(+), 40 deletions(-)
+
+--- a/drivers/pci/host/pcie-iproc-platform.c
++++ b/drivers/pci/host/pcie-iproc-platform.c
+@@ -26,8 +26,21 @@
+ 
+ #include "pcie-iproc.h"
+ 
++static const struct of_device_id iproc_pcie_of_match_table[] = {
++	{
++		.compatible = "brcm,iproc-pcie",
++		.data = (int *)IPROC_PCIE_PAXB,
++	}, {
++		.compatible = "brcm,iproc-pcie-paxc",
++		.data = (int *)IPROC_PCIE_PAXC,
++	},
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
++
+ static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
+ {
++	const struct of_device_id *of_id;
+ 	struct iproc_pcie *pcie;
+ 	struct device_node *np = pdev->dev.of_node;
+ 	struct resource reg;
+@@ -35,11 +48,16 @@ static int iproc_pcie_pltfm_probe(struct
+ 	LIST_HEAD(res);
+ 	int ret;
+ 
++	of_id = of_match_device(iproc_pcie_of_match_table, &pdev->dev);
++	if (!of_id)
++		return -EINVAL;
++
+ 	pcie = devm_kzalloc(&pdev->dev, sizeof(struct iproc_pcie), GFP_KERNEL);
+ 	if (!pcie)
+ 		return -ENOMEM;
+ 
+ 	pcie->dev = &pdev->dev;
++	pcie->type = (enum iproc_pcie_type)of_id->data;
+ 	platform_set_drvdata(pdev, pcie);
+ 
+ 	ret = of_address_to_resource(np, 0, &reg);
+@@ -114,12 +132,6 @@ static int iproc_pcie_pltfm_remove(struc
+ 	return iproc_pcie_remove(pcie);
+ }
+ 
+-static const struct of_device_id iproc_pcie_of_match_table[] = {
+-	{ .compatible = "brcm,iproc-pcie", },
+-	{ /* sentinel */ }
+-};
+-MODULE_DEVICE_TABLE(of, iproc_pcie_of_match_table);
+-
+ static struct platform_driver iproc_pcie_pltfm_driver = {
+ 	.driver = {
+ 		.name = "iproc-pcie",
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -30,20 +30,16 @@
+ 
+ #include "pcie-iproc.h"
+ 
+-#define CLK_CONTROL_OFFSET           0x000
+ #define EP_PERST_SOURCE_SELECT_SHIFT 2
+ #define EP_PERST_SOURCE_SELECT       BIT(EP_PERST_SOURCE_SELECT_SHIFT)
+ #define EP_MODE_SURVIVE_PERST_SHIFT  1
+ #define EP_MODE_SURVIVE_PERST        BIT(EP_MODE_SURVIVE_PERST_SHIFT)
+ #define RC_PCIE_RST_OUTPUT_SHIFT     0
+ #define RC_PCIE_RST_OUTPUT           BIT(RC_PCIE_RST_OUTPUT_SHIFT)
++#define PAXC_RESET_MASK              0x7f
+ 
+-#define CFG_IND_ADDR_OFFSET          0x120
+ #define CFG_IND_ADDR_MASK            0x00001ffc
+ 
+-#define CFG_IND_DATA_OFFSET          0x124
+-
+-#define CFG_ADDR_OFFSET              0x1f8
+ #define CFG_ADDR_BUS_NUM_SHIFT       20
+ #define CFG_ADDR_BUS_NUM_MASK        0x0ff00000
+ #define CFG_ADDR_DEV_NUM_SHIFT       15
+@@ -55,12 +51,8 @@
+ #define CFG_ADDR_CFG_TYPE_SHIFT      0
+ #define CFG_ADDR_CFG_TYPE_MASK       0x00000003
+ 
+-#define CFG_DATA_OFFSET              0x1fc
+-
+-#define SYS_RC_INTX_EN               0x330
+ #define SYS_RC_INTX_MASK             0xf
+ 
+-#define PCIE_LINK_STATUS_OFFSET      0xf0c
+ #define PCIE_PHYLINKUP_SHIFT         3
+ #define PCIE_PHYLINKUP               BIT(PCIE_PHYLINKUP_SHIFT)
+ #define PCIE_DL_ACTIVE_SHIFT         2
+@@ -71,12 +63,54 @@
+ #define OARR_SIZE_CFG_SHIFT          1
+ #define OARR_SIZE_CFG                BIT(OARR_SIZE_CFG_SHIFT)
+ 
+-#define OARR_LO(window)              (0xd20 + (window) * 8)
+-#define OARR_HI(window)              (0xd24 + (window) * 8)
+-#define OMAP_LO(window)              (0xd40 + (window) * 8)
+-#define OMAP_HI(window)              (0xd44 + (window) * 8)
+-
+ #define MAX_NUM_OB_WINDOWS           2
++#define MAX_NUM_PAXC_PF              4
++
++#define IPROC_PCIE_REG_INVALID 0xffff
++
++enum iproc_pcie_reg {
++	IPROC_PCIE_CLK_CTRL = 0,
++	IPROC_PCIE_CFG_IND_ADDR,
++	IPROC_PCIE_CFG_IND_DATA,
++	IPROC_PCIE_CFG_ADDR,
++	IPROC_PCIE_CFG_DATA,
++	IPROC_PCIE_INTX_EN,
++	IPROC_PCIE_OARR_LO,
++	IPROC_PCIE_OARR_HI,
++	IPROC_PCIE_OMAP_LO,
++	IPROC_PCIE_OMAP_HI,
++	IPROC_PCIE_LINK_STATUS,
++};
++
++/* iProc PCIe PAXB registers */
++static const u16 iproc_pcie_reg_paxb[] = {
++	[IPROC_PCIE_CLK_CTRL]     = 0x000,
++	[IPROC_PCIE_CFG_IND_ADDR] = 0x120,
++	[IPROC_PCIE_CFG_IND_DATA] = 0x124,
++	[IPROC_PCIE_CFG_ADDR]     = 0x1f8,
++	[IPROC_PCIE_CFG_DATA]     = 0x1fc,
++	[IPROC_PCIE_INTX_EN]      = 0x330,
++	[IPROC_PCIE_OARR_LO]      = 0xd20,
++	[IPROC_PCIE_OARR_HI]      = 0xd24,
++	[IPROC_PCIE_OMAP_LO]      = 0xd40,
++	[IPROC_PCIE_OMAP_HI]      = 0xd44,
++	[IPROC_PCIE_LINK_STATUS]  = 0xf0c,
++};
++
++/* iProc PCIe PAXC v1 registers */
++static const u16 iproc_pcie_reg_paxc[] = {
++	[IPROC_PCIE_CLK_CTRL]     = 0x000,
++	[IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
++	[IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
++	[IPROC_PCIE_CFG_ADDR]     = 0x1f8,
++	[IPROC_PCIE_CFG_DATA]     = 0x1fc,
++	[IPROC_PCIE_INTX_EN]      = IPROC_PCIE_REG_INVALID,
++	[IPROC_PCIE_OARR_LO]      = IPROC_PCIE_REG_INVALID,
++	[IPROC_PCIE_OARR_HI]      = IPROC_PCIE_REG_INVALID,
++	[IPROC_PCIE_OMAP_LO]      = IPROC_PCIE_REG_INVALID,
++	[IPROC_PCIE_OMAP_HI]      = IPROC_PCIE_REG_INVALID,
++	[IPROC_PCIE_LINK_STATUS]  = IPROC_PCIE_REG_INVALID,
++};
+ 
+ static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
+ {
+@@ -91,6 +125,65 @@ static inline struct iproc_pcie *iproc_d
+ 	return pcie;
+ }
+ 
++static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
++{
++	return !!(reg_offset == IPROC_PCIE_REG_INVALID);
++}
++
++static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
++					enum iproc_pcie_reg reg)
++{
++	return pcie->reg_offsets[reg];
++}
++
++static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
++				      enum iproc_pcie_reg reg)
++{
++	u16 offset = iproc_pcie_reg_offset(pcie, reg);
++
++	if (iproc_pcie_reg_is_invalid(offset))
++		return 0;
++
++	return readl(pcie->base + offset);
++}
++
++static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
++					enum iproc_pcie_reg reg, u32 val)
++{
++	u16 offset = iproc_pcie_reg_offset(pcie, reg);
++
++	if (iproc_pcie_reg_is_invalid(offset))
++		return;
++
++	writel(val, pcie->base + offset);
++}
++
++static inline void iproc_pcie_ob_write(struct iproc_pcie *pcie,
++				       enum iproc_pcie_reg reg,
++				       unsigned window, u32 val)
++{
++	u16 offset = iproc_pcie_reg_offset(pcie, reg);
++
++	if (iproc_pcie_reg_is_invalid(offset))
++		return;
++
++	writel(val, pcie->base + offset + (window * 8));
++}
++
++static inline bool iproc_pcie_device_is_valid(struct iproc_pcie *pcie,
++					      unsigned int slot,
++					      unsigned int fn)
++{
++	if (slot > 0)
++		return false;
++
++	/* PAXC can only support limited number of functions */
++	if (pcie->type == IPROC_PCIE_PAXC && fn >= MAX_NUM_PAXC_PF)
++		return false;
++
++	return true;
++}
++
+ /**
+  * Note access to the configuration registers are protected at the higher layer
+  * by 'pci_lock' in drivers/pci/access.c
+@@ -104,28 +197,34 @@ static void __iomem *iproc_pcie_map_cfg_
+ 	unsigned fn = PCI_FUNC(devfn);
+ 	unsigned busno = bus->number;
+ 	u32 val;
++	u16 offset;
++
++	if (!iproc_pcie_device_is_valid(pcie, slot, fn))
++		return NULL;
+ 
+ 	/* root complex access */
+ 	if (busno == 0) {
+-		if (slot >= 1)
++		iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
++				     where & CFG_IND_ADDR_MASK);
++		offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
++		if (iproc_pcie_reg_is_invalid(offset))
+ 			return NULL;
+-		writel(where & CFG_IND_ADDR_MASK,
+-		       pcie->base + CFG_IND_ADDR_OFFSET);
+-		return (pcie->base + CFG_IND_DATA_OFFSET);
++		else
++			return (pcie->base + offset);
+ 	}
+ 
+-	if (fn > 1)
+-		return NULL;
+-
+ 	/* EP device access */
+ 	val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
+ 		(slot << CFG_ADDR_DEV_NUM_SHIFT) |
+ 		(fn << CFG_ADDR_FUNC_NUM_SHIFT) |
+ 		(where & CFG_ADDR_REG_NUM_MASK) |
+ 		(1 & CFG_ADDR_CFG_TYPE_MASK);
+-	writel(val, pcie->base + CFG_ADDR_OFFSET);
+-
+-	return (pcie->base + CFG_DATA_OFFSET);
++	iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
++	offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
++	if (iproc_pcie_reg_is_invalid(offset))
++		return NULL;
++	else
++		return (pcie->base + offset);
+ }
+ 
+ static struct pci_ops iproc_pcie_ops = {
+@@ -138,18 +237,29 @@ static void iproc_pcie_reset(struct ipro
+ {
+ 	u32 val;
+ 
++	if (pcie->type == IPROC_PCIE_PAXC) {
++		val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
++		val &= ~PAXC_RESET_MASK;
++		iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
++		udelay(100);
++		val |= PAXC_RESET_MASK;
++		iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
++		udelay(100);
++		return;
++	}
++
+ 	/*
+ 	 * Select perst_b signal as reset source. Put the device into reset,
+ 	 * and then bring it out of reset
+ 	 */
+-	val = readl(pcie->base + CLK_CONTROL_OFFSET);
++	val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
+ 	val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
+ 		~RC_PCIE_RST_OUTPUT;
+-	writel(val, pcie->base + CLK_CONTROL_OFFSET);
++	iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
+ 	udelay(250);
+ 
+ 	val |= RC_PCIE_RST_OUTPUT;
+-	writel(val, pcie->base + CLK_CONTROL_OFFSET);
++	iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
+ 	msleep(100);
+ }
+ 
+@@ -160,7 +270,14 @@ static int iproc_pcie_check_link(struct
+ 	u16 pos, link_status;
+ 	bool link_is_active = false;
+ 
+-	val = readl(pcie->base + PCIE_LINK_STATUS_OFFSET);
++	/*
++	 * PAXC connects to emulated endpoint devices directly and does not
++	 * have a Serdes. Therefore skip the link detection logic here
++	 */
++	if (pcie->type == IPROC_PCIE_PAXC)
++		return 0;
++
++	val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
+ 	if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
+ 		dev_err(pcie->dev, "PHY or data link is INACTIVE!\n");
+ 		return -ENODEV;
+@@ -221,7 +338,7 @@ static int iproc_pcie_check_link(struct
+ 
+ static void iproc_pcie_enable(struct iproc_pcie *pcie)
+ {
+-	writel(SYS_RC_INTX_MASK, pcie->base + SYS_RC_INTX_EN);
++	iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
+ }
+ 
+ /**
+@@ -272,11 +389,15 @@ static int iproc_pcie_setup_ob(struct ip
+ 	axi_addr -= ob->axi_offset;
+ 
+ 	for (i = 0; i < MAX_NUM_OB_WINDOWS; i++) {
+-		writel(lower_32_bits(axi_addr) | OARR_VALID |
+-		       (ob->set_oarr_size ? 1 : 0), pcie->base + OARR_LO(i));
+-		writel(upper_32_bits(axi_addr), pcie->base + OARR_HI(i));
+-		writel(lower_32_bits(pci_addr), pcie->base + OMAP_LO(i));
+-		writel(upper_32_bits(pci_addr), pcie->base + OMAP_HI(i));
++		iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_LO, i,
++				    lower_32_bits(axi_addr) | OARR_VALID |
++				    (ob->set_oarr_size ? 1 : 0));
++		iproc_pcie_ob_write(pcie, IPROC_PCIE_OARR_HI, i,
++				    upper_32_bits(axi_addr));
++		iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_LO, i,
++				    lower_32_bits(pci_addr));
++		iproc_pcie_ob_write(pcie, IPROC_PCIE_OMAP_HI, i,
++				    upper_32_bits(pci_addr));
+ 
+ 		size -= ob->window_size;
+ 		if (size == 0)
+@@ -340,6 +461,19 @@ int iproc_pcie_setup(struct iproc_pcie *
+ 		goto err_exit_phy;
+ 	}
+ 
++	switch (pcie->type) {
++	case IPROC_PCIE_PAXB:
++		pcie->reg_offsets = iproc_pcie_reg_paxb;
++		break;
++	case IPROC_PCIE_PAXC:
++		pcie->reg_offsets = iproc_pcie_reg_paxc;
++		break;
++	default:
++		dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
++		ret = -EINVAL;
++		goto err_power_off_phy;
++	}
++
+ 	iproc_pcie_reset(pcie);
+ 
+ 	if (pcie->need_ob_cfg) {
+--- a/drivers/pci/host/pcie-iproc.h
++++ b/drivers/pci/host/pcie-iproc.h
+@@ -15,6 +15,20 @@
+ #define _PCIE_IPROC_H
+ 
+ /**
++ * iProc PCIe interface type
++ *
++ * PAXB is the wrapper used in root complex that can be connected to an
++ * external endpoint device
++ *
++ * PAXC is the wrapper used in root complex dedicated for internal emulated
++ * endpoint devices
++ */
++enum iproc_pcie_type {
++	IPROC_PCIE_PAXB = 0,
++	IPROC_PCIE_PAXC,
++};
++
++/**
+  * iProc PCIe outbound mapping
+  * @set_oarr_size: indicates the OARR size bit needs to be set
+  * @axi_offset: offset from the AXI address to the internal address used by
+@@ -29,7 +43,10 @@ struct iproc_pcie_ob {
+ 
+ /**
+  * iProc PCIe device
++ *
+  * @dev: pointer to device data structure
++ * @type: iProc PCIe interface type
++ * @reg_offsets: register offsets
+  * @base: PCIe host controller I/O register base
+  * @sysdata: Per PCI controller data (ARM-specific)
+  * @root_bus: pointer to root bus
+@@ -41,6 +58,8 @@ struct iproc_pcie_ob {
+  */
+ struct iproc_pcie {
+ 	struct device *dev;
++	enum iproc_pcie_type type;
++	const u16 *reg_offsets;
+ 	void __iomem *base;
+ #ifdef CONFIG_ARM
+ 	struct pci_sys_data sysdata;

target/linux/bcm53xx/patches-4.3/152-PCI-iproc-Add-iProc-PCIe-MSI-device-tree-binding.patch

@@ -0,0 +1,67 @@
+From 96b40de5e36ec479dabb88500f1830a87818a809 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Mon, 16 Nov 2015 17:57:33 -0800
+Subject: [PATCH 152/154] PCI: iproc: Add iProc PCIe MSI device tree binding
+
+This patch updates the iProc PCIe device tree bindings with added
+binding information for MSI
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Reviewed-by: Anup Patel <anup.patel@broadcom.com>
+Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+---
+ .../devicetree/bindings/pci/brcm,iproc-pcie.txt    | 35 ++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+--- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
++++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
+@@ -35,6 +35,28 @@ Optional:
+ - brcm,pcie-ob-oarr-size: Some iProc SoCs need the OARR size bit to be set to
+ increase the outbound window size
+ 
++MSI support (optional):
++
++For older platforms without MSI integrated in the GIC, iProc PCIe core provides
++an event queue based MSI support. The iProc MSI uses host memories to store
++MSI posted writes in the event queues
++
++- msi-parent: Link to the device node of the MSI controller. On newer iProc
++platforms, the MSI controller may be gicv2m or gicv3-its. On older iProc
++platforms without MSI support in its interrupt controller, one may use the
++event queue based MSI support integrated within the iProc PCIe core
++
++When the iProc event queue based MSI is used, one needs to define the
++following properties in the MSI device node:
++- compatible: Must be "brcm,iproc-msi"
++- msi-controller: claims itself as an MSI controller
++- interrupt-parent: Link to its parent interrupt device
++- interrupts: List of interrupt IDs from its parent interrupt device
++
++Optional properties:
++- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that
++require the interrupt enable registers to be set explicitly to enable MSI
++
+ Example:
+ 	pcie0: pcie@18012000 {
+ 		compatible = "brcm,iproc-pcie";
+@@ -61,6 +83,19 @@ Example:
+ 		brcm,pcie-ob-oarr-size;
+ 		brcm,pcie-ob-axi-offset = <0x00000000>;
+ 		brcm,pcie-ob-window-size = <256>;
++
++		msi-parent = <&msi0>;
++
++		/* iProc event queue based MSI */
++		msi0: msi@18012000 {
++			compatible = "brcm,iproc-msi";
++			msi-controller;
++			interrupt-parent = <&gic>;
++			interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
++				     <GIC_SPI 97 IRQ_TYPE_NONE>,
++				     <GIC_SPI 98 IRQ_TYPE_NONE>,
++				     <GIC_SPI 99 IRQ_TYPE_NONE>,
++		};
+ 	};
+ 
+ 	pcie1: pcie@18013000 {

target/linux/bcm53xx/patches-4.3/153-PCI-iproc-Add-iProc-PCIe-MSI-support.patch

@@ -0,0 +1,886 @@
+From c81922174d61127ff5baad6059ae148794c72276 Mon Sep 17 00:00:00 2001
+From: Ray Jui <rjui@broadcom.com>
+Date: Tue, 17 Nov 2015 13:14:37 -0800
+Subject: [PATCH 153/154] PCI: iproc: Add iProc PCIe MSI support
+
+This patch adds PCIe MSI support for both PAXB and PAXC interfaces on
+all iProc based platforms
+
+The iProc PCIe MSI support deploys an event queue based implementation.
+Each event queue is serviced by a GIC interrupt and can support up to 64
+MSI vectors. Host memory is allocated for the event queues, and each event
+queue consists of 64 word-sized entries. MSI data is written to the
+lower 16-bit of each entry, whereas the upper 16-bit of the entry is
+reserved for the controller for internal processing
+
+Each event queue is tracked by a head pointer and tail pointer. Head
+pointer indicates the next entry in the event queue to be processed by
+the driver and is updated by the driver after processing is done.
+The controller uses the tail pointer as the next MSI data insertion
+point. The controller ensures MSI data is flushed to host memory before
+updating the tail pointer and then triggering the interrupt
+
+MSI IRQ affinity is supported by evenly distributing the interrupts to
+each CPU core. MSI vector is moved from one GIC interrupt to another in
+order to steer to the target CPU
+
+Therefore, the actual number of supported MSI vectors is:
+
+M * 64 / N
+
+where M denotes the number of GIC interrupts (event queues), and N
+denotes the number of CPU cores
+
+This iProc event queue based MSI support should not be used with newer
+platforms with integrated MSI support in the GIC (e.g., giv2m or
+gicv3-its)
+
+Signed-off-by: Ray Jui <rjui@broadcom.com>
+Reviewed-by: Anup Patel <anup.patel@broadcom.com>
+Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
+Reviewed-by: Scott Branden <sbranden@broadcom.com>
+---
+ drivers/pci/host/Kconfig               |   9 +
+ drivers/pci/host/Makefile              |   1 +
+ drivers/pci/host/pcie-iproc-bcma.c     |   1 +
+ drivers/pci/host/pcie-iproc-msi.c      | 675 +++++++++++++++++++++++++++++++++
+ drivers/pci/host/pcie-iproc-platform.c |   1 +
+ drivers/pci/host/pcie-iproc.c          |  26 ++
+ drivers/pci/host/pcie-iproc.h          |  23 +-
+ 7 files changed, 734 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/pci/host/pcie-iproc-msi.c
+
+--- a/drivers/pci/host/Kconfig
++++ b/drivers/pci/host/Kconfig
+@@ -124,6 +124,15 @@ config PCIE_IPROC
+ 	  iProc family of SoCs. An appropriate bus interface driver also needs
+ 	  to be enabled
+ 
++config PCIE_IPROC_MSI
++	bool "Broadcom iProc PCIe MSI support"
++	depends on ARCH_BCM_IPROC && PCI_MSI
++	select PCI_MSI_IRQ_DOMAIN
++	default ARCH_BCM_IPROC
++	help
++	  Say Y here if you want to enable MSI support for Broadcom's iProc
++	  PCIe controller
++
+ config PCIE_IPROC_PLATFORM
+ 	tristate "Broadcom iProc PCIe platform bus driver"
+ 	depends on ARCH_BCM_IPROC || (ARM && COMPILE_TEST)
+--- a/drivers/pci/host/Makefile
++++ b/drivers/pci/host/Makefile
+@@ -15,5 +15,6 @@ obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene
+ obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
+ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
+ obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
++obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
+ obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o
+ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
+--- a/drivers/pci/host/pcie-iproc-bcma.c
++++ b/drivers/pci/host/pcie-iproc-bcma.c
+@@ -55,6 +55,7 @@ static int iproc_pcie_bcma_probe(struct
+ 	bcma_set_drvdata(bdev, pcie);
+ 
+ 	pcie->base = bdev->io_addr;
++	pcie->base_addr = bdev->addr;
+ 
+ 	res_mem.start = bdev->addr_s[0];
+ 	res_mem.end = bdev->addr_s[0] + SZ_128M - 1;
+--- /dev/null
++++ b/drivers/pci/host/pcie-iproc-msi.c
+@@ -0,0 +1,675 @@
++/*
++ * Copyright (C) 2015 Broadcom Corporation
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation version 2.
++ *
++ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
++ * kind, whether express or implied; without even the implied warranty
++ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/interrupt.h>
++#include <linux/irqchip/chained_irq.h>
++#include <linux/irqdomain.h>
++#include <linux/msi.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
++#include <linux/pci.h>
++
++#include "pcie-iproc.h"
++
++#define IPROC_MSI_INTR_EN_SHIFT        11
++#define IPROC_MSI_INTR_EN              BIT(IPROC_MSI_INTR_EN_SHIFT)
++#define IPROC_MSI_INT_N_EVENT_SHIFT    1
++#define IPROC_MSI_INT_N_EVENT          BIT(IPROC_MSI_INT_N_EVENT_SHIFT)
++#define IPROC_MSI_EQ_EN_SHIFT          0
++#define IPROC_MSI_EQ_EN                BIT(IPROC_MSI_EQ_EN_SHIFT)
++
++#define IPROC_MSI_EQ_MASK              0x3f
++
++/* max number of GIC interrupts */
++#define NR_HW_IRQS                     6
++
++/* number of entries in each event queue */
++#define EQ_LEN                         64
++
++/* size of each event queue memory region */
++#define EQ_MEM_REGION_SIZE             SZ_4K
++
++/* size of each MSI address region */
++#define MSI_MEM_REGION_SIZE            SZ_4K
++
++enum iproc_msi_reg {
++	IPROC_MSI_EQ_PAGE = 0,
++	IPROC_MSI_EQ_PAGE_UPPER,
++	IPROC_MSI_PAGE,
++	IPROC_MSI_PAGE_UPPER,
++	IPROC_MSI_CTRL,
++	IPROC_MSI_EQ_HEAD,
++	IPROC_MSI_EQ_TAIL,
++	IPROC_MSI_INTS_EN,
++	IPROC_MSI_REG_SIZE,
++};
++
++struct iproc_msi;
++
++/**
++ * iProc MSI group
++ *
++ * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
++ * event queue
++ *
++ * @msi: pointer to iProc MSI data
++ * @gic_irq: GIC interrupt
++ * @eq: Event queue number
++ */
++struct iproc_msi_grp {
++	struct iproc_msi *msi;
++	int gic_irq;
++	unsigned int eq;
++};
++
++/**
++ * iProc event queue based MSI
++ *
++ * Only meant to be used on platforms without MSI support integrated into the
++ * GIC
++ *
++ * @pcie: pointer to iProc PCIe data
++ * @reg_offsets: MSI register offsets
++ * @grps: MSI groups
++ * @nr_irqs: number of total interrupts connected to GIC
++ * @nr_cpus: number of toal CPUs
++ * @has_inten_reg: indicates the MSI interrupt enable register needs to be
++ * set explicitly (required for some legacy platforms)
++ * @bitmap: MSI vector bitmap
++ * @bitmap_lock: lock to protect access to the MSI bitmap
++ * @nr_msi_vecs: total number of MSI vectors
++ * @inner_domain: inner IRQ domain
++ * @msi_domain: MSI IRQ domain
++ * @nr_eq_region: required number of 4K aligned memory region for MSI event
++ * queues
++ * @nr_msi_region: required number of 4K aligned address region for MSI posted
++ * writes
++ * @eq_cpu: pointer to allocated memory region for MSI event queues
++ * @eq_dma: DMA address of MSI event queues
++ * @msi_addr: MSI address
++ */
++struct iproc_msi {
++	struct iproc_pcie *pcie;
++	const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE];
++	struct iproc_msi_grp *grps;
++	int nr_irqs;
++	int nr_cpus;
++	bool has_inten_reg;
++	unsigned long *bitmap;
++	struct mutex bitmap_lock;
++	unsigned int nr_msi_vecs;
++	struct irq_domain *inner_domain;
++	struct irq_domain *msi_domain;
++	unsigned int nr_eq_region;
++	unsigned int nr_msi_region;
++	void *eq_cpu;
++	dma_addr_t eq_dma;
++	phys_addr_t msi_addr;
++};
++
++static const u16 iproc_msi_reg_paxb[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
++	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x210, 0x250, 0x254, 0x208 },
++	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x214, 0x258, 0x25c, 0x208 },
++	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x218, 0x260, 0x264, 0x208 },
++	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x21c, 0x268, 0x26c, 0x208 },
++	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x220, 0x270, 0x274, 0x208 },
++	{ 0x200, 0x2c0, 0x204, 0x2c4, 0x224, 0x278, 0x27c, 0x208 },
++};
++
++static const u16 iproc_msi_reg_paxc[NR_HW_IRQS][IPROC_MSI_REG_SIZE] = {
++	{ 0xc00, 0xc04, 0xc08, 0xc0c, 0xc40, 0xc50, 0xc60 },
++	{ 0xc10, 0xc14, 0xc18, 0xc1c, 0xc44, 0xc54, 0xc64 },
++	{ 0xc20, 0xc24, 0xc28, 0xc2c, 0xc48, 0xc58, 0xc68 },
++	{ 0xc30, 0xc34, 0xc38, 0xc3c, 0xc4c, 0xc5c, 0xc6c },
++};
++
++static inline u32 iproc_msi_read_reg(struct iproc_msi *msi,
++				     enum iproc_msi_reg reg,
++				     unsigned int eq)
++{
++	struct iproc_pcie *pcie = msi->pcie;
++
++	return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]);
++}
++
++static inline void iproc_msi_write_reg(struct iproc_msi *msi,
++				       enum iproc_msi_reg reg,
++				       int eq, u32 val)
++{
++	struct iproc_pcie *pcie = msi->pcie;
++
++	writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]);
++}
++
++static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq)
++{
++	return (hwirq % msi->nr_irqs);
++}
++
++static inline unsigned int iproc_msi_addr_offset(struct iproc_msi *msi,
++						 unsigned long hwirq)
++{
++	if (msi->nr_msi_region > 1)
++		return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE;
++	else
++		return hwirq_to_group(msi, hwirq) * sizeof(u32);
++}
++
++static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq)
++{
++	if (msi->nr_eq_region > 1)
++		return eq * EQ_MEM_REGION_SIZE;
++	else
++		return eq * EQ_LEN * sizeof(u32);
++}
++
++static struct irq_chip iproc_msi_irq_chip = {
++	.name = "iProc-MSI",
++};
++
++static struct msi_domain_info iproc_msi_domain_info = {
++	.flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
++		MSI_FLAG_PCI_MSIX,
++	.chip = &iproc_msi_irq_chip,
++};
++
++/*
++ * In iProc PCIe core, each MSI group is serviced by a GIC interrupt and a
++ * dedicated event queue. Each MSI group can support up to 64 MSI vectors
++ *
++ * The number of MSI groups varies between different iProc SoCs. The total
++ * number of CPU cores also varies. To support MSI IRQ affinity, we
++ * distribute GIC interrupts across all available CPUs. MSI vector is moved
++ * from one GIC interrupt to another to steer to the target CPU
++ *
++ * Assuming:
++ * - the number of MSI groups is M
++ * - the number of CPU cores is N
++ * - M is always a multiple of N
++ *
++ * Total number of raw MSI vectors = M * 64
++ * Total number of supported MSI vectors = (M * 64) / N
++ */
++static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq)
++{
++	return (hwirq % msi->nr_cpus);
++}
++
++static inline unsigned long hwirq_to_canonical_hwirq(struct iproc_msi *msi,
++						     unsigned long hwirq)
++{
++	return (hwirq - hwirq_to_cpu(msi, hwirq));
++}
++
++static int iproc_msi_irq_set_affinity(struct irq_data *data,
++				      const struct cpumask *mask, bool force)
++{
++	struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
++	int target_cpu = cpumask_first(mask);
++	int curr_cpu;
++
++	curr_cpu = hwirq_to_cpu(msi, data->hwirq);
++	if (curr_cpu == target_cpu)
++		return IRQ_SET_MASK_OK_DONE;
++
++	/* steer MSI to the target CPU */
++	data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu;
++
++	return IRQ_SET_MASK_OK;
++}
++
++static void iproc_msi_irq_compose_msi_msg(struct irq_data *data,
++					  struct msi_msg *msg)
++{
++	struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
++	dma_addr_t addr;
++
++	addr = msi->msi_addr + iproc_msi_addr_offset(msi, data->hwirq);
++	msg->address_lo = lower_32_bits(addr);
++	msg->address_hi = upper_32_bits(addr);
++	msg->data = data->hwirq;
++}
++
++static struct irq_chip iproc_msi_bottom_irq_chip = {
++	.name = "MSI",
++	.irq_set_affinity = iproc_msi_irq_set_affinity,
++	.irq_compose_msi_msg = iproc_msi_irq_compose_msi_msg,
++};
++
++static int iproc_msi_irq_domain_alloc(struct irq_domain *domain,
++				      unsigned int virq, unsigned int nr_irqs,
++				      void *args)
++{
++	struct iproc_msi *msi = domain->host_data;
++	int hwirq;
++
++	mutex_lock(&msi->bitmap_lock);
++
++	/* allocate 'nr_cpus' number of MSI vectors each time */
++	hwirq = bitmap_find_next_zero_area(msi->bitmap, msi->nr_msi_vecs, 0,
++					   msi->nr_cpus, 0);
++	if (hwirq < msi->nr_msi_vecs) {
++		bitmap_set(msi->bitmap, hwirq, msi->nr_cpus);
++	} else {
++		mutex_unlock(&msi->bitmap_lock);
++		return -ENOSPC;
++	}
++
++	mutex_unlock(&msi->bitmap_lock);
++
++	irq_domain_set_info(domain, virq, hwirq, &iproc_msi_bottom_irq_chip,
++			    domain->host_data, handle_simple_irq, NULL, NULL);
++
++	return 0;
++}
++
++static void iproc_msi_irq_domain_free(struct irq_domain *domain,
++				      unsigned int virq, unsigned int nr_irqs)
++{
++	struct irq_data *data = irq_domain_get_irq_data(domain, virq);
++	struct iproc_msi *msi = irq_data_get_irq_chip_data(data);
++	unsigned int hwirq;
++
++	mutex_lock(&msi->bitmap_lock);
++
++	hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq);
++	bitmap_clear(msi->bitmap, hwirq, msi->nr_cpus);
++
++	mutex_unlock(&msi->bitmap_lock);
++
++	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
++}
++
++static const struct irq_domain_ops msi_domain_ops = {
++	.alloc = iproc_msi_irq_domain_alloc,
++	.free = iproc_msi_irq_domain_free,
++};
++
++static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head)
++{
++	u32 *msg, hwirq;
++	unsigned int offs;
++
++	offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32);
++	msg = (u32 *)(msi->eq_cpu + offs);
++	hwirq = *msg & IPROC_MSI_EQ_MASK;
++
++	/*
++	 * Since we have multiple hwirq mapped to a single MSI vector,
++	 * now we need to derive the hwirq at CPU0. It can then be used to
++	 * mapped back to virq
++	 */
++	return hwirq_to_canonical_hwirq(msi, hwirq);
++}
++
++static void iproc_msi_handler(struct irq_desc *desc)
++{
++	struct irq_chip *chip = irq_desc_get_chip(desc);
++	struct iproc_msi_grp *grp;
++	struct iproc_msi *msi;
++	struct iproc_pcie *pcie;
++	u32 eq, head, tail, nr_events;
++	unsigned long hwirq;
++	int virq;
++
++	chained_irq_enter(chip, desc);
++
++	grp = irq_desc_get_handler_data(desc);
++	msi = grp->msi;
++	pcie = msi->pcie;
++	eq = grp->eq;
++
++	/*
++	 * iProc MSI event queue is tracked by head and tail pointers. Head
++	 * pointer indicates the next entry (MSI data) to be consumed by SW in
++	 * the queue and needs to be updated by SW. iProc MSI core uses the
++	 * tail pointer as the next data insertion point
++	 *
++	 * Entries between head and tail pointers contain valid MSI data. MSI
++	 * data is guaranteed to be in the event queue memory before the tail
++	 * pointer is updated by the iProc MSI core
++	 */
++	head = iproc_msi_read_reg(msi, IPROC_MSI_EQ_HEAD,
++				  eq) & IPROC_MSI_EQ_MASK;
++	do {
++		tail = iproc_msi_read_reg(msi, IPROC_MSI_EQ_TAIL,
++					  eq) & IPROC_MSI_EQ_MASK;
++
++		/*
++		 * Figure out total number of events (MSI data) to be
++		 * processed
++		 */
++		nr_events = (tail < head) ?
++			(EQ_LEN - (head - tail)) : (tail - head);
++		if (!nr_events)
++			break;
++
++		/* process all outstanding events */
++		while (nr_events--) {
++			hwirq = decode_msi_hwirq(msi, eq, head);
++			virq = irq_find_mapping(msi->inner_domain, hwirq);
++			generic_handle_irq(virq);
++
++			head++;
++			head %= EQ_LEN;
++		}
++
++		/*
++		 * Now all outstanding events have been processed. Update the
++		 * head pointer
++		 */
++		iproc_msi_write_reg(msi, IPROC_MSI_EQ_HEAD, eq, head);
++
++		/*
++		 * Now go read the tail pointer again to see if there are new
++		 * oustanding events that came in during the above window
++		 */
++	} while (true);
++
++	chained_irq_exit(chip, desc);
++}
++
++static void iproc_msi_enable(struct iproc_msi *msi)
++{
++	int i, eq;
++	u32 val;
++
++	/* program memory region for each event queue */
++	for (i = 0; i < msi->nr_eq_region; i++) {
++		dma_addr_t addr = msi->eq_dma + (i * EQ_MEM_REGION_SIZE);
++
++		iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE, i,
++				    lower_32_bits(addr));
++		iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE_UPPER, i,
++				    upper_32_bits(addr));
++	}
++
++	/* program address region for MSI posted writes */
++	for (i = 0; i < msi->nr_msi_region; i++) {
++		phys_addr_t addr = msi->msi_addr + (i * MSI_MEM_REGION_SIZE);
++
++		iproc_msi_write_reg(msi, IPROC_MSI_PAGE, i,
++				    lower_32_bits(addr));
++		iproc_msi_write_reg(msi, IPROC_MSI_PAGE_UPPER, i,
++				    upper_32_bits(addr));
++	}
++
++	for (eq = 0; eq < msi->nr_irqs; eq++) {
++		/* enable MSI event queue */
++		val = IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
++			IPROC_MSI_EQ_EN;
++		iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
++
++		/*
++		 * Some legacy platforms require the MSI interrupt enable
++		 * register to be set explicitly
++		 */
++		if (msi->has_inten_reg) {
++			val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
++			val |= BIT(eq);
++			iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
++		}
++	}
++}
++
++static void iproc_msi_disable(struct iproc_msi *msi)
++{
++	u32 eq, val;
++
++	for (eq = 0; eq < msi->nr_irqs; eq++) {
++		if (msi->has_inten_reg) {
++			val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq);
++			val &= ~BIT(eq);
++			iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val);
++		}
++
++		val = iproc_msi_read_reg(msi, IPROC_MSI_CTRL, eq);
++		val &= ~(IPROC_MSI_INTR_EN | IPROC_MSI_INT_N_EVENT |
++			 IPROC_MSI_EQ_EN);
++		iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val);
++	}
++}
++
++static int iproc_msi_alloc_domains(struct device_node *node,
++				   struct iproc_msi *msi)
++{
++	msi->inner_domain = irq_domain_add_linear(NULL, msi->nr_msi_vecs,
++						  &msi_domain_ops, msi);
++	if (!msi->inner_domain)
++		return -ENOMEM;
++
++	msi->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
++						    &iproc_msi_domain_info,
++						    msi->inner_domain);
++	if (!msi->msi_domain) {
++		irq_domain_remove(msi->inner_domain);
++		return -ENOMEM;
++	}
++
++	return 0;
++}
++
++static void iproc_msi_free_domains(struct iproc_msi *msi)
++{
++	if (msi->msi_domain)
++		irq_domain_remove(msi->msi_domain);
++
++	if (msi->inner_domain)
++		irq_domain_remove(msi->inner_domain);
++}
++
++static void iproc_msi_irq_free(struct iproc_msi *msi, unsigned int cpu)
++{
++	int i;
++
++	for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
++		irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
++						 NULL, NULL);
++	}
++}
++
++static int iproc_msi_irq_setup(struct iproc_msi *msi, unsigned int cpu)
++{
++	int i, ret;
++	cpumask_var_t mask;
++	struct iproc_pcie *pcie = msi->pcie;
++
++	for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) {
++		irq_set_chained_handler_and_data(msi->grps[i].gic_irq,
++						 iproc_msi_handler,
++						 &msi->grps[i]);
++		/* dedicate GIC interrupt to each CPU core */
++		if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
++			cpumask_clear(mask);
++			cpumask_set_cpu(cpu, mask);
++			ret = irq_set_affinity(msi->grps[i].gic_irq, mask);
++			if (ret)
++				dev_err(pcie->dev,
++					"failed to set affinity for IRQ%d\n",
++					msi->grps[i].gic_irq);
++			free_cpumask_var(mask);
++		} else {
++			dev_err(pcie->dev, "failed to alloc CPU mask\n");
++			ret = -EINVAL;
++		}
++
++		if (ret) {
++			/* free all configured/unconfigured irqs */
++			iproc_msi_irq_free(msi, cpu);
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node)
++{
++	struct iproc_msi *msi;
++	int i, ret;
++	unsigned int cpu;
++
++	if (!of_device_is_compatible(node, "brcm,iproc-msi"))
++		return -ENODEV;
++
++	if (!of_find_property(node, "msi-controller", NULL))
++		return -ENODEV;
++
++	if (pcie->msi)
++		return -EBUSY;
++
++	msi = devm_kzalloc(pcie->dev, sizeof(*msi), GFP_KERNEL);
++	if (!msi)
++		return -ENOMEM;
++
++	msi->pcie = pcie;
++	pcie->msi = msi;
++	msi->msi_addr = pcie->base_addr;
++	mutex_init(&msi->bitmap_lock);
++	msi->nr_cpus = num_possible_cpus();
++
++	msi->nr_irqs = of_irq_count(node);
++	if (!msi->nr_irqs) {
++		dev_err(pcie->dev, "found no MSI GIC interrupt\n");
++		return -ENODEV;
++	}
++
++	if (msi->nr_irqs > NR_HW_IRQS) {
++		dev_warn(pcie->dev, "too many MSI GIC interrupts defined %d\n",
++			 msi->nr_irqs);
++		msi->nr_irqs = NR_HW_IRQS;
++	}
++
++	if (msi->nr_irqs < msi->nr_cpus) {
++		dev_err(pcie->dev,
++			"not enough GIC interrupts for MSI affinity\n");
++		return -EINVAL;
++	}
++
++	if (msi->nr_irqs % msi->nr_cpus != 0) {
++		msi->nr_irqs -= msi->nr_irqs % msi->nr_cpus;
++		dev_warn(pcie->dev, "Reducing number of interrupts to %d\n",
++			 msi->nr_irqs);
++	}
++
++	switch (pcie->type) {
++	case IPROC_PCIE_PAXB:
++		msi->reg_offsets = iproc_msi_reg_paxb;
++		msi->nr_eq_region = 1;
++		msi->nr_msi_region = 1;
++		break;
++	case IPROC_PCIE_PAXC:
++		msi->reg_offsets = iproc_msi_reg_paxc;
++		msi->nr_eq_region = msi->nr_irqs;
++		msi->nr_msi_region = msi->nr_irqs;
++		break;
++	default:
++		dev_err(pcie->dev, "incompatible iProc PCIe interface\n");
++		return -EINVAL;
++	}
++
++	if (of_find_property(node, "brcm,pcie-msi-inten", NULL))
++		msi->has_inten_reg = true;
++
++	msi->nr_msi_vecs = msi->nr_irqs * EQ_LEN;
++	msi->bitmap = devm_kcalloc(pcie->dev, BITS_TO_LONGS(msi->nr_msi_vecs),
++				   sizeof(*msi->bitmap), GFP_KERNEL);
++	if (!msi->bitmap)
++		return -ENOMEM;
++
++	msi->grps = devm_kcalloc(pcie->dev, msi->nr_irqs, sizeof(*msi->grps),
++				 GFP_KERNEL);
++	if (!msi->grps)
++		return -ENOMEM;
++
++	for (i = 0; i < msi->nr_irqs; i++) {
++		unsigned int irq = irq_of_parse_and_map(node, i);
++
++		if (!irq) {
++			dev_err(pcie->dev, "unable to parse/map interrupt\n");
++			ret = -ENODEV;
++			goto free_irqs;
++		}
++		msi->grps[i].gic_irq = irq;
++		msi->grps[i].msi = msi;
++		msi->grps[i].eq = i;
++	}
++
++	/* reserve memory for event queue and make sure memories are zeroed */
++	msi->eq_cpu = dma_zalloc_coherent(pcie->dev,
++					  msi->nr_eq_region * EQ_MEM_REGION_SIZE,
++					  &msi->eq_dma, GFP_KERNEL);
++	if (!msi->eq_cpu) {
++		ret = -ENOMEM;
++		goto free_irqs;
++	}
++
++	ret = iproc_msi_alloc_domains(node, msi);
++	if (ret) {
++		dev_err(pcie->dev, "failed to create MSI domains\n");
++		goto free_eq_dma;
++	}
++
++	for_each_online_cpu(cpu) {
++		ret = iproc_msi_irq_setup(msi, cpu);
++		if (ret)
++			goto free_msi_irq;
++	}
++
++	iproc_msi_enable(msi);
++
++	return 0;
++
++free_msi_irq:
++	for_each_online_cpu(cpu)
++		iproc_msi_irq_free(msi, cpu);
++	iproc_msi_free_domains(msi);
++
++free_eq_dma:
++	dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
++			  msi->eq_cpu, msi->eq_dma);
++
++free_irqs:
++	for (i = 0; i < msi->nr_irqs; i++) {
++		if (msi->grps[i].gic_irq)
++			irq_dispose_mapping(msi->grps[i].gic_irq);
++	}
++	pcie->msi = NULL;
++	return ret;
++}
++EXPORT_SYMBOL(iproc_msi_init);
++
++void iproc_msi_exit(struct iproc_pcie *pcie)
++{
++	struct iproc_msi *msi = pcie->msi;
++	unsigned int i, cpu;
++
++	if (!msi)
++		return;
++
++	iproc_msi_disable(msi);
++
++	for_each_online_cpu(cpu)
++		iproc_msi_irq_free(msi, cpu);
++
++	iproc_msi_free_domains(msi);
++
++	dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE,
++			  msi->eq_cpu, msi->eq_dma);
++
++	for (i = 0; i < msi->nr_irqs; i++) {
++		if (msi->grps[i].gic_irq)
++			irq_dispose_mapping(msi->grps[i].gic_irq);
++	}
++}
++EXPORT_SYMBOL(iproc_msi_exit);
+--- a/drivers/pci/host/pcie-iproc-platform.c
++++ b/drivers/pci/host/pcie-iproc-platform.c
+@@ -71,6 +71,7 @@ static int iproc_pcie_pltfm_probe(struct
+ 		dev_err(pcie->dev, "unable to map controller registers\n");
+ 		return -ENOMEM;
+ 	}
++	pcie->base_addr = reg.start;
+ 
+ 	if (of_property_read_bool(np, "brcm,pcie-ob")) {
+ 		u32 val;
+--- a/drivers/pci/host/pcie-iproc.c
++++ b/drivers/pci/host/pcie-iproc.c
+@@ -440,6 +440,26 @@ static int iproc_pcie_map_ranges(struct
+ 	return 0;
+ }
+ 
++static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
++{
++	struct device_node *msi_node;
++
++	msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
++	if (!msi_node)
++		return -ENODEV;
++
++	/*
++	 * If another MSI controller is being used, the call below should fail
++	 * but that is okay
++	 */
++	return iproc_msi_init(pcie, msi_node);
++}
++
++static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
++{
++	iproc_msi_exit(pcie);
++}
++
+ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
+ {
+ 	int ret;
+@@ -507,6 +527,10 @@ int iproc_pcie_setup(struct iproc_pcie *
+ 
+ 	iproc_pcie_enable(pcie);
+ 
++	if (IS_ENABLED(CONFIG_PCI_MSI))
++		if (iproc_pcie_msi_enable(pcie))
++			dev_info(pcie->dev, "not using iProc MSI\n");
++
+ 	pci_scan_child_bus(bus);
+ 	pci_assign_unassigned_bus_resources(bus);
+ 	pci_fixup_irqs(pci_common_swizzle, pcie->map_irq);
+@@ -531,6 +555,8 @@ int iproc_pcie_remove(struct iproc_pcie
+ 	pci_stop_root_bus(pcie->root_bus);
+ 	pci_remove_root_bus(pcie->root_bus);
+ 
++	iproc_pcie_msi_disable(pcie);
++
+ 	phy_power_off(pcie->phy);
+ 	phy_exit(pcie->phy);
+ 
+--- a/drivers/pci/host/pcie-iproc.h
++++ b/drivers/pci/host/pcie-iproc.h
+@@ -41,6 +41,8 @@ struct iproc_pcie_ob {
+ 	resource_size_t window_size;
+ };
+ 
++struct iproc_msi;
++
+ /**
+  * iProc PCIe device
+  *
+@@ -48,19 +50,21 @@ struct iproc_pcie_ob {
+  * @type: iProc PCIe interface type
+  * @reg_offsets: register offsets
+  * @base: PCIe host controller I/O register base
++ * @base_addr: PCIe host controller register base physical address
+  * @sysdata: Per PCI controller data (ARM-specific)
+  * @root_bus: pointer to root bus
+  * @phy: optional PHY device that controls the Serdes
+- * @irqs: interrupt IDs
+  * @map_irq: function callback to map interrupts
+- * @need_ob_cfg: indidates SW needs to configure the outbound mapping window
++ * @need_ob_cfg: indicates SW needs to configure the outbound mapping window
+  * @ob: outbound mapping parameters
++ * @msi: MSI data
+  */
+ struct iproc_pcie {
+ 	struct device *dev;
+ 	enum iproc_pcie_type type;
+ 	const u16 *reg_offsets;
+ 	void __iomem *base;
++	phys_addr_t base_addr;
+ #ifdef CONFIG_ARM
+ 	struct pci_sys_data sysdata;
+ #endif
+@@ -69,9 +73,24 @@ struct iproc_pcie {
+ 	int (*map_irq)(const struct pci_dev *, u8, u8);
+ 	bool need_ob_cfg;
+ 	struct iproc_pcie_ob ob;
++	struct iproc_msi *msi;
+ };
+ 
+ int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res);
+ int iproc_pcie_remove(struct iproc_pcie *pcie);
+ 
++#ifdef CONFIG_PCI_MSI
++int iproc_msi_init(struct iproc_pcie *pcie, struct device_node *node);
++void iproc_msi_exit(struct iproc_pcie *pcie);
++#else
++static inline int iproc_msi_init(struct iproc_pcie *pcie,
++				 struct device_node *node)
++{
++	return -ENODEV;
++}
++static void iproc_msi_exit(struct iproc_pcie *pcie)
++{
++}
++#endif
++
+ #endif /* _PCIE_IPROC_H */