mirror of https://github.com/hak5/openwrt.git
provide a system clock to be used by the MIPS timer
Signed-off-by: Florian Fainelli <florian@openwrt.org> SVN-Revision: 34550lede-17.01
parent
79c2ce01b7
commit
e37f6fb458
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@ -3,5 +3,5 @@
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#
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#
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obj-y := irq.o pci.o prom.o platform.o proc.o \
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obj-y := irq.o pci.o prom.o platform.o proc.o \
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setup.o time.o early_printk.o clock.o \
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setup.o clock.o time.o early_printk.o \
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net_core.o net_intr.o
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net_core.o net_intr.o
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@ -22,12 +22,19 @@ static struct clk uart_clk = {
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.rate = ADM8668_UARTCLK_FREQ,
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.rate = ADM8668_UARTCLK_FREQ,
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};
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};
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static struct clk sys_clk;
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struct clk *clk_get(struct device *dev, const char *id)
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struct clk *clk_get(struct device *dev, const char *id)
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{
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{
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const char *name = dev_name(dev);
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const char *lookup = id;
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if (!strcmp(name, "apb:uart0"))
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if (dev)
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lookup = dev_name(dev);
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if (!strcmp(lookup, "apb:uart0"))
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return &uart_clk;
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return &uart_clk;
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if (!strcmp(lookup, "sys"))
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return &sys_clk;
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return ERR_PTR(-ENOENT);
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return ERR_PTR(-ENOENT);
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}
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}
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@ -54,3 +61,16 @@ void clk_put(struct clk *clk)
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{
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{
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}
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}
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EXPORT_SYMBOL(clk_put);
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EXPORT_SYMBOL(clk_put);
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void __init adm8668_init_clocks(void)
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{
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u32 adj;
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/* adjustable clock selection
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* CR3 bit 14~11, 0000 -> 175MHz, 0001 -> 180MHz, etc...
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*/
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adj = (ADM8668_CONFIG_REG(ADM8668_CR3) >> 11) & 0xf;
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sys_clk.rate = SYS_CLOCK + adj * 5000000;
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pr_info("ADM8668 CPU clock: %lu MHz\n", sys_clk.rate / 1000000);
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}
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@ -1,17 +1,20 @@
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <asm/time.h>
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#include <asm/time.h>
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#include <adm8668.h>
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#include <adm8668.h>
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void __init plat_time_init(void)
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void __init plat_time_init(void)
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{
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{
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int adj = (ADM8668_CONFIG_REG(ADM8668_CR3) >> 11) & 0xf;
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struct clk *sys_clk;
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/* adjustable clock selection
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adm8668_init_clocks();
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CR3 bit 14~11, 0000 -> 175MHz, 0001 -> 180MHz, etc... */
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mips_hpt_frequency = (SYS_CLOCK + adj * 5000000) / 2;
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sys_clk = clk_get(NULL, "sys");
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printk("ADM8668 CPU clock: %d MHz\n", 2*mips_hpt_frequency / 1000000);
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if (IS_ERR(sys_clk))
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panic("unable to get system clock\n");
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mips_hpt_frequency = clk_get_rate(sys_clk) / 2;
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}
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}
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@ -109,4 +109,6 @@
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#define CRGPIO_TOGGLE(num) \
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#define CRGPIO_TOGGLE(num) \
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ADM8668_CONFIG_REG(CRGPIO_REG) ^= (1 << (6 + num))
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ADM8668_CONFIG_REG(CRGPIO_REG) ^= (1 << (6 + num))
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void adm8668_init_clocks(void);
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#endif /* __ADM8668_H__ */
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#endif /* __ADM8668_H__ */
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