mirror of https://github.com/hak5/openwrt.git
kernel: update 4.9 to 4.9.50
Refresh patches. Compile-tested on ipq8065/nbg6817 and x86/64. Runtime-tested on ipq8065/nbg6817 and x86/64. Fixes CVE-2017-1000251. Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be> [adapt qcom_nandc.c patches to match upstream changes, test ipq8065/nbg6817] Signed-off-by: Stefan Lippers-Hollmann <s.l-h@gmx.de>openwrt-18.06
parent
bb83c9dcca
commit
e37c7636ee
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@ -4,11 +4,11 @@ LINUX_RELEASE?=1
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LINUX_VERSION-3.18 = .71
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LINUX_VERSION-4.4 = .88
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LINUX_VERSION-4.9 = .49
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LINUX_VERSION-4.9 = .50
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LINUX_KERNEL_HASH-3.18.71 = 5abc9778ad44ce02ed6c8ab52ece8a21c6d20d21f6ed8a19287b4a38a50c1240
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LINUX_KERNEL_HASH-4.4.88 = 144fe8dd773ec317fa06109b8d7bd04141bf1941daa03799fb4f437bbbb919b4
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LINUX_KERNEL_HASH-4.9.49 = 57ecdcf180b56356b2e15264ca567a8fcd9eec993fc70286bec3bd0005e791fb
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LINUX_KERNEL_HASH-4.9.50 = 2c0914c8ba3606e34c68b086ad0f470a04072d59816452c4c51e06850f2f1536
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ifdef KERNEL_PATCHVER
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LINUX_VERSION:=$(KERNEL_PATCHVER)$(strip $(LINUX_VERSION-$(KERNEL_PATCHVER)))
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@ -116,7 +116,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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compatible = "qcom,nandcs";
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--- a/drivers/mtd/nand/qcom_nandc.c
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+++ b/drivers/mtd/nand/qcom_nandc.c
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@@ -226,6 +226,7 @@ struct nandc_regs {
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@@ -234,6 +234,7 @@ struct nandc_regs {
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* by upper layers directly
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* @buf_size/count/start: markers for chip->read_buf/write_buf functions
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* @reg_read_buf: local buffer for reading back registers via DMA
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@ -124,7 +124,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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* @reg_read_pos: marker for data read in reg_read_buf
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*
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* @regs: a contiguous chunk of memory for DMA register
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@@ -234,7 +235,10 @@ struct nandc_regs {
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@@ -242,7 +243,10 @@ struct nandc_regs {
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* @cmd1/vld: some fixed controller register values
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* @ecc_modes: supported ECC modes by the current controller,
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* initialized via DT match data
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@ -136,7 +136,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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struct qcom_nand_controller {
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struct nand_hw_control controller;
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struct list_head host_list;
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@@ -247,17 +251,28 @@ struct qcom_nand_controller {
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@@ -255,17 +259,28 @@ struct qcom_nand_controller {
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struct clk *core_clk;
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struct clk *aon_clk;
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@ -168,7 +168,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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int reg_read_pos;
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struct nandc_regs *regs;
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@@ -316,6 +331,17 @@ struct qcom_nand_host {
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@@ -324,6 +339,17 @@ struct qcom_nand_host {
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u32 clrreadstatus;
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};
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@ -186,16 +186,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
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{
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return container_of(chip, struct qcom_nand_host, chip);
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@@ -1893,7 +1919,7 @@ static int qcom_nand_host_setup(struct q
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| wide_bus << WIDE_FLASH
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| 1 << DEV0_CFG1_ECC_DISABLE;
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- host->ecc_bch_cfg = host->bch_enabled << ECC_CFG_ECC_DISABLE
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+ host->ecc_bch_cfg = !host->bch_enabled << ECC_CFG_ECC_DISABLE
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| 0 << ECC_SW_RESET
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| host->cw_data << ECC_NUM_DATA_BYTES
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| 1 << ECC_FORCE_CLK_OPEN
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@@ -1942,16 +1968,46 @@ static int qcom_nandc_alloc(struct qcom_
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@@ -1949,16 +1975,46 @@ static int qcom_nandc_alloc(struct qcom_
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if (!nandc->regs)
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return -ENOMEM;
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@ -251,7 +242,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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}
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INIT_LIST_HEAD(&nandc->desc_list);
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@@ -1964,8 +2020,35 @@ static int qcom_nandc_alloc(struct qcom_
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@@ -1971,8 +2027,35 @@ static int qcom_nandc_alloc(struct qcom_
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static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc)
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{
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@ -289,7 +280,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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/* one time setup of a few nand controller registers */
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static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
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@@ -2002,6 +2085,8 @@ static int qcom_nand_host_init(struct qc
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@@ -2010,6 +2093,8 @@ static int qcom_nand_host_init(struct qc
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mtd->name = devm_kasprintf(dev, GFP_KERNEL, "qcom_nand.%d", host->cs);
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mtd->owner = THIS_MODULE;
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mtd->dev.parent = dev;
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@ -298,7 +289,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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chip->cmdfunc = qcom_nandc_command;
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chip->select_chip = qcom_nandc_select_chip;
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@@ -2049,16 +2134,20 @@ static int qcom_nandc_parse_dt(struct pl
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@@ -2057,16 +2142,20 @@ static int qcom_nandc_parse_dt(struct pl
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struct device_node *np = nandc->dev->of_node;
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int ret;
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@ -328,7 +319,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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}
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return 0;
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@@ -2073,6 +2162,7 @@ static int qcom_nandc_probe(struct platf
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@@ -2081,6 +2170,7 @@ static int qcom_nandc_probe(struct platf
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struct device_node *dn = dev->of_node, *child;
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struct resource *res;
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int ret;
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@ -336,7 +327,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL);
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if (!nandc)
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@@ -2087,7 +2177,10 @@ static int qcom_nandc_probe(struct platf
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@@ -2095,7 +2185,10 @@ static int qcom_nandc_probe(struct platf
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return -ENODEV;
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}
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@ -348,7 +339,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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nandc->base = devm_ioremap_resource(dev, res);
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@@ -2179,7 +2272,15 @@ static int qcom_nandc_remove(struct plat
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@@ -2187,7 +2280,15 @@ static int qcom_nandc_remove(struct plat
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return 0;
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}
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@ -365,7 +356,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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/*
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* data will hold a struct pointer containing more differences once we support
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@@ -2187,7 +2288,10 @@ static int qcom_nandc_remove(struct plat
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@@ -2195,7 +2296,10 @@ static int qcom_nandc_remove(struct plat
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*/
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static const struct of_device_id qcom_nandc_of_match[] = {
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{ .compatible = "qcom,ipq806x-nand",
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@ -45,7 +45,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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/* dummy register offsets, used by write_reg_dma */
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#define NAND_DEV_CMD1_RESTORE 0xdead
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@@ -131,6 +134,11 @@
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@@ -135,6 +138,11 @@
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#define ERASED_PAGE (PAGE_ALL_ERASED | PAGE_ERASED)
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#define ERASED_CW (CODEWORD_ALL_ERASED | CODEWORD_ERASED)
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@ -57,9 +57,9 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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/* Version Mask */
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#define NAND_VERSION_MAJOR_MASK 0xf0000000
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#define NAND_VERSION_MAJOR_SHIFT 28
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@@ -148,6 +156,9 @@
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#define FETCH_ID 0xb
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#define RESET_DEVICE 0xd
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@@ -156,6 +164,9 @@
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#define NAND_DEV_CMD_VLD_VAL (READ_START_VLD | WRITE_START_VLD | \
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ERASE_START_VLD | SEQ_READ_START_VLD)
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+/* NAND_CTRL bits */
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+#define BAM_MODE_EN BIT(0)
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@ -67,7 +67,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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/*
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* the NAND controller performs reads/writes with ECC in 516 byte chunks.
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* the driver calls the chunks 'step' or 'codeword' interchangeably
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@@ -169,12 +180,77 @@
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@@ -177,12 +188,77 @@
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#define ECC_BCH_4BIT BIT(2)
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#define ECC_BCH_8BIT BIT(3)
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@ -145,7 +145,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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};
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/*
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@@ -202,6 +278,13 @@ struct nandc_regs {
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@@ -210,6 +286,13 @@ struct nandc_regs {
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__le32 orig_vld;
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__le32 ecc_buf_cfg;
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@ -159,7 +159,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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};
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/*
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@@ -217,6 +300,7 @@ struct nandc_regs {
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@@ -225,6 +308,7 @@ struct nandc_regs {
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* @aon_clk: another controller clock
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*
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* @chan: dma channel
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@ -167,7 +167,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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* @cmd_crci: ADM DMA CRCI for command flow control
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* @data_crci: ADM DMA CRCI for data flow control
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* @desc_list: DMA descriptor list (list of desc_infos)
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@@ -242,6 +326,7 @@ struct nandc_regs {
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@@ -250,6 +334,7 @@ struct nandc_regs {
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struct qcom_nand_controller {
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struct nand_hw_control controller;
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struct list_head host_list;
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struct device *dev;
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@@ -342,6 +427,45 @@ struct qcom_nand_driver_data {
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@@ -350,6 +435,45 @@ struct qcom_nand_driver_data {
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bool dma_bam_enabled;
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};
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@ -221,7 +221,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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static inline struct qcom_nand_host *to_qcom_nand_host(struct nand_chip *chip)
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{
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return container_of(chip, struct qcom_nand_host, chip);
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@@ -398,6 +522,16 @@ static __le32 *offset_to_nandc_reg(struc
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@@ -406,6 +530,16 @@ static __le32 *offset_to_nandc_reg(struc
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return ®s->orig_vld;
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case NAND_EBI2_ECC_BUF_CFG:
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return ®s->ecc_buf_cfg;
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default:
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return NULL;
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}
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@@ -439,7 +573,7 @@ static void update_rw_regs(struct qcom_n
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@@ -447,7 +581,7 @@ static void update_rw_regs(struct qcom_n
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{
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struct nand_chip *chip = &host->chip;
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struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
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@ -247,7 +247,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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if (read) {
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if (host->use_ecc)
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@@ -456,12 +590,20 @@ static void update_rw_regs(struct qcom_n
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@@ -464,12 +598,20 @@ static void update_rw_regs(struct qcom_n
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cfg1 = host->cfg1;
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ecc_bch_cfg = host->ecc_bch_cfg;
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@ -268,7 +268,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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}
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nandc_set_reg(nandc, NAND_FLASH_CMD, cmd);
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@@ -472,8 +614,104 @@ static void update_rw_regs(struct qcom_n
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@@ -480,8 +622,104 @@ static void update_rw_regs(struct qcom_n
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nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
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nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
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nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
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@ -373,7 +373,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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static int prep_dma_desc(struct qcom_nand_controller *nandc, bool read,
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int reg_off, const void *vaddr, int size,
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bool flow_control)
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@@ -552,7 +790,7 @@ err:
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@@ -560,7 +798,7 @@ err:
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* @num_regs: number of registers to read
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*/
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static int read_reg_dma(struct qcom_nand_controller *nandc, int first,
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{
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bool flow_control = false;
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void *vaddr;
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@@ -561,10 +799,18 @@ static int read_reg_dma(struct qcom_nand
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@@ -569,10 +807,18 @@ static int read_reg_dma(struct qcom_nand
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if (first == NAND_READ_ID || first == NAND_FLASH_STATUS)
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flow_control = true;
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return prep_dma_desc(nandc, true, first, vaddr, size, flow_control);
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}
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@@ -576,7 +822,7 @@ static int read_reg_dma(struct qcom_nand
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@@ -584,7 +830,7 @@ static int read_reg_dma(struct qcom_nand
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* @num_regs: number of registers to write
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*/
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static int write_reg_dma(struct qcom_nand_controller *nandc, int first,
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@ -411,7 +411,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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{
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bool flow_control = false;
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struct nandc_regs *regs = nandc->regs;
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@@ -588,12 +834,29 @@ static int write_reg_dma(struct qcom_nan
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@@ -596,12 +842,29 @@ static int write_reg_dma(struct qcom_nan
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if (first == NAND_FLASH_CMD)
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flow_control = true;
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size = num_regs * sizeof(u32);
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return prep_dma_desc(nandc, false, first, vaddr, size, flow_control);
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@@ -608,8 +871,12 @@ static int write_reg_dma(struct qcom_nan
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@@ -616,8 +879,12 @@ static int write_reg_dma(struct qcom_nan
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* @size: DMA transaction size in bytes
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*/
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static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off,
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return prep_dma_desc(nandc, true, reg_off, vaddr, size, false);
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}
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@@ -622,8 +889,12 @@ static int read_data_dma(struct qcom_nan
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@@ -630,8 +897,12 @@ static int read_data_dma(struct qcom_nan
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* @size: DMA transaction size in bytes
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*/
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static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
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return prep_dma_desc(nandc, false, reg_off, vaddr, size, false);
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}
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@@ -633,14 +904,57 @@ static int write_data_dma(struct qcom_na
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@@ -641,14 +912,57 @@ static int write_data_dma(struct qcom_na
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*/
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static void config_cw_read(struct qcom_nand_controller *nandc)
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{
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@ -533,7 +533,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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}
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/*
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@@ -649,19 +963,20 @@ static void config_cw_read(struct qcom_n
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@@ -657,19 +971,20 @@ static void config_cw_read(struct qcom_n
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*/
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static void config_cw_write_pre(struct qcom_nand_controller *nandc)
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{
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}
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/*
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@@ -675,6 +990,8 @@ static int nandc_param(struct qcom_nand_
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@@ -683,6 +998,8 @@ static int nandc_param(struct qcom_nand_
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struct nand_chip *chip = &host->chip;
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struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
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@ -570,7 +570,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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/*
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* NAND_CMD_PARAM is called before we know much about the FLASH chip
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* in use. we configure the controller to perform a raw read of 512
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@@ -708,9 +1025,13 @@ static int nandc_param(struct qcom_nand_
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@@ -715,9 +1032,13 @@ static int nandc_param(struct qcom_nand_
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nandc_set_reg(nandc, NAND_DEV_CMD1_RESTORE, nandc->cmd1);
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nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
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@ -586,7 +586,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
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nandc->buf_count = 512;
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memset(nandc->data_buffer, 0xff, nandc->buf_count);
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@@ -718,11 +1039,12 @@ static int nandc_param(struct qcom_nand_
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@@ -725,11 +1046,12 @@ static int nandc_param(struct qcom_nand_
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config_cw_read(nandc);
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|
||||
read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
|
||||
|
@ -602,7 +602,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
|
||||
return 0;
|
||||
}
|
||||
@@ -733,6 +1055,8 @@ static int erase_block(struct qcom_nand_
|
||||
@@ -740,6 +1062,8 @@ static int erase_block(struct qcom_nand_
|
||||
struct nand_chip *chip = &host->chip;
|
||||
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
||||
|
||||
|
@ -611,7 +611,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
nandc_set_reg(nandc, NAND_FLASH_CMD,
|
||||
BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
|
||||
nandc_set_reg(nandc, NAND_ADDR0, page_addr);
|
||||
@@ -744,14 +1068,15 @@ static int erase_block(struct qcom_nand_
|
||||
@@ -751,14 +1075,15 @@ static int erase_block(struct qcom_nand_
|
||||
nandc_set_reg(nandc, NAND_FLASH_STATUS, host->clrflashstatus);
|
||||
nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
|
||||
|
||||
|
@ -633,7 +633,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
|
||||
return 0;
|
||||
}
|
||||
@@ -765,16 +1090,19 @@ static int read_id(struct qcom_nand_host
|
||||
@@ -772,16 +1097,19 @@ static int read_id(struct qcom_nand_host
|
||||
if (column == -1)
|
||||
return 0;
|
||||
|
||||
|
@ -657,7 +657,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
|
||||
return 0;
|
||||
}
|
||||
@@ -785,28 +1113,108 @@ static int reset(struct qcom_nand_host *
|
||||
@@ -792,28 +1120,108 @@ static int reset(struct qcom_nand_host *
|
||||
struct nand_chip *chip = &host->chip;
|
||||
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
||||
|
||||
|
@ -771,7 +771,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
|
||||
return 0;
|
||||
}
|
||||
@@ -817,7 +1225,16 @@ static void free_descs(struct qcom_nand_
|
||||
@@ -824,7 +1232,16 @@ static void free_descs(struct qcom_nand_
|
||||
|
||||
list_for_each_entry_safe(desc, n, &nandc->desc_list, node) {
|
||||
list_del(&desc->node);
|
||||
|
@ -789,7 +789,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
kfree(desc);
|
||||
}
|
||||
}
|
||||
@@ -1128,6 +1545,9 @@ static int read_page_ecc(struct qcom_nan
|
||||
@@ -1135,6 +1552,9 @@ static int read_page_ecc(struct qcom_nan
|
||||
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
||||
int i, ret;
|
||||
|
||||
|
@ -799,7 +799,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
/* queue cmd descs for each codeword */
|
||||
for (i = 0; i < ecc->steps; i++) {
|
||||
int data_size, oob_size;
|
||||
@@ -1141,11 +1561,36 @@ static int read_page_ecc(struct qcom_nan
|
||||
@@ -1148,11 +1568,36 @@ static int read_page_ecc(struct qcom_nan
|
||||
oob_size = host->ecc_bytes_hw + host->spare_bytes;
|
||||
}
|
||||
|
||||
|
@ -838,7 +838,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
|
||||
/*
|
||||
* when ecc is enabled, the controller doesn't read the real
|
||||
@@ -1161,7 +1606,7 @@ static int read_page_ecc(struct qcom_nan
|
||||
@@ -1168,7 +1613,7 @@ static int read_page_ecc(struct qcom_nan
|
||||
*oob_buf++ = 0xff;
|
||||
|
||||
read_data_dma(nandc, FLASH_BUF_ACC + data_size,
|
||||
|
@ -847,7 +847,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
}
|
||||
|
||||
if (data_buf)
|
||||
@@ -1200,10 +1645,14 @@ static int copy_last_cw(struct qcom_nand
|
||||
@@ -1207,10 +1652,14 @@ static int copy_last_cw(struct qcom_nand
|
||||
|
||||
set_address(host, host->cw_size * (ecc->steps - 1), page);
|
||||
update_rw_regs(host, 1, true);
|
||||
|
@ -863,7 +863,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
|
||||
ret = submit_descs(nandc);
|
||||
if (ret)
|
||||
@@ -1226,6 +1675,7 @@ static int qcom_nandc_read_page(struct m
|
||||
@@ -1233,6 +1682,7 @@ static int qcom_nandc_read_page(struct m
|
||||
data_buf = buf;
|
||||
oob_buf = oob_required ? chip->oob_poi : NULL;
|
||||
|
||||
|
@ -871,7 +871,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
ret = read_page_ecc(host, data_buf, oob_buf);
|
||||
if (ret) {
|
||||
dev_err(nandc->dev, "failure to read page\n");
|
||||
@@ -1245,13 +1695,19 @@ static int qcom_nandc_read_page_raw(stru
|
||||
@@ -1252,13 +1702,19 @@ static int qcom_nandc_read_page_raw(stru
|
||||
u8 *data_buf, *oob_buf;
|
||||
struct nand_ecc_ctrl *ecc = &chip->ecc;
|
||||
int i, ret;
|
||||
|
@ -891,7 +891,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
for (i = 0; i < ecc->steps; i++) {
|
||||
int data_size1, data_size2, oob_size1, oob_size2;
|
||||
int reg_off = FLASH_BUF_ACC;
|
||||
@@ -1269,21 +1725,49 @@ static int qcom_nandc_read_page_raw(stru
|
||||
@@ -1276,21 +1732,49 @@ static int qcom_nandc_read_page_raw(stru
|
||||
oob_size2 = host->ecc_bytes_hw + host->spare_bytes;
|
||||
}
|
||||
|
||||
|
@ -946,7 +946,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
oob_buf += oob_size2;
|
||||
}
|
||||
|
||||
@@ -1306,6 +1790,7 @@ static int qcom_nandc_read_oob(struct mt
|
||||
@@ -1313,6 +1797,7 @@ static int qcom_nandc_read_oob(struct mt
|
||||
int ret;
|
||||
|
||||
clear_read_regs(nandc);
|
||||
|
@ -954,7 +954,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
|
||||
host->use_ecc = true;
|
||||
set_address(host, 0, page);
|
||||
@@ -1329,6 +1814,7 @@ static int qcom_nandc_write_page(struct
|
||||
@@ -1336,6 +1821,7 @@ static int qcom_nandc_write_page(struct
|
||||
int i, ret;
|
||||
|
||||
clear_read_regs(nandc);
|
||||
|
@ -962,7 +962,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
|
||||
data_buf = (u8 *)buf;
|
||||
oob_buf = chip->oob_poi;
|
||||
@@ -1350,7 +1836,8 @@ static int qcom_nandc_write_page(struct
|
||||
@@ -1357,7 +1843,8 @@ static int qcom_nandc_write_page(struct
|
||||
|
||||
config_cw_write_pre(nandc);
|
||||
|
||||
|
@ -972,7 +972,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
|
||||
/*
|
||||
* when ECC is enabled, we don't really need to write anything
|
||||
@@ -1363,7 +1850,7 @@ static int qcom_nandc_write_page(struct
|
||||
@@ -1370,7 +1857,7 @@ static int qcom_nandc_write_page(struct
|
||||
oob_buf += host->bbm_size;
|
||||
|
||||
write_data_dma(nandc, FLASH_BUF_ACC + data_size,
|
||||
|
@ -981,7 +981,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
}
|
||||
|
||||
config_cw_write_post(nandc);
|
||||
@@ -1393,6 +1880,7 @@ static int qcom_nandc_write_page_raw(str
|
||||
@@ -1400,6 +1887,7 @@ static int qcom_nandc_write_page_raw(str
|
||||
int i, ret;
|
||||
|
||||
clear_read_regs(nandc);
|
||||
|
@ -989,7 +989,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
|
||||
data_buf = (u8 *)buf;
|
||||
oob_buf = chip->oob_poi;
|
||||
@@ -1419,19 +1907,22 @@ static int qcom_nandc_write_page_raw(str
|
||||
@@ -1426,19 +1914,22 @@ static int qcom_nandc_write_page_raw(str
|
||||
|
||||
config_cw_write_pre(nandc);
|
||||
|
||||
|
@ -1016,7 +1016,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
oob_buf += oob_size2;
|
||||
|
||||
config_cw_write_post(nandc);
|
||||
@@ -1467,6 +1958,7 @@ static int qcom_nandc_write_oob(struct m
|
||||
@@ -1474,6 +1965,7 @@ static int qcom_nandc_write_oob(struct m
|
||||
|
||||
host->use_ecc = true;
|
||||
|
||||
|
@ -1024,7 +1024,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
ret = copy_last_cw(host, page);
|
||||
if (ret)
|
||||
return ret;
|
||||
@@ -1486,7 +1978,7 @@ static int qcom_nandc_write_oob(struct m
|
||||
@@ -1493,7 +1985,7 @@ static int qcom_nandc_write_oob(struct m
|
||||
|
||||
config_cw_write_pre(nandc);
|
||||
write_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
|
||||
|
@ -1033,7 +1033,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
config_cw_write_post(nandc);
|
||||
|
||||
ret = submit_descs(nandc);
|
||||
@@ -1524,6 +2016,7 @@ static int qcom_nandc_block_bad(struct m
|
||||
@@ -1531,6 +2023,7 @@ static int qcom_nandc_block_bad(struct m
|
||||
*/
|
||||
host->use_ecc = false;
|
||||
|
||||
|
@ -1041,7 +1041,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
ret = copy_last_cw(host, page);
|
||||
if (ret)
|
||||
goto err;
|
||||
@@ -1554,6 +2047,7 @@ static int qcom_nandc_block_markbad(stru
|
||||
@@ -1561,6 +2054,7 @@ static int qcom_nandc_block_markbad(stru
|
||||
int page, ret, status = 0;
|
||||
|
||||
clear_read_regs(nandc);
|
||||
|
@ -1049,7 +1049,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
|
||||
/*
|
||||
* to mark the BBM as bad, we flash the entire last codeword with 0s.
|
||||
@@ -1570,7 +2064,8 @@ static int qcom_nandc_block_markbad(stru
|
||||
@@ -1577,7 +2071,8 @@ static int qcom_nandc_block_markbad(stru
|
||||
update_rw_regs(host, 1, false);
|
||||
|
||||
config_cw_write_pre(nandc);
|
||||
|
@ -1059,7 +1059,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
config_cw_write_post(nandc);
|
||||
|
||||
ret = submit_descs(nandc);
|
||||
@@ -1930,6 +2425,8 @@ static int qcom_nand_host_setup(struct q
|
||||
@@ -1937,6 +2432,8 @@ static int qcom_nand_host_setup(struct q
|
||||
|
||||
host->clrflashstatus = FS_READY_BSY_N;
|
||||
host->clrreadstatus = 0xc0;
|
||||
|
@ -1068,7 +1068,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
|
||||
dev_dbg(nandc->dev,
|
||||
"cfg0 %x cfg1 %x ecc_buf_cfg %x ecc_bch cfg %x cw_size %d cw_data %d strength %d parity_bytes %d steps %d\n",
|
||||
@@ -2008,6 +2505,12 @@ static int qcom_nandc_alloc(struct qcom_
|
||||
@@ -2015,6 +2512,12 @@ static int qcom_nandc_alloc(struct qcom_
|
||||
dev_err(nandc->dev, "failed to request cmd channel\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
@ -1081,7 +1081,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
}
|
||||
|
||||
INIT_LIST_HEAD(&nandc->desc_list);
|
||||
@@ -2043,6 +2546,9 @@ static void qcom_nandc_unalloc(struct qc
|
||||
@@ -2050,6 +2553,9 @@ static void qcom_nandc_unalloc(struct qc
|
||||
devm_kfree(nandc->dev, nandc->reg_read_buf);
|
||||
}
|
||||
|
||||
|
@ -1091,7 +1091,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
if (nandc->regs)
|
||||
devm_kfree(nandc->dev, nandc->regs);
|
||||
|
||||
@@ -2053,11 +2559,18 @@ static void qcom_nandc_unalloc(struct qc
|
||||
@@ -2060,12 +2566,19 @@ static void qcom_nandc_unalloc(struct qc
|
||||
/* one time setup of a few nand controller registers */
|
||||
static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
|
||||
{
|
||||
|
@ -1099,6 +1099,7 @@ Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
|
|||
+
|
||||
/* kill onenand */
|
||||
nandc_write(nandc, SFLASHC_BURST_CFG, 0);
|
||||
nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
|
||||
|
||||
- /* enable ADM DMA */
|
||||
- nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
|
||||
|
|
|
@ -10,7 +10,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
|
|||
|
||||
--- a/drivers/net/phy/phy_device.c
|
||||
+++ b/drivers/net/phy/phy_device.c
|
||||
@@ -1799,7 +1799,7 @@ static struct phy_driver genphy_driver[]
|
||||
@@ -1804,7 +1804,7 @@ static struct phy_driver genphy_driver[]
|
||||
.config_init = genphy_config_init,
|
||||
.features = PHY_GBIT_FEATURES | SUPPORTED_MII |
|
||||
SUPPORTED_AUI | SUPPORTED_FIBRE |
|
||||
|
|
Loading…
Reference in New Issue