mirror of https://github.com/hak5/openwrt.git
ar71xx: QCA956X: add missing register
Signed-off-by: Henryk Heisig <hyniu@o2.pl>lede-17.01
Henryk Heisig
Matthias Schiffer
parent
7bc25dfa63
commit
e07ee06aad
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@ -686,7 +686,6 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
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case ATH79_SOC_AR7241:
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case ATH79_SOC_AR9330:
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case ATH79_SOC_AR9331:
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case ATH79_SOC_QCA956X:
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case ATH79_SOC_TP9343:
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pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
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break;
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@ -698,6 +697,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
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case ATH79_SOC_AR9342:
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case ATH79_SOC_AR9344:
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case ATH79_SOC_QCA9533:
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case ATH79_SOC_QCA956X:
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switch (pdata->phy_if_mode) {
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case PHY_INTERFACE_MODE_MII:
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case PHY_INTERFACE_MODE_GMII:
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@ -814,6 +814,27 @@ void __init ath79_setup_qca955x_eth_cfg(u32 mask)
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iounmap(base);
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}
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void __init ath79_setup_qca956x_eth_cfg(u32 mask)
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{
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void __iomem *base;
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u32 t;
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base = ioremap(QCA956X_GMAC_BASE, QCA956X_GMAC_SIZE);
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t = __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
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t &= ~(QCA956X_ETH_CFG_SW_ONLY_MODE |
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QCA956X_ETH_CFG_SW_PHY_SWAP);
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t |= mask;
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__raw_writel(t, base + QCA956X_GMAC_REG_ETH_CFG);
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/* flush write */
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__raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
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iounmap(base);
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}
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static int ath79_eth_instance __initdata;
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void __init ath79_register_eth(unsigned int id)
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{
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@ -49,5 +49,6 @@ void ath79_setup_ar933x_phy4_switch(bool mac, bool mdio);
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void ath79_setup_ar934x_eth_cfg(u32 mask);
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void ath79_setup_ar934x_eth_rx_delay(unsigned int rxd, unsigned int rxdv);
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void ath79_setup_qca955x_eth_cfg(u32 mask);
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void ath79_setup_qca956x_eth_cfg(u32 mask);
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#endif /* _ATH79_DEV_ETH_H */
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@ -37,11 +37,13 @@ struct ag71xx_platform_data {
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u8 is_ar724x:1;
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u8 has_ar8216:1;
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u8 use_flow_control:1;
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u8 is_qca956x:1;
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struct ag71xx_switch_platform_data *switch_data;
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void (*ddr_flush)(void);
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void (*set_speed)(int speed);
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void (*update_pll)(u32 pll_10, u32 pll_100, u32 pll_1000);
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u32 fifo_cfg1;
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u32 fifo_cfg2;
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@ -0,0 +1,38 @@
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -157,6 +157,10 @@
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#define QCA956X_EHCI0_BASE 0x1b000000
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#define QCA956X_EHCI1_BASE 0x1b400000
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#define QCA956X_EHCI_SIZE 0x200
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+#define QCA956X_GMAC_SGMII_BASE (AR71XX_APB_BASE + 0x00070000)
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+#define QCA956X_GMAC_SGMII_SIZE 0x64
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+#define QCA956X_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
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+#define QCA956X_PLL_SIZE 0x50
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#define QCA956X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
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#define QCA956X_GMAC_SIZE 0x64
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@@ -404,6 +408,7 @@
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#define QCA956X_PLL_DDR_CONFIG_REG 0x08
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#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
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#define QCA956X_PLL_CLK_CTRL_REG 0x10
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+#define QCA956X_PLL_ETH_XMII_CONTROL_REG 0x30
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#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
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#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
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@@ -1186,4 +1191,16 @@
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#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
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#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
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+/*
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+ * QCA956X GMAC Interface
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+ */
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+
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+#define QCA956X_GMAC_REG_ETH_CFG 0x00
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+
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+#define QCA956X_ETH_CFG_SW_ONLY_MODE BIT(7)
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+#define QCA956X_ETH_CFG_SW_PHY_SWAP BIT(8)
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+#define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(9)
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+#define QCA956X_ETH_CFG_SW_APB_ACCESS BIT(10)
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+#define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
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+
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#endif /* __ASM_MACH_AR71XX_REGS_H */
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@ -20,7 +20,7 @@
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#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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#define AR71XX_UART_SIZE 0x100
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#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
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@@ -218,6 +218,9 @@
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@@ -222,6 +222,9 @@
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#define QCA953X_DDR_REG_FLUSH_PCIE 0xa8
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#define QCA953X_DDR_REG_FLUSH_WMAC 0xac
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@ -48,7 +48,7 @@ functions on the Arduino Yun.
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void __iomem *reg = ath79_gpio_get_function_reg();
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -850,6 +850,7 @@
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@@ -855,6 +855,7 @@
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#define AR71XX_GPIO_REG_INT_PENDING 0x20
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#define AR71XX_GPIO_REG_INT_ENABLE 0x24
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#define AR71XX_GPIO_REG_FUNC 0x28
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@ -56,7 +56,7 @@ functions on the Arduino Yun.
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#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
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#define AR934X_GPIO_REG_OUT_FUNC1 0x30
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@@ -974,6 +975,8 @@
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@@ -979,6 +980,8 @@
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#define AR724X_GPIO_FUNC_UART_EN BIT(1)
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#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
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