ramips: Improve TP-Link Archer C20i support

Improve / finalise TP-Link Archer C20i support.

Signed-off-by: P.Wassi <p.wassi@gmx.at>
lede-17.01
P.Wassi 2016-07-26 06:44:19 +02:00 committed by John Crispin
parent d4abe72cce
commit dbf107cd2b
4 changed files with 49 additions and 5 deletions

View File

@ -78,6 +78,12 @@ broadway)
set_usb_led "$board:red:diskmounted"
set_wifi_led "$board:red:wps_active"
;;
c20i)
ucidef_set_led_switch "lan" "lan" "$board:blue:lan" "switch0" "0x1e"
ucidef_set_led_switch "wan" "wan" "$board:blue:wan" "switch0" "0x01"
set_usb_led "$board:blue:usb" "2-1"
ucidef_set_led_wlan "wlan" "wlan" "$board:blue:wlan" "phy0radio"
;;
c50)
ucidef_set_led_default "power" "power" "tp-link:blue:power" "0"
ucidef_set_led_netdev "lan" "lan" "tp-link:blue:lan" "eth0.2"

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@ -114,6 +114,7 @@ ramips_setup_interfaces()
atp-52b|\
awm002-evb|\
awm003-evb|\
c20i|\
c50|\
dir-645|\
dir-860l-b1|\

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@ -12,20 +12,57 @@
gpio-leds {
compatible = "gpio-leds";
lan {
label = "c20i:blue:lan";
gpios = <&gpio0 1 1>;
};
usb {
label = "c20i:blue:usb";
gpios = <&gpio0 11 1>;
};
wps {
label = "c20i:blue:wps";
gpios = <&gpio1 15 1>;
};
wan {
label = "c20i:blue:wan";
gpios = <&gpio2 0 1>;
};
wlan {
label = "c20i:blue:wlan";
gpios = <&gpio3 0 1>;
};
};
gpio-keys-polled {
compatible = "gpio-keys-polled";
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
poll-interval = <20>;
rfkill {
label = "rfkill";
gpios = <&gpio0 2 1>;
linux,code = <0xf7>;
};
reset_wps {
label = "reset_wps";
gpios = <&gpio0 13 1>;
linux,code = <0x198>;
};
};
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&spi0 {
status = "okay";
@ -73,7 +110,7 @@
&pinctrl {
state_default: pinctrl0 {
gpio {
ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd";
ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd", "ephy", "spi refclk";
ralink,function = "gpio";
};
};
@ -81,7 +118,6 @@
&ethernet {
pinctrl-names = "default";
pinctrl-0 = <&ephy_pins>;
mtd-mac-address = <&rom 0xf100>;
mediatek,portmap = "wllll";
};

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@ -194,6 +194,7 @@ CONFIG_SPI_MASTER=y
CONFIG_SPI_RT2880=y
CONFIG_SRCU=y
CONFIG_SWCONFIG=y
CONFIG_SWCONFIG_LEDS=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_CPU_MIPS32_R2=y