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@ -13,7 +13,7 @@
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/* ============================= */
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--- a/src/drv_vmmc_bbd.c
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+++ b/src/drv_vmmc_bbd.c
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@@ -1072,7 +1072,11 @@
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@@ -1072,7 +1072,11 @@ static IFX_int32_t vmmc_BBD_DownloadChCr
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IFX_uint8_t padBytes = 0;
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#endif
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IFX_uint16_t cram_offset, cram_crc,
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@ -88,7 +88,7 @@
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} while(0);
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/**
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@@ -72,11 +34,6 @@
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@@ -72,11 +34,6 @@ do { \
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*/
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#define VMMC_DRIVER_UNLOAD_HOOK(ret) \
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do { \
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@ -141,7 +141,7 @@
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#undef USE_PLAIN_VOICE_FIRMWARE
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#undef PRINT_ON_ERR_INTERRUPT
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@@ -35,8 +36,35 @@
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@@ -35,8 +36,22 @@
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#include "ifxos_interrupt.h"
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#include "ifxos_time.h"
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@ -157,19 +157,6 @@
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+# define ifx_gptu_countvalue_get lq_get_count_value
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+# define ifx_gptu_timer_free lq_free_timer
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+
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+# define IFX_MPS_SRAM IFXMIPS_MPS_SRAM
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+# define IFX_MPS_AD0ENR IFXMIPS_MPS_AD0ENR
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+# define IFX_MPS_AD1ENR IFXMIPS_MPS_AD1ENR
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+# define IFX_MPS_VC0ENR IFXMIPS_MPS_VC0ENR
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+# define IFX_MPS_SAD0SR IFXMIPS_MPS_SAD0SR
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+# define IFX_MPS_RAD0SR IFXMIPS_MPS_RAD0SR
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+# define IFX_MPS_RAD1SR IFXMIPS_MPS_RAD1SR
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+# define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
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+# define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
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+# define IFX_MPS_RVC0SR IFXMIPS_MPS_RVC0SR
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+# define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
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+
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+# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
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+
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+# define bsp_mask_and_ack_irq lq_mask_and_ack_irq
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+#else
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@ -179,80 +166,123 @@
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#include "drv_mps_vmmc.h"
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#include "drv_mps_vmmc_dbg.h"
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@@ -201,7 +229,8 @@
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@@ -98,6 +113,9 @@ extern IFX_void_t bsp_mask_and_ack_irq (
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extern IFX_void_t mask_and_ack_danube_irq (IFX_uint32_t irq_nr);
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#endif /* */
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+
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+extern void sys_hw_setup (void);
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+
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extern IFXOS_event_t fw_ready_evt;
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/* callback function to free all data buffers currently used by voice FW */
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IFX_void_t (*ifx_mps_bufman_freeall)(IFX_void_t) = IFX_NULL;
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@@ -201,7 +219,8 @@ IFX_boolean_t ifx_mps_ext_bufman ()
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*/
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IFX_void_t *ifx_mps_fastbuf_malloc (IFX_size_t size, IFX_int32_t priority)
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{
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- IFX_uint32_t ptr, flags;
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+ unsigned long flags;
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+ IFXOS_INTSTAT flags;
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+ IFX_uint32_t ptr;
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IFX_int32_t index = fastbuf_index;
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if (fastbuf_initialized == 0)
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@@ -255,7 +284,7 @@
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@@ -255,7 +274,7 @@ IFX_void_t *ifx_mps_fastbuf_malloc (IFX_
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*/
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IFX_void_t ifx_mps_fastbuf_free (const IFX_void_t * ptr)
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{
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- IFX_uint32_t flags;
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+ unsigned long flags;
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+ IFXOS_INTSTAT flags;
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IFX_int32_t index = fastbuf_index;
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IFXOS_LOCKINT (flags);
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@@ -451,7 +480,7 @@
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@@ -451,7 +470,7 @@ static mps_buffer_state_e ifx_mps_bufman
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*/
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static IFX_int32_t ifx_mps_bufman_inc_level (IFX_uint32_t value)
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{
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- IFX_uint32_t flags;
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+ unsigned long flags;
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+ IFXOS_INTSTAT flags;
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if (mps_buffer.buf_level + value > MPS_BUFFER_MAX_LEVEL)
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{
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@@ -478,7 +507,7 @@
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@@ -478,7 +497,7 @@ static IFX_int32_t ifx_mps_bufman_inc_le
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*/
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static IFX_int32_t ifx_mps_bufman_dec_level (IFX_uint32_t value)
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{
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- IFX_uint32_t flags;
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+ unsigned long flags;
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+ IFXOS_INTSTAT flags;
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if (mps_buffer.buf_level < value)
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{
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@@ -946,7 +975,7 @@
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@@ -630,7 +649,7 @@ IFX_int32_t ifx_mps_bufman_buf_provide (
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mem_seg_ptr[i] =
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(IFX_uint32_t *) CPHYSADDR ((IFX_uint32_t) mps_buffer.
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malloc (segment_size, FASTBUF_FW_OWNED));
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- if (mem_seg_ptr[i] == CPHYSADDR (IFX_NULL))
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+ if (mem_seg_ptr[i] == (IFX_uint32_t *)CPHYSADDR (IFX_NULL))
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|
{
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|
|
TRACE (MPS, DBG_LEVEL_HIGH,
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|
|
("%s(): cannot allocate buffer\n", __FUNCTION__));
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|
@@ -946,7 +965,7 @@ IFX_int32_t ifx_mps_common_open (mps_com
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mps_mbx_dev * pMBDev, IFX_int32_t bcommand,
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IFX_boolean_t from_kernel)
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{
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- IFX_uint32_t flags;
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+ unsigned long flags;
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+ IFXOS_INTSTAT flags;
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IFXOS_LOCKINT (flags);
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@@ -1062,7 +1091,7 @@
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@@ -1062,7 +1081,7 @@ IFX_int32_t ifx_mps_common_close (mps_mb
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IFX_void_t ifx_mps_release_structures (mps_comm_dev * pDev)
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{
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IFX_int32_t count;
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- IFX_uint32_t flags;
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+ unsigned long flags;
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+ IFXOS_INTSTAT flags;
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IFXOS_LOCKINT (flags);
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IFXOS_BlockFree (pFW_img_data);
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|
@@ -1558,7 +1587,7 @@
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@@ -1111,7 +1130,7 @@ IFX_uint32_t ifx_mps_init_structures (mp
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/* Initialize MPS main structure */
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memset ((IFX_void_t *) pDev, 0, sizeof (mps_comm_dev));
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|
- pDev->base_global = (mps_mbx_reg *) IFX_MPS_SRAM;
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+ pDev->base_global = (mps_mbx_reg *) IFXMIPS_MPS_SRAM;
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|
pDev->flags = 0x00000000;
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|
|
MBX_Memory = pDev->base_global;
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|
@@ -1119,9 +1138,11 @@ IFX_uint32_t ifx_mps_init_structures (mp
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for MBX communication. These are: mailbox base address, mailbox size, *
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|
mailbox read index and mailbox write index. for command and voice
|
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mailbox, * upstream and downstream direction. */
|
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|
|
- memset ((IFX_void_t *) MBX_Memory, /* avoid to overwrite CPU boot
|
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|
|
- registers */
|
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|
|
- 0, sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));
|
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|
|
+ memset (
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|
+ /* avoid to overwrite CPU boot registers */
|
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|
|
+ (IFX_void_t *) MBX_Memory,
|
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|
|
+ 0,
|
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|
|
+ sizeof (mps_mbx_reg) - 2 * sizeof (mps_boot_cfg_reg));
|
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|
|
|
MBX_Memory->MBX_UPSTR_CMD_BASE =
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|
|
|
(IFX_uint32_t *) CPHYSADDR ((IFX_uint32_t) MBX_UPSTRM_CMD_FIFO_BASE);
|
|
|
|
|
MBX_Memory->MBX_UPSTR_CMD_SIZE = MBX_CMD_FIFO_SIZE;
|
|
|
|
|
@@ -1558,7 +1579,7 @@ IFX_int32_t ifx_mps_mbx_read_message (mp
|
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|
|
|
IFX_uint32_t * bytes)
|
|
|
|
|
{
|
|
|
|
|
IFX_int32_t i, ret;
|
|
|
|
|
- IFX_uint32_t flags;
|
|
|
|
|
+ unsigned long flags;
|
|
|
|
|
+ IFXOS_INTSTAT flags;
|
|
|
|
|
|
|
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|
|
IFXOS_LOCKINT (flags);
|
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|
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|
|
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|
|
@@ -1768,7 +1797,7 @@
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|
@@ -1768,7 +1789,7 @@ IFX_int32_t ifx_mps_mbx_write_message (m
|
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|
|
{
|
|
|
|
|
mps_fifo *mbx;
|
|
|
|
|
IFX_uint32_t i;
|
|
|
|
|
- IFX_uint32_t flags;
|
|
|
|
|
+ unsigned long flags;
|
|
|
|
|
+ IFXOS_INTSTAT flags;
|
|
|
|
|
IFX_int32_t retval = -EAGAIN;
|
|
|
|
|
IFX_int32_t retries = 0;
|
|
|
|
|
IFX_uint32_t word = 0;
|
|
|
|
|
@@ -2163,6 +2192,7 @@
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|
@@ -2163,6 +2184,7 @@ IFX_int32_t ifx_mps_mbx_write_cmd (mps_m
|
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|
|
|
TRACE (MPS, DBG_LEVEL_HIGH,
|
|
|
|
|
("%s(): Invalid device ID %d !\n", __FUNCTION__, pMBDev->devID));
|
|
|
|
|
}
|
|
|
|
|
@ -260,16 +290,16 @@
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|
|
return retval;
|
|
|
|
|
}
|
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|
|
|
|
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|
|
@@ -2186,7 +2216,7 @@
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|
|
@@ -2186,7 +2208,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
|
|
|
|
|
mps_mbx_dev *mbx_dev;
|
|
|
|
|
MbxMsg_s msg;
|
|
|
|
|
IFX_uint32_t bytes_read = 0;
|
|
|
|
|
- IFX_uint32_t flags;
|
|
|
|
|
+ unsigned long flags;
|
|
|
|
|
+ IFXOS_INTSTAT flags;
|
|
|
|
|
IFX_int32_t ret;
|
|
|
|
|
|
|
|
|
|
/* set pointer to data upstream mailbox, no matter if 0,1,2 or 3 because
|
|
|
|
|
@@ -2277,7 +2307,7 @@
|
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|
|
@@ -2277,7 +2299,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
|
|
|
|
|
{
|
|
|
|
|
ifx_mps_bufman_dec_level (1);
|
|
|
|
|
if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
|
|
|
|
|
@ -278,7 +308,7 @@
|
|
|
|
|
{
|
|
|
|
|
IFXOS_LockRelease (pMPSDev->provide_buffer);
|
|
|
|
|
}
|
|
|
|
|
@@ -2320,7 +2350,7 @@
|
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|
|
@@ -2320,7 +2342,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
|
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|
|
|
#endif /* CONFIG_PROC_FS */
|
|
|
|
|
ifx_mps_bufman_dec_level (1);
|
|
|
|
|
if ((ifx_mps_bufman_get_level () <= mps_buffer.buf_threshold) &&
|
|
|
|
|
@ -287,43 +317,59 @@
|
|
|
|
|
{
|
|
|
|
|
IFXOS_LockRelease (pMPSDev->provide_buffer);
|
|
|
|
|
}
|
|
|
|
|
@@ -2350,7 +2380,7 @@
|
|
|
|
|
@@ -2350,7 +2372,7 @@ IFX_void_t ifx_mps_mbx_data_upstream (IF
|
|
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|
|
IFX_void_t ifx_mps_mbx_cmd_upstream (IFX_ulong_t dummy)
|
|
|
|
|
{
|
|
|
|
|
mps_fifo *mbx;
|
|
|
|
|
- IFX_uint32_t flags;
|
|
|
|
|
+ unsigned long flags;
|
|
|
|
|
+ IFXOS_INTSTAT flags;
|
|
|
|
|
|
|
|
|
|
/* set pointer to upstream command mailbox */
|
|
|
|
|
mbx = &(pMPSDev->cmd_upstrm_fifo);
|
|
|
|
|
@@ -2398,7 +2428,7 @@
|
|
|
|
|
@@ -2398,7 +2420,7 @@ IFX_void_t ifx_mps_mbx_event_upstream (I
|
|
|
|
|
mps_event_msg msg;
|
|
|
|
|
IFX_int32_t length = 0;
|
|
|
|
|
IFX_int32_t read_length = 0;
|
|
|
|
|
- IFX_uint32_t flags;
|
|
|
|
|
+ unsigned long flags;
|
|
|
|
|
+ IFXOS_INTSTAT flags;
|
|
|
|
|
|
|
|
|
|
/* set pointer to upstream event mailbox */
|
|
|
|
|
mbx = &(pMPSDev->event_upstrm_fifo);
|
|
|
|
|
@@ -2641,7 +2671,7 @@
|
|
|
|
|
@@ -2613,6 +2635,7 @@ IFX_void_t ifx_mps_enable_mailbox_int ()
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
*IFX_MPS_AD0ENR = Ad0Reg.val;
|
|
|
|
|
+
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
@@ -2641,7 +2664,7 @@ IFX_void_t ifx_mps_disable_mailbox_int (
|
|
|
|
|
*/
|
|
|
|
|
IFX_void_t ifx_mps_dd_mbx_int_enable (IFX_void_t)
|
|
|
|
|
{
|
|
|
|
|
- IFX_uint32_t flags;
|
|
|
|
|
+ unsigned long flags;
|
|
|
|
|
+ IFXOS_INTSTAT flags;
|
|
|
|
|
MPS_Ad0Reg_u Ad0Reg;
|
|
|
|
|
|
|
|
|
|
IFXOS_LOCKINT (flags);
|
|
|
|
|
@@ -2667,7 +2697,7 @@
|
|
|
|
|
@@ -2667,7 +2690,7 @@ IFX_void_t ifx_mps_dd_mbx_int_enable (IF
|
|
|
|
|
*/
|
|
|
|
|
IFX_void_t ifx_mps_dd_mbx_int_disable (IFX_void_t)
|
|
|
|
|
{
|
|
|
|
|
- IFX_uint32_t flags;
|
|
|
|
|
+ unsigned long flags;
|
|
|
|
|
+ IFXOS_INTSTAT flags;
|
|
|
|
|
MPS_Ad0Reg_u Ad0Reg;
|
|
|
|
|
|
|
|
|
|
IFXOS_LOCKINT (flags);
|
|
|
|
|
@@ -2794,6 +2824,7 @@
|
|
|
|
|
@@ -2732,7 +2755,6 @@ irqreturn_t ifx_mps_ad0_irq (IFX_int32_t
|
|
|
|
|
#else /* */
|
|
|
|
|
mask_and_ack_danube_irq (irq);
|
|
|
|
|
#endif /* */
|
|
|
|
|
-
|
|
|
|
|
/* FW is up and ready to process commands */
|
|
|
|
|
if (MPS_Ad0StatusReg.fld.dl_end)
|
|
|
|
|
{
|
|
|
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@@ -2794,6 +2816,7 @@ irqreturn_t ifx_mps_ad0_irq (IFX_int32_t
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}
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}
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@ -331,7 +377,21 @@
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if (MPS_Ad0StatusReg.fld.du_mbx)
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{
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#ifdef CONFIG_PROC_FS
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@@ -3087,7 +3118,8 @@
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@@ -2938,12 +2961,12 @@ irqreturn_t ifx_mps_vc_irq (IFX_int32_t
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IFX_MPS_CVC0SR[chan] = MPS_VCStatusReg.val;
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/* handle only enabled interrupts */
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MPS_VCStatusReg.val &= IFX_MPS_VC0ENR[chan];
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-
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#ifdef LINUX_2_6
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bsp_mask_and_ack_irq (irq);
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#else /* */
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mask_and_ack_danube_irq (irq);
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#endif /* */
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+
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pMPSDev->event.MPS_VCStatReg[chan].val = MPS_VCStatusReg.val;
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#ifdef PRINT_ON_ERR_INTERRUPT
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if (MPS_VCStatusReg.fld.rcv_ov)
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@@ -3087,7 +3110,8 @@ IFX_int32_t ifx_mps_get_fw_version (IFX_
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*/
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IFX_return_t ifx_mps_init_gpt ()
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{
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@ -341,6 +401,14 @@
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IFX_ulong_t count;
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#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
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timer = TIMER1A;
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@@ -3160,6 +3184,7 @@ IFX_void_t ifx_mps_shutdown_gpt (IFX_voi
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#else /* Danube */
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timer = TIMER1B;
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#endif /* SYSTEM_AR9 || SYSTEM_VR9 */
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+
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ifx_gptu_timer_free (timer);
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}
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--- a/src/mps/drv_mps_vmmc_danube.c
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+++ b/src/mps/drv_mps_vmmc_danube.c
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@@ -32,9 +32,21 @@
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@ -368,7 +436,7 @@
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#include "drv_mps_vmmc.h"
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#include "drv_mps_vmmc_dbg.h"
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@@ -71,6 +83,20 @@
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@@ -71,6 +83,20 @@ IFX_void_t ifx_mps_release (IFX_void_t);
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/* Local function definition */
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/* ============================= */
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@ -389,7 +457,7 @@
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/******************************************************************************
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* DANUBE Specific Routines
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******************************************************************************/
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@@ -130,6 +156,15 @@
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@@ -130,6 +156,15 @@ IFX_int32_t ifx_mps_download_firmware (m
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}
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/* check if FW image fits in available memory space */
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@ -405,7 +473,7 @@
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if (mem > ifx_get_cp1_size())
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{
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TRACE (MPS, DBG_LEVEL_HIGH,
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@@ -137,6 +172,7 @@
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@@ -137,6 +172,7 @@ IFX_int32_t ifx_mps_download_firmware (m
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__FILE__, __func__, __LINE__, mem, ifx_get_cp1_size()));
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return IFX_ERROR;
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}
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@ -413,7 +481,7 @@
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/* reset the driver */
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ifx_mps_reset ();
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@@ -357,7 +393,7 @@
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@@ -357,7 +393,7 @@ IFX_void_t ifx_mps_release (IFX_void_t)
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*/
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IFX_void_t ifx_mps_wdog_expiry()
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{
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@ -424,7 +492,7 @@
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/* recalculate and compare the firmware checksum */
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--- a/src/mps/drv_mps_vmmc_device.h
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+++ b/src/mps/drv_mps_vmmc_device.h
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@@ -16,8 +16,15 @@
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@@ -16,8 +16,58 @@
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declarations.
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*******************************************************************************/
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@ -435,97 +503,11 @@
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+# include <irq.h>
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+# include <xway/xway.h>
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+# include <gpio.h>
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+#else
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+# include <asm/ifx/ifx_regs.h>
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+# include <asm/ifx_vpe.h>
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+#endif
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/* ============================= */
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/* MPS Common defines */
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--- a/src/mps/drv_mps_vmmc_linux.c
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+++ b/src/mps/drv_mps_vmmc_linux.c
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@@ -40,10 +40,28 @@
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#include <linux/moduleparam.h>
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#endif /* */
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-
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-#include <asm/ifx/irq.h>
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-#include <asm/ifx/ifx_regs.h>
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-#include <asm/ifx_vpe.h>
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+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
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+#include "drv_vmmc_init.h"
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+# include <lantiq.h>
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+# include <irq.h>
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+
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+# define IFX_MPS_AD0ENR IFXMIPS_MPS_AD0ENR
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+# define IFX_MPS_AD1ENR IFXMIPS_MPS_AD1ENR
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+# define IFX_MPS_RAD0SR IFXMIPS_MPS_RAD0SR
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+# define IFX_MPS_RAD1SR IFXMIPS_MPS_RAD1SR
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+# define IFX_MPS_VC0ENR IFXMIPS_MPS_VC0ENR
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+# define IFX_MPS_RVC0SR IFXMIPS_MPS_RVC0SR
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+
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+# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
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+# define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18)
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+# define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19)
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+#define LQ_ICU_BASE_ADDR (KSEG1 | 0x1F880200)
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+# define IFX_ICU_IM4_IER (LQ_ICU_BASE_ADDR + 0x00A8)
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+#else
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+# include <asm/ifx/irq.h>
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+# include <asm/ifx/ifx_regs.h>
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+# include <asm/ifx_vpe.h>
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+#endif
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/* lib_ifxos headers */
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#include "ifx_types.h"
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@@ -915,7 +933,7 @@
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#endif /* MPS_FIFO_BLOCKING_WRITE */
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case FIO_MPS_GET_STATUS:
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{
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- IFX_uint32_t flags;
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+ unsigned long flags;
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/* get the status of the channel */
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if (!from_kernel)
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@@ -949,7 +967,7 @@
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#if CONFIG_MPS_HISTORY_SIZE > 0
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case FIO_MPS_GET_CMD_HISTORY:
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{
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- IFX_uint32_t flags;
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+ unsigned long flags;
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if (from_kernel)
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{
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@@ -1641,6 +1659,7 @@
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sprintf (buf + len, " minLv: \t %8d\n",
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ifx_mps_dev.voice_mb[i].upstrm_fifo->min_space);
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}
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+
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return len;
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}
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--- a/src/drv_vmmc_init.h
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+++ b/src/drv_vmmc_init.h
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@@ -53,4 +53,41 @@
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extern IFX_int32_t VMMC_DeviceDriverStart(IFX_void_t);
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extern IFX_void_t VMMC_DeviceDriverStop(IFX_void_t);
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+
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+#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
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+#define IFXMIPS_MPS_SRAM ((u32 *)(KSEG1 + 0x1F200000))
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+
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+#define IFXMIPS_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
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+#define IFXMIPS_MPS_CHIPID ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0344))
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+#define IFXMIPS_MPS_VC0ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0000))
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+#define IFXMIPS_MPS_VC1ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0004))
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+#define IFXMIPS_MPS_VC2ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0008))
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+#define IFXMIPS_MPS_VC3ENR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x000C))
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+#define IFXMIPS_MPS_RVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0010))
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+#define IFXMIPS_MPS_RVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0014))
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+#define IFXMIPS_MPS_RVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0018))
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+#define IFXMIPS_MPS_RVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x001C))
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+#define IFXMIPS_MPS_SVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0020))
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+#define IFXMIPS_MPS_SVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0024))
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+#define IFXMIPS_MPS_SVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0028))
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+#define IFXMIPS_MPS_SVC3SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x002C))
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+#define IFXMIPS_MPS_CVC0SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0030))
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+#define IFXMIPS_MPS_CVC1SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0034))
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+#define IFXMIPS_MPS_CVC2SR ((u32 *)(IFXMIPS_MPS_BASE_ADDR + 0x0038))
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@ -545,8 +527,228 @@
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+#define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value) ((((1 << 16) - 1) & (value)) << 12)
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+#define IFXMIPS_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1))
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+#define IFXMIPS_MPS_CHIPID_MANID_SET(value) ((((1 << 10) - 1) & (value)) << 1)
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+#else
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+# include <asm/ifx/ifx_regs.h>
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+# include <asm/ifx_vpe.h>
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+#endif
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+/* MPS register */
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+# define IFX_MPS_AD0ENR IFXMIPS_MPS_AD0ENR
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+# define IFX_MPS_AD1ENR IFXMIPS_MPS_AD1ENR
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+# define IFX_MPS_RAD0SR IFXMIPS_MPS_RAD0SR
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+# define IFX_MPS_RAD1SR IFXMIPS_MPS_RAD1SR
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+# define IFX_MPS_VC0ENR IFXMIPS_MPS_VC0ENR
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+# define IFX_MPS_RVC0SR IFXMIPS_MPS_RVC0SR
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+# define IFX_MPS_CVC0SR IFXMIPS_MPS_CVC0SR
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+# define IFX_MPS_CAD0SR IFXMIPS_MPS_CAD0SR
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+# define IFX_MPS_CAD1SR IFXMIPS_MPS_CAD1SR
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+# define IFX_MPS_CVC1SR IFXMIPS_MPS_CVC1SR
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+# define IFX_MPS_CVC2SR IFXMIPS_MPS_CVC2SR
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+# define IFX_MPS_CVC3SR IFXMIPS_MPS_CVC3SR
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+# define IFX_MPS_SAD0SR IFXMIPS_MPS_SAD0SR
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+/* interrupt vectors */
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+# define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
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+# define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18)
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+# define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19)
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+# define IFX_ICU_IM4_IER IFXMIPS_ICU_IM4_IER
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/* ============================= */
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/* MPS Common defines */
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@@ -26,32 +76,28 @@
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#define MPS_BASEADDRESS 0xBF107000
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#define MPS_RAD0SR MPS_BASEADDRESS + 0x0004
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-#define MPS_RAD0SR_DU (1<<0)
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-#define MPS_RAD0SR_CU (1<<1)
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-
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#define MBX_BASEADDRESS 0xBF200000
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#define VCPU_BASEADDRESS 0xBF208000 /* 0xBF108000 */
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/*---------------------------------------------------------------------------*/
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+#if !defined(CONFIG_LANTIQ)
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+/* enabling interrupts is done with request_irq by the BSP
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+ The related code should not be needed anymore */
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#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
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/* TODO: doublecheck - IM4 or different! */
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#define MPS_INTERRUPTS_ENABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) |= X;
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#define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) &= ~X;
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-#define MPS_INTERRUPTS_CLEAR(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_ISR) = X;
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-#define MPS_INTERRUPTS_SET(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IRSR) = X;/* |= ? */
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#else /* Danube */
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/* TODO: possibly needs to be changed to IM4 !!!!!! */
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#ifdef LINUX_2_6
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#define MPS_INTERRUPTS_ENABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) |= X;
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#define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IER) &= ~X;
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-#define MPS_INTERRUPTS_CLEAR(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_ISR) = X;
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-#define MPS_INTERRUPTS_SET(X) *((volatile IFX_uint32_t*) IFX_ICU_IM4_IRSR) = X;/* |= ? */
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#else /* */
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#define MPS_INTERRUPTS_ENABLE(X) *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IER) |= X;
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#define MPS_INTERRUPTS_DISABLE(X) *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IER) &= ~X;
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-#define MPS_INTERRUPTS_CLEAR(X) *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_ISR) = X;
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-#define MPS_INTERRUPTS_SET(X) *((volatile IFX_uint32_t*) DANUBE_ICU_IM5_IRSR) = X;/* |= ? */
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#endif /* LINUX_2_6 */
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#endif /* SYSTEM_AR9 || SYSTEM_VR9 */
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+#endif /* !defined(CONFIG_LANTIQ) */
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+
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#endif /* _DRV_VMMC_INIT_H */
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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@@ -142,53 +188,9 @@
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#if defined(SYSTEM_AR9) || defined(SYSTEM_VR9)
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/* ***** Amazon-S specific defines ***** */
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#define IFX_MPS_Base AMAZON_S_MPS
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-
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-//#define IFX_MPS_CHIPID AMAZON_S_MPS_CHIPID
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-//#define IFX_MPS_CHIPID_VERSION_GET AMAZON_S_MPS_CHIPID_VERSION_GET
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-
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-//#define IFX_MPS_AD0ENR AMAZON_S_MPS_AD0ENR
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-//#define IFX_MPS_AD1ENR AMAZON_S_MPS_AD1ENR
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-//#define IFX_MPS_VC0ENR AMAZON_S_MPS_VC0ENR
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-//#define IFX_MPS_SAD0SR AMAZON_S_MPS_SAD0SR
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-//#define IFX_MPS_RAD0SR AMAZON_S_MPS_RAD0SR
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-//#define IFX_MPS_CAD0SR AMAZON_S_MPS_CAD0SR
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-//#define IFX_MPS_RAD1SR AMAZON_S_MPS_RAD1SR
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-//#define IFX_MPS_CAD1SR AMAZON_S_MPS_CAD1SR
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-//#define IFX_MPS_RVC0SR AMAZON_S_MPS_RVC0SR
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-//#define IFX_MPS_CVC0SR AMAZON_S_MPS_CVC0SR
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-//#define IFX_MPS_CVC1SR AMAZON_S_MPS_CVC1SR
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-//#define IFX_MPS_CVC2SR AMAZON_S_MPS_CVC2SR
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-//#define IFX_MPS_CVC3SR AMAZON_S_MPS_CVC3SR
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-
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-//#define IFX_MPS_SRAM AMAZON_S_MPS_SRAM
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#else /* */
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/* ***** DANUBE specific defines ***** */
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#define IFX_MPS_Base DANUBE_MPS
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-
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-//#define IFX_MPS_CHIPID DANUBE_MPS_CHIPID
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-//#define IFX_MPS_CHIPID_VERSION_GET DANUBE_MPS_CHIPID_VERSION_GET
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-//#define IFX_MPS_CHIPID_VERSION_SET DANUBE_MPS_CHIPID_VERSION_SET
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-//#define IFX_MPS_CHIPID_PARTNUM_GET DANUBE_MPS_CHIPID_PARTNUM_GET
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-//#define IFX_MPS_CHIPID_PARTNUM_SET DANUBE_MPS_CHIPID_PARTNUM_SET
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-//#define IFX_MPS_CHIPID_MANID_GET DANUBE_MPS_CHIPID_MANID_GET
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-//#define IFX_MPS_CHIPID_MANID_SET DANUBE_MPS_CHIPID_MANID_SET
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-//#define IFX_MPS_SUBVER DANUBE_MPS_SUBVER
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-
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-//#define IFX_MPS_AD0ENR DANUBE_MPS_AD0ENR
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-//#define IFX_MPS_AD1ENR DANUBE_MPS_AD1ENR
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-//#define IFX_MPS_VC0ENR DANUBE_MPS_VC0ENR
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-//#define IFX_MPS_SAD0SR DANUBE_MPS_SAD0SR
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-//#define IFX_MPS_RAD0SR DANUBE_MPS_RAD0SR
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-//#define IFX_MPS_CAD0SR DANUBE_MPS_CAD0SR
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|
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-//#define IFX_MPS_RAD1SR DANUBE_MPS_RAD1SR
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-//#define IFX_MPS_CAD1SR DANUBE_MPS_CAD1SR
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|
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-//#define IFX_MPS_RVC0SR DANUBE_MPS_RVC0SR
|
|
|
|
|
-//#define IFX_MPS_CVC0SR DANUBE_MPS_CVC0SR
|
|
|
|
|
-//#define IFX_MPS_CVC1SR DANUBE_MPS_CVC1SR
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|
|
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-//#define IFX_MPS_CVC2SR DANUBE_MPS_CVC2SR
|
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-//#define IFX_MPS_CVC3SR DANUBE_MPS_CVC3SR
|
|
|
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|
-
|
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|
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|
-//#define IFX_MPS_SRAM DANUBE_MPS_SRAM
|
|
|
|
|
#endif /* SYSTEM_AR9 || SYSTEM_VR9 */
|
|
|
|
|
typedef enum
|
|
|
|
|
{
|
|
|
|
|
--- a/src/mps/drv_mps_vmmc_linux.c
|
|
|
|
|
+++ b/src/mps/drv_mps_vmmc_linux.c
|
|
|
|
|
@@ -19,11 +19,16 @@
|
|
|
|
|
#include "drv_config.h"
|
|
|
|
|
|
|
|
|
|
#include "drv_mps_version.h"
|
|
|
|
|
+#include <linux/version.h>
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_DEBUG_MINI_BOOT
|
|
|
|
|
#define IKOS_MINI_BOOT
|
|
|
|
|
#endif /* */
|
|
|
|
|
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,33))
|
|
|
|
|
+#include <linux/autoconf.h>
|
|
|
|
|
+#else
|
|
|
|
|
#include <generated/autoconf.h>
|
|
|
|
|
+#endif
|
|
|
|
|
#include <linux/module.h>
|
|
|
|
|
#include <linux/init.h>
|
|
|
|
|
#include <linux/poll.h>
|
|
|
|
|
@@ -34,16 +39,27 @@
|
|
|
|
|
#include <linux/delay.h>
|
|
|
|
|
#include <linux/interrupt.h>
|
|
|
|
|
#ifdef LINUX_2_6
|
|
|
|
|
+#ifndef UTS_RELEASE
|
|
|
|
|
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 33)
|
|
|
|
|
+#include <linux/utsrelease.h>
|
|
|
|
|
+#else
|
|
|
|
|
#include <generated/utsrelease.h>
|
|
|
|
|
+#endif
|
|
|
|
|
+#endif /* UTC_RELEASE */
|
|
|
|
|
#else /* */
|
|
|
|
|
#include <linux/uts.h>
|
|
|
|
|
#include <linux/moduleparam.h>
|
|
|
|
|
#endif /* */
|
|
|
|
|
|
|
|
|
|
-
|
|
|
|
|
-#include <asm/ifx/irq.h>
|
|
|
|
|
-#include <asm/ifx/ifx_regs.h>
|
|
|
|
|
-#include <asm/ifx_vpe.h>
|
|
|
|
|
+#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,28))
|
|
|
|
|
+#include "drv_vmmc_init.h"
|
|
|
|
|
+# include <lantiq.h>
|
|
|
|
|
+# include <irq.h>
|
|
|
|
|
+#else
|
|
|
|
|
+# include <asm/ifx/irq.h>
|
|
|
|
|
+# include <asm/ifx/ifx_regs.h>
|
|
|
|
|
+# include <asm/ifx_vpe.h>
|
|
|
|
|
+#endif
|
|
|
|
|
|
|
|
|
|
/* lib_ifxos headers */
|
|
|
|
|
#include "ifx_types.h"
|
|
|
|
|
@@ -915,7 +931,7 @@ IFX_int32_t ifx_mps_ioctl (struct inode
|
|
|
|
|
#endif /* MPS_FIFO_BLOCKING_WRITE */
|
|
|
|
|
case FIO_MPS_GET_STATUS:
|
|
|
|
|
{
|
|
|
|
|
- IFX_uint32_t flags;
|
|
|
|
|
+ unsigned long flags;
|
|
|
|
|
|
|
|
|
|
/* get the status of the channel */
|
|
|
|
|
if (!from_kernel)
|
|
|
|
|
@@ -949,7 +965,7 @@ IFX_int32_t ifx_mps_ioctl (struct inode
|
|
|
|
|
#if CONFIG_MPS_HISTORY_SIZE > 0
|
|
|
|
|
case FIO_MPS_GET_CMD_HISTORY:
|
|
|
|
|
{
|
|
|
|
|
- IFX_uint32_t flags;
|
|
|
|
|
+ unsigned long flags;
|
|
|
|
|
|
|
|
|
|
if (from_kernel)
|
|
|
|
|
{
|
|
|
|
|
@@ -1641,6 +1657,7 @@ IFX_int32_t ifx_mps_get_status_proc (IFX
|
|
|
|
|
sprintf (buf + len, " minLv: \t %8d\n",
|
|
|
|
|
ifx_mps_dev.voice_mb[i].upstrm_fifo->min_space);
|
|
|
|
|
}
|
|
|
|
|
+
|
|
|
|
|
return len;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
@@ -2247,9 +2264,11 @@ IFX_int32_t __init ifx_mps_init_module (
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
+#if !defined(CONFIG_LANTIQ)
|
|
|
|
|
+ /** \todo This is handled already with request_irq, remove */
|
|
|
|
|
/* Enable all MPS Interrupts at ICU0 */
|
|
|
|
|
MPS_INTERRUPTS_ENABLE (0x0000FF80);
|
|
|
|
|
-
|
|
|
|
|
+#endif
|
|
|
|
|
/* enable mailbox interrupts */
|
|
|
|
|
ifx_mps_enable_mailbox_int ();
|
|
|
|
|
/* init FW ready event */
|
|
|
|
|
@@ -2377,9 +2396,11 @@ ifx_mps_cleanup_module (IFX_void_t)
|
|
|
|
|
/* disable mailbox interrupts */
|
|
|
|
|
ifx_mps_disable_mailbox_int ();
|
|
|
|
|
|
|
|
|
|
+#if !defined(CONFIG_LANTIQ)
|
|
|
|
|
/* disable Interrupts at ICU0 */
|
|
|
|
|
- MPS_INTERRUPTS_DISABLE (DANUBE_MPS_AD0_IR4); /* Disable DFE/AFE 0 Interrupts
|
|
|
|
|
- */
|
|
|
|
|
+ /* Disable DFE/AFE 0 Interrupts*/
|
|
|
|
|
+ MPS_INTERRUPTS_DISABLE (DANUBE_MPS_AD0_IR4);
|
|
|
|
|
+#endif
|
|
|
|
|
|
|
|
|
|
/* disable all MPS interrupts */
|
|
|
|
|
ifx_mps_disable_all_int ();
|
|
|
|
|
--- a/src/drv_vmmc_ioctl.c
|
|
|
|
|
+++ b/src/drv_vmmc_ioctl.c
|
|
|
|
|
@@ -18,6 +18,7 @@
|
|
|
|
|
|
John Crispin