mirror of https://github.com/hak5/openwrt.git
generic: ar8216: fix unknown packet flooding for ar8229/ar8236
ar8229 and ar8236 don't allow unknown unicast/multicast frames and
broadcast frames to be flooded to cpu port. This isn't desired behavior
for swconfig as we treat it as a standalone switch.
Current code doesn't enable unicast frame flooding for ar8229 and uses
wrong setup for ar8236. This commit fixes both of them by enabling port
0 flooding for all unknown frames.
Fixes: FS#2848
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
(cherry picked from commit 47f17b0662
)
openwrt-19.07
parent
429e4490c4
commit
d9244a1b5b
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@ -943,10 +943,14 @@ ar8229_init_globals(struct ar8xxx_priv *priv)
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ar8xxx_reg_set(priv, AR8229_REG_QM_CTRL,
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AR8229_QM_CTRL_ARP_EN);
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/* Enable Broadcast/Multicast frames transmitted to the CPU */
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/*
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* Enable Broadcast/unknown multicast and unicast frames
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* transmitted to the CPU port.
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*/
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ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
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AR8229_FLOOD_MASK_BC_DP(0) |
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AR8229_FLOOD_MASK_MC_DP(0));
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AR8229_FLOOD_MASK_MC_DP(0) |
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AR8229_FLOOD_MASK_UC_DP(0));
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/* setup MTU */
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ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
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@ -1008,7 +1012,7 @@ ar7240sw_init_globals(struct ar8xxx_priv *priv)
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/* Enable Broadcast frames transmitted to the CPU */
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ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
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AR8236_FM_CPU_BROADCAST_EN);
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AR8216_FM_CPU_BROADCAST_EN);
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/* setup MTU */
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ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
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@ -1074,9 +1078,14 @@ ar8236_init_globals(struct ar8xxx_priv *priv)
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ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
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AR8236_ATU_CTRL_RES);
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/* enable cpu port to receive multicast and broadcast frames */
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/*
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* Enable Broadcast/unknown multicast and unicast frames
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* transmitted to the CPU port.
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*/
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ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
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AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
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AR8229_FLOOD_MASK_BC_DP(0) |
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AR8229_FLOOD_MASK_MC_DP(0) |
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AR8229_FLOOD_MASK_UC_DP(0));
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/* Enable MIB counters */
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ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
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@ -56,10 +56,10 @@
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#define AR8216_REG_FLOOD_MASK 0x002C
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#define AR8216_FM_UNI_DEST_PORTS BITS(0, 6)
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#define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6)
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#define AR8216_FM_CPU_BROADCAST_EN BIT(26)
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#define AR8229_FLOOD_MASK_UC_DP(_p) BIT(_p)
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#define AR8229_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
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#define AR8229_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
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#define AR8236_FM_CPU_BROADCAST_EN BIT(26)
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#define AR8236_FM_CPU_BCAST_FWD_EN BIT(25)
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#define AR8216_REG_GLOBAL_CTRL 0x0030
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#define AR8216_GCTRL_MTU BITS(0, 11)
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