mirror of https://github.com/hak5/openwrt.git
ar7: clocks setup (prerequisite for dsl/usb) and misc cleanups.
SVN-Revision: 6693lede-17.01
Eugene Konev
parent
8c2cf394a3
commit
d81c7f76b9
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@ -9,7 +9,7 @@ CONFIG_BASE_SMALL=0
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# CONFIG_BCM43XX is not set
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# CONFIG_BLK_DEV_INITRD is not set
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CONFIG_BOOT_ELF32=y
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CONFIG_CMDLINE="console=ttyS0,38400n8r root=/dev/mtdblock3 init=/etc/preinit"
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CONFIG_CMDLINE="console=ttyS0,38400n8r init=/etc/preinit"
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CONFIG_CPMAC=y
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# CONFIG_CPU_BIG_ENDIAN is not set
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CONFIG_CPU_HAS_LLSC=y
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@ -7,6 +7,7 @@ obj-y := \
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time.o \
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platform.o \
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gpio.o \
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clock.o \
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vlynq.o
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obj-$(CONFIG_PCI) += \
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@ -0,0 +1,362 @@
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/*
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* $Id$
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*
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* Copyright (C) 2007 OpenWrt.org
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#include <asm/ar7/ar7.h>
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#define BOOT_PLL_SOURCE_MASK 0x3
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#define CPU_PLL_SOURCE_SHIFT 16
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#define BUS_PLL_SOURCE_SHIFT 14
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#define USB_PLL_SOURCE_SHIFT 18
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#define DSP_PLL_SOURCE_SHIFT 22
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#define BOOT_PLL_SOURCE_AFE 0
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#define BOOT_PLL_SOURCE_BUS 0
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#define BOOT_PLL_SOURCE_REF 1
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#define BOOT_PLL_SOURCE_XTAL 2
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#define BOOT_PLL_SOURCE_CPU 3
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#define BOOT_PLL_BYPASS 0x00000020
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#define BOOT_PLL_ASYNC_MODE 0x02000000
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#define BOOT_PLL_2TO1_MODE 0x00008000
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struct tnetd7300_clock {
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u32 ctrl;
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#define PREDIV_MASK 0x001f0000
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#define PREDIV_SHIFT 16
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#define POSTDIV_MASK 0x0000001f
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u32 unused1[3];
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u32 pll;
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#define MUL_MASK 0x0000f000
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#define MUL_SHIFT 12
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#define PLL_MODE_MASK 0x00000001
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#define PLL_NDIV 0x00000800
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#define PLL_DIV 0x00000002
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#define PLL_STATUS 0x00000001
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u32 unused2[3];
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} __attribute__ ((packed));
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struct tnetd7300_clocks {
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struct tnetd7300_clock bus;
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struct tnetd7300_clock cpu;
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struct tnetd7300_clock usb;
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struct tnetd7300_clock dsp;
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} __attribute__ ((packed));
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struct tnetd7200_clock {
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u32 ctrl;
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u32 unused1[3];
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#define DIVISOR_ENABLE_MASK 0x00008000
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u32 mul;
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u32 prediv;
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u32 postdiv;
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u32 unused2[7];
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u32 cmd;
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u32 status;
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u32 cmden;
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u32 padding[15];
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};
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struct tnetd7200_clocks {
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struct tnetd7200_clock cpu;
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struct tnetd7200_clock dsp;
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struct tnetd7200_clock usb;
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};
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int ar7_afe_clock = 35328000;
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int ar7_ref_clock = 25000000;
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int ar7_xtal_clock = 24000000;
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int ar7_cpu_clock = 150000000;
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EXPORT_SYMBOL(ar7_cpu_clock);
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int ar7_bus_clock = 125000000;
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EXPORT_SYMBOL(ar7_bus_clock);
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int ar7_dsp_clock = 0;
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EXPORT_SYMBOL(ar7_dsp_clock);
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static int gcd(int x, int y)
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{
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if (x > y)
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return (x % y) ? gcd(y, x % y) : y;
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return (y % x) ? gcd(x, y % x) : x;
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}
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static inline int ABS(int x)
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{
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return (x >= 0) ? x : -x;
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}
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static void approximate(int base, int target, int *prediv,
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int *postdiv, int *mul)
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{
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int i, j, k, freq, res = target;
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for (i = 1; i <= 16; i++) {
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for (j = 1; j <= 32; j++) {
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for (k = 1; k <= 32; k++) {
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freq = ABS(base / j * i / k - target);
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if (freq < res) {
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res = freq;
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*mul = i;
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*prediv = j;
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*postdiv = k;
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}
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}
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}
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}
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}
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static void calculate(int base, int target, int *prediv, int *postdiv,
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int *mul)
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{
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int tmp_gcd, tmp_base, tmp_freq;
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for (*prediv = 1; *prediv <= 32; (*prediv)++) {
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tmp_base = base / *prediv;
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tmp_gcd = gcd(target, tmp_base);
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*mul = target / tmp_gcd;
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*postdiv = tmp_base / tmp_gcd;
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if ((*mul < 1) || (*mul >= 16))
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continue;
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if ((*postdiv > 0) & (*postdiv <= 32))
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break;
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}
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if (base / (*prediv) * (*mul) / (*postdiv) != target) {
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approximate(base, target, prediv, postdiv, mul);
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tmp_freq = base / (*prediv) * (*mul) / (*postdiv);
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printk(KERN_WARNING
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"Adjusted requested frequency %d to %d\n",
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target, tmp_freq);
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}
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printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
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*prediv, *postdiv, *mul);
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}
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static int tnetd7300_dsp_clock(void)
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{
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u32 didr1, didr2;
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u8 rev = ar7_chip_rev();
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didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
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didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
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if (didr2 & (1 << 23))
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return 0;
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if ((rev >= 0x23) && (rev != 0x57))
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return 250000000;
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if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
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> 4208000)
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return 250000000;
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return 0;
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}
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static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
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u32 *bootcr, u32 bus_clock)
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{
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int product;
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int base_clock = ar7_ref_clock;
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int prediv = ((clock->ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
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int postdiv = (clock->ctrl & POSTDIV_MASK) + 1;
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int divisor = prediv * postdiv;
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int mul = ((clock->pll & MUL_MASK) >> MUL_SHIFT) + 1;
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switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
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case BOOT_PLL_SOURCE_BUS:
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base_clock = bus_clock;
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break;
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case BOOT_PLL_SOURCE_REF:
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base_clock = ar7_ref_clock;
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break;
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case BOOT_PLL_SOURCE_XTAL:
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base_clock = ar7_xtal_clock;
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break;
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case BOOT_PLL_SOURCE_CPU:
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base_clock = ar7_cpu_clock;
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break;
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}
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if (*bootcr & BOOT_PLL_BYPASS)
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return base_clock / divisor;
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if ((clock->pll & PLL_MODE_MASK) == 0)
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return (base_clock >> (mul / 16 + 1)) / divisor;
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if ((clock->pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
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product = (mul & 1) ?
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(base_clock * mul) >> 1 :
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(base_clock * (mul - 1)) >> 2;
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return product / divisor;
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}
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if (mul == 16)
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return base_clock / divisor;
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return base_clock * mul / divisor;
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}
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static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
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u32 *bootcr, u32 frequency)
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{
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volatile u32 status;
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int prediv, postdiv, mul;
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int base_clock = ar7_bus_clock;
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switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
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case BOOT_PLL_SOURCE_BUS:
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base_clock = ar7_bus_clock;
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break;
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case BOOT_PLL_SOURCE_REF:
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base_clock = ar7_ref_clock;
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break;
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case BOOT_PLL_SOURCE_XTAL:
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base_clock = ar7_xtal_clock;
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break;
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case BOOT_PLL_SOURCE_CPU:
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base_clock = ar7_cpu_clock;
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break;
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}
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calculate(base_clock, frequency, &prediv, &postdiv, &mul);
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clock->ctrl = ((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1);
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mdelay(1);
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clock->pll = 4;
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do {
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status = clock->pll;
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} while (status & PLL_STATUS);
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clock->pll = ((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e;
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mdelay(75);
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}
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static void __init tnetd7300_init_clocks(void)
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{
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u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
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struct tnetd7300_clocks *clocks = (struct tnetd7300_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x20, sizeof(struct tnetd7300_clocks));
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ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
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&clocks->bus, bootcr,
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ar7_afe_clock);
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if (*bootcr & BOOT_PLL_ASYNC_MODE) {
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ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
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&clocks->cpu,
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bootcr, ar7_afe_clock);
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} else {
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ar7_cpu_clock = ar7_bus_clock;
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}
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tnetd7300_set_clock(USB_PLL_SOURCE_SHIFT, &clocks->usb,
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bootcr, 48000000);
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if (ar7_dsp_clock == 250000000)
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tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
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bootcr, ar7_dsp_clock);
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iounmap(clocks);
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iounmap(bootcr);
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}
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static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
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u32 *bootcr, u32 bus_clock)
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{
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int divisor = ((clock->prediv & 0x1f) + 1) *
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((clock->postdiv & 0x1f) + 1);
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if (*bootcr & BOOT_PLL_BYPASS)
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return base / divisor;
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return base * ((clock->mul & 0xf) + 1) / divisor;
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}
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static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
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u32 *bootcr, u32 frequency)
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{
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volatile u32 status;
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int prediv, postdiv, mul;
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calculate(base, frequency, &prediv, &postdiv, &mul);
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clock->ctrl = 0;
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clock->prediv = DIVISOR_ENABLE_MASK | prediv;
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clock->mul = mul;
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mdelay(1);
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do {
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status = clock->status;
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} while (status & PLL_STATUS);
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clock->postdiv = DIVISOR_ENABLE_MASK | postdiv;
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clock->cmden = 1;
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clock->cmd = 1;
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do {
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status = clock->status;
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} while (status & PLL_STATUS);
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clock->ctrl = 1;
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}
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static void __init tnetd7200_init_clocks(void)
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{
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u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
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struct tnetd7200_clocks *clocks = (struct tnetd7200_clocks *)ioremap_nocache(AR7_REGS_POWER + 0x80, sizeof(struct tnetd7200_clocks));
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ar7_cpu_clock = tnetd7200_get_clock(ar7_afe_clock,
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&clocks->cpu,
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bootcr, ar7_afe_clock);
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if (*bootcr & BOOT_PLL_ASYNC_MODE) {
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ar7_bus_clock = 125000000;
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} else {
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if (*bootcr & BOOT_PLL_2TO1_MODE) {
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ar7_bus_clock = ar7_cpu_clock / 2;
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} else {
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ar7_bus_clock = ar7_cpu_clock;
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}
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}
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tnetd7200_set_clock(ar7_ref_clock * 5, &clocks->usb,
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bootcr, 48000000);
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if (ar7_dsp_clock == 250000000)
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tnetd7200_set_clock(ar7_ref_clock, &clocks->dsp,
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bootcr, ar7_dsp_clock);
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iounmap(clocks);
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iounmap(bootcr);
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}
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void __init ar7_init_clocks(void)
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{
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switch (ar7_chip_id()) {
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case AR7_CHIP_7100:
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tnetd7200_init_clocks();
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break;
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case AR7_CHIP_7200:
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#warning FIXME: check revision
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ar7_dsp_clock = 250000000;
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tnetd7200_init_clocks();
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break;
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case AR7_CHIP_7300:
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ar7_dsp_clock = tnetd7300_dsp_clock();
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tnetd7300_init_clocks();
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break;
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default:
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break;
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}
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}
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@ -47,7 +47,7 @@ struct psp_chip_map {
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/* I hate this. No. *I* *HATE* *THIS* */
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static __initdata struct psp_chip_map psp_chip_map[] = {
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{
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.chip = 0x5,
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.chip = AR7_CHIP_7100,
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.names = {
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"dummy", "cpufrequency", "memsize",
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"flashsize", "modetty0", "modetty1", "prompt",
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@ -65,7 +65,7 @@ static __initdata struct psp_chip_map psp_chip_map[] = {
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},
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},
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{
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.chip = 0x18,
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.chip = AR7_CHIP_7200,
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.names = {
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"dummy", "cpufrequency", "memsize",
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"flashsize", "modetty0", "modetty1", "prompt",
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@ -83,7 +83,7 @@ static __initdata struct psp_chip_map psp_chip_map[] = {
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},
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},
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{
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.chip = 0x2b,
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.chip = AR7_CHIP_7300,
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.names = {
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"dummy", "cpufrequency", "memsize",
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"flashsize", "modetty0", "modetty1", "prompt",
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@ -186,7 +186,7 @@ static int __init parse_psp_env(void *start)
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char *src, *dest, *name, *value;
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struct psp_env_var *vars = start;
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chip = get_chip_id();
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chip = ar7_chip_id();
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for (map = psp_chip_map; map->chip; map++)
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if (map->chip == chip)
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break;
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@ -72,13 +72,13 @@ static void ar7_machine_power_off(void)
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const char *get_system_type(void)
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{
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u16 chip_id = get_chip_id();
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u16 chip_id = ar7_chip_id();
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switch (chip_id) {
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case 0x5:
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case AR7_CHIP_7300:
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return "TI AR7 (TNETD7300)";
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case 0x18:
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case AR7_CHIP_7100:
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return "TI AR7 (TNETD7100)";
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case 0x2b:
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case AR7_CHIP_7200:
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return "TI AR7 (TNETD7200)";
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default:
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return "TI AR7 (Unknown)";
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@ -95,6 +95,8 @@ static int __init ar7_init_console(void)
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* given by the bios and saves the command line.
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*/
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extern void ar7_init_clocks(void);
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void __init plat_mem_setup(void)
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{
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unsigned long io_base;
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@ -110,6 +112,7 @@ void __init plat_mem_setup(void)
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set_io_port_base(io_base);
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prom_meminit();
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ar7_init_clocks();
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ioport_resource.start = 0;
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ioport_resource.end = ~0;
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|
@ -70,9 +70,6 @@ typedef struct {
|
|||
static struct semaphore open_semaphore;
|
||||
static unsigned expect_close;
|
||||
|
||||
/* XXX correct? assumed to be sysfreq/2. get this dynamically ... */
|
||||
#define vbus_freq (ar7_bus_freq() / 2)
|
||||
|
||||
/* XXX currently fixed, allows max margin ~68.72 secs */
|
||||
#define prescale_value 0xFFFF
|
||||
|
||||
|
|
@ -143,14 +140,14 @@ static void ar7_wdt_update_margin(int new_margin)
|
|||
{
|
||||
u32 change;
|
||||
|
||||
change = new_margin * (vbus_freq / prescale_value);
|
||||
change = new_margin * (ar7_vbus_freq() / prescale_value);
|
||||
if (change < 1) change = 1;
|
||||
if (change > 0xFFFF) change = 0xFFFF;
|
||||
ar7_wdt_change(change);
|
||||
margin = change * prescale_value / vbus_freq;
|
||||
margin = change * prescale_value / ar7_vbus_freq();
|
||||
printk(KERN_INFO DRVNAME
|
||||
": timer margin %d seconds (prescale %d, change %d, freq %d)\n",
|
||||
margin, prescale_value, change, vbus_freq);
|
||||
margin, prescale_value, change, ar7_vbus_freq());
|
||||
}
|
||||
|
||||
static void ar7_wdt_enable_wdt(void)
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@
|
|||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/bootmem.h>
|
||||
#include <linux/squashfs_fs.h>
|
||||
#include <linux/root_dev.h>
|
||||
|
||||
struct ar7_bin_rec {
|
||||
unsigned int checksum;
|
||||
|
|
@ -108,6 +109,7 @@ static int create_mtd_partitions(struct mtd_info *master,
|
|||
ar7_parts[p - 1].size -= ar7_parts[p].size;
|
||||
ar7_parts[p - 1].mask_flags |= MTD_WRITEABLE;
|
||||
ar7_parts[p++].mask_flags = 0;
|
||||
ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, p - 1);
|
||||
} else {
|
||||
printk("Squashfs not found. Moving rootfs partition to next erase block\n");
|
||||
if ((root_offset % master->erasesize) > 0)
|
||||
|
|
@ -116,6 +118,7 @@ static int create_mtd_partitions(struct mtd_info *master,
|
|||
|
||||
ar7_parts[p].offset = root_offset;
|
||||
ar7_parts[p].size = master->size - root_offset - post_size;
|
||||
ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, p);
|
||||
}
|
||||
*pparts = ar7_parts;
|
||||
return p;
|
||||
|
|
|
|||
|
|
@ -31,12 +31,20 @@
|
|||
#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
|
||||
#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
|
||||
#define AR7_REGS_WDT (AR7_REGS_BASE + 0x0b00)
|
||||
#define AR7_REGS_TIMER0 (AR7_REGS_BASE + 0x0c00)
|
||||
#define AR7_REGS_TIMER1 (AR7_REGS_BASE + 0x0d00)
|
||||
#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
|
||||
#define AR7_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
|
||||
#define AR7_REGS_I2C (AR7_REGS_BASE + 0x1000)
|
||||
#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
|
||||
#define AR7_REGS_DMA (AR7_REGS_BASE + 0x1400)
|
||||
#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
|
||||
#define AR7_REGS_BIST (AR7_REGS_BASE + 0x1700)
|
||||
#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
|
||||
#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1A00)
|
||||
#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1C00)
|
||||
#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1E00)
|
||||
#define AR7_REGS_FSER (AR7_REGS_BASE + 0x2000)
|
||||
#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
|
||||
#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
|
||||
|
||||
|
|
@ -54,6 +62,9 @@
|
|||
|
||||
#define AR7_GPIO_BIT_STATUS_LED 8
|
||||
|
||||
#define AR7_CHIP_7100 0x18
|
||||
#define AR7_CHIP_7200 0x2b
|
||||
#define AR7_CHIP_7300 0x05
|
||||
|
||||
/* Interrupts */
|
||||
#define AR7_IRQ_UART0 15
|
||||
|
|
@ -66,49 +77,52 @@ struct plat_cpmac_data {
|
|||
char dev_addr[6];
|
||||
};
|
||||
|
||||
struct plat_dsl_data {
|
||||
int reset_bit_dsl;
|
||||
int reset_bit_sar;
|
||||
};
|
||||
|
||||
extern char *prom_getenv(char *envname);
|
||||
|
||||
/* A bunch of small bit-toggling functions */
|
||||
static inline u32 get_chip_id(void)
|
||||
extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
|
||||
|
||||
static inline u16 ar7_chip_id(void)
|
||||
{
|
||||
return *((u16 *)KSEG1ADDR(AR7_REGS_GPIO + 0x14));
|
||||
return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
|
||||
}
|
||||
|
||||
static inline u8 ar7_chip_rev(void)
|
||||
{
|
||||
return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
|
||||
}
|
||||
|
||||
static inline int ar7_cpu_freq(void)
|
||||
{
|
||||
u16 chip_id = get_chip_id();
|
||||
switch (chip_id) {
|
||||
case 0x5:
|
||||
return 150000000;
|
||||
case 0x18:
|
||||
case 0x2b:
|
||||
return 211968000;
|
||||
default:
|
||||
return 150000000;
|
||||
}
|
||||
return ar7_cpu_clock;
|
||||
}
|
||||
|
||||
static inline int ar7_bus_freq(void)
|
||||
{
|
||||
u16 chip_id = get_chip_id();
|
||||
switch (chip_id) {
|
||||
case 0x5:
|
||||
return 125000000;
|
||||
case 0x18:
|
||||
case 0x2b:
|
||||
return 105984000;
|
||||
default:
|
||||
return 125000000;
|
||||
}
|
||||
return ar7_bus_clock;
|
||||
}
|
||||
|
||||
static inline int ar7_vbus_freq(void)
|
||||
{
|
||||
return ar7_bus_clock / 2;
|
||||
}
|
||||
#define ar7_cpmac_freq ar7_vbus_freq
|
||||
|
||||
static inline int ar7_dsp_freq(void)
|
||||
{
|
||||
return ar7_dsp_clock;
|
||||
}
|
||||
#define ar7_cpmac_freq ar7_bus_freq
|
||||
|
||||
static inline int ar7_has_high_cpmac(void)
|
||||
{
|
||||
u16 chip_id = get_chip_id();
|
||||
u16 chip_id = ar7_chip_id();
|
||||
switch (chip_id) {
|
||||
case 0x18:
|
||||
case 0x2b:
|
||||
case AR7_CHIP_7100:
|
||||
case AR7_CHIP_7200:
|
||||
return 0;
|
||||
default:
|
||||
return 1;
|
||||
|
|
@ -118,15 +132,15 @@ static inline int ar7_has_high_cpmac(void)
|
|||
|
||||
static inline void ar7_device_enable(u32 bit)
|
||||
{
|
||||
volatile u32 *reset_reg = (u32 *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
|
||||
*reset_reg |= (1 << bit);
|
||||
void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
|
||||
writel(readl(reset_reg) | (1 << bit), reset_reg);
|
||||
mdelay(20);
|
||||
}
|
||||
|
||||
static inline void ar7_device_disable(u32 bit)
|
||||
{
|
||||
volatile u32 *reset_reg = (u32 *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
|
||||
*reset_reg &= ~(1 << bit);
|
||||
void *reset_reg = (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
|
||||
writel(readl(reset_reg) & ~(1 << bit), reset_reg);
|
||||
mdelay(20);
|
||||
}
|
||||
|
||||
|
|
@ -138,15 +152,15 @@ static inline void ar7_device_reset(u32 bit)
|
|||
|
||||
static inline void ar7_device_on(u32 bit)
|
||||
{
|
||||
volatile u32 *power_reg = (u32 *)KSEG1ADDR(AR7_REGS_POWER);
|
||||
*power_reg |= (1 << bit);
|
||||
void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
|
||||
writel(readl(power_reg) | (1 << bit), power_reg);
|
||||
mdelay(20);
|
||||
}
|
||||
|
||||
static inline void ar7_device_off(u32 bit)
|
||||
{
|
||||
volatile u32 *power_reg = (u32 *)KSEG1ADDR(AR7_REGS_POWER);
|
||||
*power_reg &= ~(1 << bit);
|
||||
void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
|
||||
writel(readl(power_reg) & ~(1 << bit), power_reg);
|
||||
mdelay(20);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ static inline int gpio_direction_input(unsigned gpio)
|
|||
if (gpio >= AR7_GPIO_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
__raw_writel(__raw_readl(gpio_dir) | (1 << gpio), gpio_dir);
|
||||
writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -47,7 +47,7 @@ static inline int gpio_direction_output(unsigned gpio)
|
|||
if (gpio >= AR7_GPIO_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
__raw_writel(__raw_readl(gpio_dir) & ~(1 << gpio), gpio_dir);
|
||||
writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -59,7 +59,7 @@ static inline int gpio_get_value(unsigned gpio)
|
|||
if (gpio >= AR7_GPIO_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
return ((__raw_readl(gpio_in) & (1 << gpio)) != 0);
|
||||
return ((readl(gpio_in) & (1 << gpio)) != 0);
|
||||
}
|
||||
|
||||
static inline void gpio_set_value(unsigned gpio, int value)
|
||||
|
|
@ -70,10 +70,10 @@ static inline void gpio_set_value(unsigned gpio, int value)
|
|||
if (gpio >= AR7_GPIO_MAX)
|
||||
return;
|
||||
|
||||
tmp = __raw_readl(gpio_out) & ~(1 << gpio);
|
||||
tmp = readl(gpio_out) & ~(1 << gpio);
|
||||
if (value)
|
||||
tmp |= 1 << gpio;
|
||||
__raw_writel(tmp, gpio_out);
|
||||
writel(tmp, gpio_out);
|
||||
}
|
||||
|
||||
static inline int gpio_to_irq(unsigned gpio)
|
||||
|
|
@ -94,7 +94,7 @@ static inline int ar7_gpio_enable(unsigned gpio)
|
|||
if (gpio >= AR7_GPIO_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
__raw_writel(__raw_readl(gpio_en) | (1 << gpio), gpio_en);
|
||||
writel(readl(gpio_en) | (1 << gpio), gpio_en);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -106,7 +106,7 @@ static inline int ar7_gpio_disable(unsigned gpio)
|
|||
if (gpio >= AR7_GPIO_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
__raw_writel(__raw_readl(gpio_en) & ~(1 << gpio), gpio_en);
|
||||
writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue