ipq40xx: OpenMesh A42 overhaul

Sort the soc entries in the dts by address and use dtc labels whenever
possible.

Adjust the DTS files, the OpenMesh A42 is actually an IPQ4018 and not an
IPQ4019.

Signed-off-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
openwrt-18.06
Christian Lamparter 2018-03-10 09:55:18 +01:00 committed by Mathias Kresin
parent a44d435c1d
commit d0e9621404
3 changed files with 81 additions and 88 deletions

View File

@ -47,6 +47,14 @@
};
soc {
mdio@90000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
tcsr@194b000 {
/* select hostmode */
compatible = "qcom,tcsr";
@ -55,87 +63,34 @@
status = "ok";
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1949000 {
compatible = "qcom,tcsr";
reg = <0x1949000 0x100>;
qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
};
ess_tcsr@1953000 {
compatible = "qcom,tcsr";
reg = <0x1953000 0x1000>;
qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
};
tcsr@1957000 {
compatible = "qcom,tcsr";
reg = <0x1957000 0x100>;
qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
};
pinctrl@1000000 {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pinmux {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
};
pinmux_cs {
function = "gpio";
pins = "gpio54";
};
pinconf {
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pinconf_cs {
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
blsp_dma: dma@7884000 {
usb2: usb2@60f8800 {
status = "ok";
};
spi_0: spi@78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "ok";
cs-gpios = <&tlmm 54 0>;
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
/* partitions are passed via bootloader */
};
};
serial@78af000 {
pinctrl-0 = <&serial_pins>;
pinctrl-names = "default";
status = "ok";
};
cryptobam: dma@8e04000 {
status = "ok";
};
crypto@8e3a000 {
status = "ok";
};
@ -144,39 +99,13 @@
status = "ok";
};
usb2_hs_phy: hsphy@a8000 {
status = "ok";
};
usb2: usb2@60f8800 {
status = "ok";
};
mdio@90000 {
status = "okay";
};
ess-switch@c000000 {
status = "okay";
};
ess-psgmii@98000 {
status = "okay";
};
edma@c080000 {
status = "okay";
};
wifi@a000000 {
status = "okay";
qcom,ath10k-calibration-variant = "OM-A42";
};
wifi@a800000 {
status = "okay";
qcom,ath10k-calibration-variant = "OM-A42";
};
};
gpio-keys {
@ -227,6 +156,56 @@
};
};
&tlmm {
serial_pins: serial_pinmux {
mux {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;
};
};
spi_0_pins: spi_0_pinmux {
pin {
function = "blsp_spi0";
pins = "gpio55", "gpio56", "gpio57";
drive-strength = <12>;
bias-disable;
};
pin_cs {
function = "gpio";
pins = "gpio54";
drive-strength = <2>;
bias-disable;
output-high;
};
};
};
&blsp_dma {
status = "ok";
};
&spi_0 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "ok";
cs-gpios = <&tlmm 54 0>;
m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <24000000>;
/* partitions are passed via bootloader */
};
};
&cryptobam {
status = "ok";
};
&gmac0 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
@ -242,3 +221,17 @@
qcom,forced_duplex = <1>;
vlan_tag = <1 0x10>;
};
&usb2_hs_phy {
status = "ok";
};
&wifi0 {
status = "okay";
qcom,ath10k-calibration-variant = "OM-A42";
};
&wifi1 {
status = "okay";
qcom,ath10k-calibration-variant = "OM-A42";
};

View File

@ -61,7 +61,7 @@ TARGET_DEVICES += glinet_gl-b1300
define Device/openmesh_a42
$(call Device/FitImageLzma)
DEVICE_DTS := qcom-ipq4019-a42
DEVICE_DTS := qcom-ipq4018-a42
BLOCKSIZE := 64k
SUPPORTED_DEVICES := openmesh,a42
DEVICE_TITLE := OpenMesh A42

View File

@ -14,7 +14,7 @@ Signed-off-by: John Crispin <john@phrozen.org>
qcom-apq8074-dragonboard.dtb \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
+ qcom-ipq4019-a42.dtb \
+ qcom-ipq4018-a42.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c1.dtb \
+ qcom-ipq4019-fritz4040.dtb \