mirror of https://github.com/hak5/openwrt.git
imx6: pcie driver fixups
Add upstream patches needed for PCIe through a switch. Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 38511lede-17.01
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From 93d2b52fe73294d59bbce3a6d4da031647b1f3b2 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Tue, 22 Oct 2013 15:56:40 -0700
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Subject: [PATCH] PCI: imx6: remove outbound io/mem ATU region mapping
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The IMX6 iATU is used for address translation between the AXI bus
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address space and PCI address space. This is used for type0 and type1
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config cycles but is not necessary for outbound io/mem regions.
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This patch removes the calls that inappropriately re-configures the ATU
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viewport for outbound memory and IO after config cycles and removes them
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altogether as they are not necessary.
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This resolves issues with PCI devices behind switches and has been tested with
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a Gige device behind a PLX PEX860x switch.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/pci/host/pcie-designware.c | 41 +++---------------------------------
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1 file changed, 3 insertions(+), 38 deletions(-)
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--- a/drivers/pci/host/pcie-designware.c
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+++ b/drivers/pci/host/pcie-designware.c
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@@ -43,7 +43,6 @@
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#define PCIE_ATU_VIEWPORT 0x900
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#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
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#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
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-#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
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#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
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#define PCIE_ATU_CR1 0x904
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#define PCIE_ATU_TYPE_MEM (0x0 << 0)
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@@ -264,8 +263,8 @@ static void dw_pcie_prog_viewport_cfg0(s
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static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
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{
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- /* Program viewport 1 : OUTBOUND : CFG1 */
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- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
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+ /* Program viewport 0 : OUTBOUND : CFG1 */
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+ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_VIEWPORT);
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dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
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dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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@@ -275,38 +274,8 @@ static void dw_pcie_prog_viewport_cfg1(s
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PCIE_ATU_LIMIT);
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dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
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dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
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-}
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-
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-static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
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-{
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- /* Program viewport 0 : OUTBOUND : MEM */
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- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
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- PCIE_ATU_VIEWPORT);
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- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
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- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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- dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
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- dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
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- dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
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- PCIE_ATU_LIMIT);
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- dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
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- dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
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- PCIE_ATU_UPPER_TARGET);
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-}
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-
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-static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
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-{
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- /* Program viewport 1 : OUTBOUND : IO */
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- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
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- PCIE_ATU_VIEWPORT);
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- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
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+ dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
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dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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- dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
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- dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
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- dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
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- PCIE_ATU_LIMIT);
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- dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
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- dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
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- PCIE_ATU_UPPER_TARGET);
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}
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static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
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@@ -322,11 +291,9 @@ static int dw_pcie_rd_other_conf(struct
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if (bus->parent->number == pp->root_bus_nr) {
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dw_pcie_prog_viewport_cfg0(pp, busdev);
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ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
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- dw_pcie_prog_viewport_mem_outbound(pp);
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} else {
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dw_pcie_prog_viewport_cfg1(pp, busdev);
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ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
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- dw_pcie_prog_viewport_io_outbound(pp);
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}
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return ret;
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@@ -345,11 +312,9 @@ static int dw_pcie_wr_other_conf(struct
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if (bus->parent->number == pp->root_bus_nr) {
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dw_pcie_prog_viewport_cfg0(pp, busdev);
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ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
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- dw_pcie_prog_viewport_mem_outbound(pp);
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} else {
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dw_pcie_prog_viewport_cfg1(pp, busdev);
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ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
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- dw_pcie_prog_viewport_io_outbound(pp);
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}
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return ret;
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@ -0,0 +1,24 @@
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From 8c8c877d8490c9d51210ee9e90d5f4d740f115c9 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Thu, 17 Oct 2013 15:55:47 -0700
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Subject: [PATCH 3/5] PCI: imx6: init must be early
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If driver init is not early the pcie port driver gets initalized
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first and interrupts are not configured for the imx6 pcie driver.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/pci/host/pci-imx6.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/pci/host/pci-imx6.c
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+++ b/drivers/pci/host/pci-imx6.c
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@@ -568,7 +568,7 @@ static int __init imx6_pcie_init(void)
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{
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return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe);
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}
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-module_init(imx6_pcie_init);
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+fs_initcall(imx6_pcie_init);
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MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>");
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MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver");
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@ -0,0 +1,36 @@
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From 8590081d5328fe59d4f72aaadafb47fb91d8dc7c Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Thu, 17 Oct 2013 15:52:16 -0700
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Subject: [PATCH] PCI: imx6: fix imprecise abort handler
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An imprecise abort is triggered when a port behind a switch is accessed
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and no device is present. At enumeration, imprecise aborts are not enabled
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thus this ends up getting deferred until the kernel has completed init. At
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that point we must not adjust PC - the handler must do nothing, but a handler
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must exist.
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This fixes random crashes that occur right after freeing init.
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This is against linux-pci/host-imx6.
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Acked-by: Marek Vasut <marex@denx.de>
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Tested-by: Marek Vasut <marex@denx.de>
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/pci/host/pci-imx6.c | 6 ------
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1 file changed, 6 deletions(-)
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--- a/drivers/pci/host/pci-imx6.c
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+++ b/drivers/pci/host/pci-imx6.c
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@@ -200,12 +200,6 @@ static int pcie_phy_write(void __iomem *
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static int imx6q_pcie_abort_handler(unsigned long addr,
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unsigned int fsr, struct pt_regs *regs)
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{
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- /*
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- * If it was an imprecise abort, then we need to correct the
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- * return address to be _after_ the instruction.
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- */
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- if (fsr & (1 << 10))
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- regs->ARM_pc += 4;
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return 0;
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}
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@ -0,0 +1,24 @@
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From 11e8d0ed8cc3b415767961555efc2885791a9391 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Thu, 17 Oct 2013 15:57:28 -0700
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Subject: [PATCH 4/5] PCI: imx6: increase link startup
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An increase link startup delay is required when certain PCI switches are
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attached to the root complex.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/pci/host/pci-imx6.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/pci/host/pci-imx6.c
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+++ b/drivers/pci/host/pci-imx6.c
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@@ -318,7 +318,7 @@ static void imx6_pcie_host_init(struct p
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while (!dw_pcie_link_up(pp)) {
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usleep_range(100, 1000);
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count++;
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- if (count >= 10) {
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+ if (count >= 200) {
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dev_err(pp->dev, "phy link never came up\n");
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dev_dbg(pp->dev,
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"DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
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@ -0,0 +1,28 @@
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From 73a0e49b562da9b06e487fb8e051075543495be5 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Thu, 17 Oct 2013 15:50:48 -0700
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Subject: [PATCH 1/5] PCI: imx6: swizzle interrupts
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/pci/host/pcie-designware.c | 8 +++++++-
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1 file changed, 7 insertions(+), 1 deletion(-)
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--- a/drivers/pci/host/pcie-designware.c
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+++ b/drivers/pci/host/pcie-designware.c
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@@ -676,7 +676,13 @@ int dw_pcie_map_irq(const struct pci_dev
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{
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struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
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- return pp->irq;
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+ switch (pin) {
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+ case 1: return pp->irq;
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+ case 2: return pp->irq - 1;
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+ case 3: return pp->irq - 2;
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+ case 4: return pp->irq - 3;
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+ default: return -1;
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+ }
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}
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static void dw_pcie_add_bus(struct pci_bus *bus)
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@ -26,3 +26,20 @@
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+
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+# PCI host controller drivers
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+obj-y += host/
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--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
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+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
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@@ -208,10 +208,10 @@ clocks and IDs.
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pll4_post_div 193
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pll5_post_div 194
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pll5_video_div 195
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- lvds1_sel 204
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- lvds2_sel 205
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- lvds1_gate 206
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- lvds2_gate 207
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+ lvds1_sel 196
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+ lvds2_sel 197
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+ lvds1_gate 198
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+ lvds2_gate 199
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Examples:
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@ -1,24 +0,0 @@
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--- a/drivers/pci/host/pci-imx6.c
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+++ b/drivers/pci/host/pci-imx6.c
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@@ -200,12 +200,6 @@ static int pcie_phy_write(void __iomem *
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static int imx6q_pcie_abort_handler(unsigned long addr,
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unsigned int fsr, struct pt_regs *regs)
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{
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- /*
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- * If it was an imprecise abort, then we need to correct the
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- * return address to be _after_ the instruction.
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- */
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- if (fsr & (1 << 10))
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- regs->ARM_pc += 4;
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return 0;
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}
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@@ -322,7 +316,7 @@ static void imx6_pcie_host_init(struct p
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IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
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while (!dw_pcie_link_up(pp)) {
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- usleep_range(100, 1000);
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+ usleep_range(2000, 3000);
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count++;
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if (count >= 10) {
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dev_err(pp->dev, "phy link never came up\n");
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